path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.694125                       # Number of seconds simulated
sim_ticks                                51694125219000                       # Number of ticks simulated
final_tick                               51694125219000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 131034                       # Simulator instruction rate (inst/s)
host_op_rate                                   153967                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7136466436                       # Simulator tick rate (ticks/s)
host_mem_usage                                 718208                       # Number of bytes of host memory used
host_seconds                                  7243.66                       # Real time elapsed on the host
sim_insts                                   949163000                       # Number of instructions simulated
sim_ops                                    1115282140                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       407680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       346624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10124864                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         101217736                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        409088                       # Number of bytes read from this memory
system.physmem.bytes_read::total            112505992                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst     10124864                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        10124864                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     94737216                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          94757796                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         6370                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         5416                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             158201                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1581540                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6392                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1757919                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1480269                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1482842                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           7886                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           6705                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               195861                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1958012                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7914                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2176379                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          195861                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             195861                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1832650                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1833048                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1832650                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          7886                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          6705                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              195861                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1958410                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7914                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4009426                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1757919                       # Number of read requests accepted
system.physmem.writeReqs                      1482842                       # Number of write requests accepted
system.physmem.readBursts                     1757919                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1482842                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                112457536                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     49280                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  94756288                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 112505992                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               94757796                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      770                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2248                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         146200                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              105973                       # Per bank write bursts
system.physmem.perBankRdBursts::1              111407                       # Per bank write bursts
system.physmem.perBankRdBursts::2              105002                       # Per bank write bursts
system.physmem.perBankRdBursts::3              101812                       # Per bank write bursts
system.physmem.perBankRdBursts::4              108332                       # Per bank write bursts
system.physmem.perBankRdBursts::5              117578                       # Per bank write bursts
system.physmem.perBankRdBursts::6              104534                       # Per bank write bursts
system.physmem.perBankRdBursts::7              108687                       # Per bank write bursts
system.physmem.perBankRdBursts::8              103848                       # Per bank write bursts
system.physmem.perBankRdBursts::9              161007                       # Per bank write bursts
system.physmem.perBankRdBursts::10             107405                       # Per bank write bursts
system.physmem.perBankRdBursts::11             110838                       # Per bank write bursts
system.physmem.perBankRdBursts::12             104563                       # Per bank write bursts
system.physmem.perBankRdBursts::13             103815                       # Per bank write bursts
system.physmem.perBankRdBursts::14             100822                       # Per bank write bursts
system.physmem.perBankRdBursts::15             101526                       # Per bank write bursts
system.physmem.perBankWrBursts::0               90430                       # Per bank write bursts
system.physmem.perBankWrBursts::1               94995                       # Per bank write bursts
system.physmem.perBankWrBursts::2               91678                       # Per bank write bursts
system.physmem.perBankWrBursts::3               90022                       # Per bank write bursts
system.physmem.perBankWrBursts::4               94229                       # Per bank write bursts
system.physmem.perBankWrBursts::5               99888                       # Per bank write bursts
system.physmem.perBankWrBursts::6               89385                       # Per bank write bursts
system.physmem.perBankWrBursts::7               93994                       # Per bank write bursts
system.physmem.perBankWrBursts::8               90076                       # Per bank write bursts
system.physmem.perBankWrBursts::9               95745                       # Per bank write bursts
system.physmem.perBankWrBursts::10              91874                       # Per bank write bursts
system.physmem.perBankWrBursts::11              95898                       # Per bank write bursts
system.physmem.perBankWrBursts::12              91438                       # Per bank write bursts
system.physmem.perBankWrBursts::13              92023                       # Per bank write bursts
system.physmem.perBankWrBursts::14              89075                       # Per bank write bursts
system.physmem.perBankWrBursts::15              89817                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          27                       # Number of times write queue was full causing retry
system.physmem.totGap                    51694123514000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1757904                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1480269                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1422025                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    328688                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1048                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       351                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       481                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       469                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       492                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       522                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       773                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       906                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      358                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      190                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      168                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      130                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      117                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       93                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       92                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       77                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       57                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    15568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    18151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    71947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    88213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    88480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    88386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    88377                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    91264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    92065                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    94405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    93246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    93724                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    90170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    90391                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   100271                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    88772                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    90332                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    87233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      738                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      700                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      613                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      492                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      399                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      281                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      306                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      271                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       83                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       690739                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      299.988042                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.369601                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     327.443819                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         271817     39.35%     39.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       165800     24.00%     63.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        63380      9.18%     72.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        36796      5.33%     77.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        26984      3.91%     81.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        18833      2.73%     84.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        14857      2.15%     86.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        13605      1.97%     88.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        78667     11.39%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         690739                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         86593                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.291686                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      270.345126                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          86590    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           86593                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         86593                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.097999                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.728630                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        5.809360                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           84121     97.15%     97.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             149      0.17%     97.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             413      0.48%     97.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             198      0.23%     98.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             310      0.36%     98.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             507      0.59%     98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             123      0.14%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              35      0.04%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              41      0.05%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              24      0.03%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              40      0.05%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              29      0.03%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             413      0.48%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              31      0.04%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              42      0.05%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              40      0.05%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               8      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               4      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               4      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            31      0.04%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             4      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           86593                       # Writes before turning the bus around for reads
system.physmem.totQLat                    26847024830                       # Total ticks spent queuing
system.physmem.totMemAccLat               59793568580                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   8785745000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15278.74                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34028.74                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.18                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.83                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.18                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.83                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.96                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1436721                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1110255                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.76                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.99                       # Row buffer hit rate for writes
system.physmem.avgGap                     15951229.82                       # Average gap between requests
system.physmem.pageHitRate                      78.67                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2651919480                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1446979875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                6733888200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4825144080                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3376408666800                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1308234674070                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29868898243500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34569199516005                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.725939                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49688706621634                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1726180300000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    279237825366                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2570067360                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1402318500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                6971827200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4768930080                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3376408666800                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1306063695690                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29870802610500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34568988116130                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.721850                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49691848230640                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1726180300000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    276092348110                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             16                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               260286663                       # Number of BP lookups
system.cpu.branchPred.condPredicted         182589592                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12077009                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            191806323                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               136128585                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             70.971896                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                31602025                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2167880                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    582770                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                582770                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        22376                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       191329                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples       582770                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0          582770    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       582770                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       213705                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 26351.678716                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 22931.447770                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 15578.711548                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       211142     98.80%     98.80% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         2168      1.01%     99.82% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607          149      0.07%     99.88% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          124      0.06%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679           84      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           25      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       213705                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    -58656296                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       -58656296    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    -58656296                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        191330     89.53%     89.53% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         22376     10.47%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       213706                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       582770                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       582770                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       213706                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       213706                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       796476                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    183257458                       # DTB read hits
system.cpu.dtb.read_misses                     481031                       # DTB read misses
system.cpu.dtb.write_hits                   162586595                       # DTB write hits
system.cpu.dtb.write_misses                    101739                       # DTB write misses
system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               47231                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    80339                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1450                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  15121                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     23575                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                183738489                       # DTB read accesses
system.cpu.dtb.write_accesses               162688334                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         345844053                       # DTB hits
system.cpu.dtb.misses                          582770                       # DTB misses
system.cpu.dtb.accesses                     346426823                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    136614                       # Table walker walks requested
system.cpu.itb.walker.walksLong                136614                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1073                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       118911                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       136614                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          136614    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       136614                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       119984                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28837.324143                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 25253.165818                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 17670.490053                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       116985     97.50%     97.50% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071         2707      2.26%     99.76% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607          180      0.15%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           56      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679           24      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           27      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       119984                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    -59528796                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       -59528796    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    -59528796                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        118911     99.11%     99.11% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1073      0.89%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       119984                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136614                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       136614                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       119984                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       119984                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       256598                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    452975639                       # ITB inst hits
system.cpu.itb.inst_misses                     136614                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               47231                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    57698                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    370160                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                453112253                       # ITB inst accesses
system.cpu.itb.hits                         452975639                       # DTB hits
system.cpu.itb.misses                          136614                       # DTB misses
system.cpu.itb.accesses                     453112253                       # DTB accesses
system.cpu.numCycles                       2511767999                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   949163000                       # Number of instructions committed
system.cpu.committedOps                    1115282140                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      97160712                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      7743                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                 100877722288                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.646298                       # CPI: cycles per instruction
system.cpu.ipc                               0.377886                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    19481                       # number of quiesce instructions executed
system.cpu.tickCycles                      1790897935                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       720870064                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements          11142195                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.957822                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           329410408                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          11142707                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.562871                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4277412500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.957822                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999918                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999918                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          385                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1384553632                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1384553632                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    168394927                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       168394927                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    151754199                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      151754199                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       523439                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        523439                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       336679                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       336679                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      4017108                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      4017108                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      4334477                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4334477                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     320149126                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        320149126                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    320672565                       # number of overall hits
system.cpu.dcache.overall_hits::total       320672565                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      6628843                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       6628843                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      4317749                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4317749                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1481094                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1481094                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1245106                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1245106                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       319103                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       319103                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     10946592                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       10946592                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     12427686                       # number of overall misses
system.cpu.dcache.overall_misses::total      12427686                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 107264639000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 107264639000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 153170066000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 153170066000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  58641269000                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  58641269000                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4837420500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   4837420500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       115500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       115500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 260434705000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 260434705000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 260434705000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 260434705000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    175023770                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    175023770                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    156071948                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    156071948                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      2004533                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      2004533                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1581785                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1581785                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4336211                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4336211                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      4334479                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4334479                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    331095718                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    331095718                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    333100251                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    333100251                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037874                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.037874                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027665                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.027665                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.738872                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.738872                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787152                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.787152                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.073590                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.073590                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.033062                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.033062                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037309                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037309                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16181.502413                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16181.502413                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35474.518320                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35474.518320                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 47097.410983                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 47097.410983                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15159.432848                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15159.432848                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        57750                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        57750                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23791.395989                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23791.395989                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20956.009429                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20956.009429                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      8554549                       # number of writebacks
system.cpu.dcache.writebacks::total           8554549                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       817761                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       817761                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1903794                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1903794                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          151                       # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total          151                       # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70489                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        70489                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2721555                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2721555                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2721555                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2721555                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5811082                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5811082                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2413955                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2413955                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1473693                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1473693                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1244955                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1244955                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       248614                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       248614                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      8225037                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      8225037                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9698730                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9698730                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33699                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33699                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67406                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67406                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  87944699500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  87944699500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  80337194000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  80337194000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23656791000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23656791000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  57392051500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  57392051500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3386354500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3386354500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       113500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       113500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168281893500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 168281893500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191938684500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 191938684500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5830552000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5830552000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5692063000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5692063000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11522615000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11522615000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033202                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033202                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015467                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015467                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.735180                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.735180                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787057                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787057                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057334                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057334                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024842                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024842                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029117                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.029117                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15133.962918                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15133.962918                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33280.319641                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33280.319641                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16052.726721                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.726721                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 46099.699588                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 46099.699588                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13620.932450                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13620.932450                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        56750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        56750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20459.712643                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20459.712643                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19790.084320                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19790.084320                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173018.546544                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173018.546544                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168868.869968                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168868.869968                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170943.462006                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170943.462006                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          24575522                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.918698                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           428017274                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          24576034                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             17.416043                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       26893274500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.918698                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999841                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999841                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          118                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         477169361                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        477169361                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    428017274                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       428017274                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     428017274                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        428017274                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    428017274                       # number of overall hits
system.cpu.icache.overall_hits::total       428017274                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     24576044                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      24576044                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     24576044                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       24576044                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     24576044                       # number of overall misses
system.cpu.icache.overall_misses::total      24576044                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 327136040500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 327136040500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 327136040500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 327136040500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 327136040500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 327136040500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    452593318                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    452593318                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    452593318                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    452593318                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    452593318                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    452593318                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054301                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.054301                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.054301                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.054301                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.054301                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.054301                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13311.175733                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13311.175733                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13311.175733                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13311.175733                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13311.175733                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13311.175733                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24576044                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     24576044                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     24576044                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     24576044                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     24576044                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     24576044                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52295                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        52295                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52295                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        52295                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302559997500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 302559997500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302559997500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 302559997500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302559997500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 302559997500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   4042938500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   4042938500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   4042938500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   4042938500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054301                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054301                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054301                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.054301                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054301                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.054301                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12311.175773                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12311.175773                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12311.175773                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12311.175773                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12311.175773                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12311.175773                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77310.230424                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77310.230424                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77310.230424                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77310.230424                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1607082                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65318.726670                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           67354503                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1670310                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            40.324552                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      24502286000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36002.307210                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   335.180696                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   433.791675                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  8203.980766                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 20343.466323                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.549352                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005114                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006619                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.125183                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.310417                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996685                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          219                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63009                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          218                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          524                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2413                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5473                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54554                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003342                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961441                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        587356710                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       587356710                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       972528                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       286301                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1258829                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      8554549                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      8554549                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        10855                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        10855                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1654669                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1654669                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24470106                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     24470106                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7204785                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      7204785                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       700263                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       700263                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       972528                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       286301                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     24470106                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8859454                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        34588389                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       972528                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       286301                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     24470106                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8859454                       # number of overall hits
system.cpu.l2cache.overall_hits::total       34588389                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6370                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5416                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        11786                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        38716                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        38716                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       709953                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       709953                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       105935                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total       105935                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       328366                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       328366                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       544692                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       544692                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         6370                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         5416                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       105935                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1038319                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1156040                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         6370                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         5416                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       105935                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1038319                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1156040                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    553122500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    470413000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1023535500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    578007500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    578007500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       110500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       110500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  58013412000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  58013412000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   8652629500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   8652629500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  27752985500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  27752985500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  47906162000                       # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total  47906162000                       # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    553122500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    470413000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   8652629500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  85766397500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  95442562500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    553122500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    470413000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   8652629500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  85766397500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  95442562500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       978898                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       291717                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1270615                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      8554549                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      8554549                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        49571                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        49571                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2364622                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2364622                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24576041                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     24576041                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7533151                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7533151                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1244955                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1244955                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       978898                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       291717                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     24576041                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9897773                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     35744429                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       978898                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       291717                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     24576041                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9897773                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     35744429                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006507                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.018566                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.009276                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.781021                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.781021                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.300240                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.300240                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004310                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004310                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043589                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043589                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.437519                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.437519                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006507                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018566                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004310                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.104904                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.032342                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006507                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.018566                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004310                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.104904                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.032342                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86832.417582                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86856.166913                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 86843.331071                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14929.421944                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14929.421944                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        55250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        55250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81714.440252                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81714.440252                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81678.666163                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81678.666163                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84518.450449                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84518.450449                       # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 87950.919052                       # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 87950.919052                       # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86832.417582                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86856.166913                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81678.666163                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82601.202039                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82559.913584                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86832.417582                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86856.166913                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81678.666163                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82601.202039                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82559.913584                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1373638                       # number of writebacks
system.cpu.l2cache.writebacks::total          1373638                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6370                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5416                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        11786                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1102                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         1102                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        38716                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        38716                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       709953                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       709953                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       105932                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total       105932                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       328345                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       328345                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       544692                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       544692                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6370                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5416                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       105932                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1038298                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1156016                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6370                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5416                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       105932                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1038298                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1156016                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52295                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33699                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        85994                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52295                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67406                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119701                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    489422500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    416253000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    905675500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    803927500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    803927500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        90500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        90500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  50913882000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  50913882000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7593134000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7593134000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  24468048000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  24468048000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  42459242000                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  42459242000                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    489422500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    416253000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7593134000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  75381930000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  83880739500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    489422500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    416253000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7593134000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  75381930000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  83880739500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3232365500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5409250000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8641615500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5303815500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5303815500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3232365500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10713065500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13945431000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006507                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018566                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.009276                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.781021                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.781021                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.300240                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.300240                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004310                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004310                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043587                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043587                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.437519                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.437519                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006507                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018566                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004310                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.104902                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.032341                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006507                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018566                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004310                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.104902                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.032341                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76856.166913                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76843.331071                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.735510                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.735510                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        45250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        45250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71714.440252                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71714.440252                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71679.322584                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71679.322584                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74519.325709                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74519.325709                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77950.919052                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77950.919052                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76856.166913                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71679.322584                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72601.440049                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72560.189046                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76856.166913                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71679.322584                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72601.440049                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72560.189046                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 61810.220862                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160516.632541                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.912157                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157350.565165                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157350.565165                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 61810.220862                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158933.410972                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116502.209672                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        1789463                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      33899423                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33707                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33707                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback     10034845                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict     27401014                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        49574                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        49576                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2364622                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2364622                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     24576044                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7542009                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1351619                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1244955                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     73828388                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     33661752                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       699908                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2274176                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total         110464224                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1576213440                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1181188062                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2333736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7831184                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2767566422                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     2271727                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     75147333                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.047128                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.211913                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1           71605763     95.29%     95.29% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2            3541570      4.71%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       75147333                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    45226020496                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1150500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   36946016966                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   15544978992                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     408213455                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1295285984                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40306                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40306                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230970                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230970                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353754                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334312                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334312                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           568890575                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147730000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115467                       # number of replacements
system.iocache.tags.tagsinuse               10.447125                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115483                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13147039080000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.519011                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.928115                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219938                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.433007                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.652945                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039722                       # Number of tag accesses
system.iocache.tags.data_accesses             1039722                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8821                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8858                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8821                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8861                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8821                       # number of overall misses
system.iocache.overall_misses::total             8861                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1605437158                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1610506158                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12610481417                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12610481417                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1605437158                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1610857158                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1605437158                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1610857158                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8821                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8858                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8821                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8861                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8821                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8861                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 182001.718399                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 181813.745541                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.218940                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118226.218940                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 182001.718399                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 181791.802054                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 182001.718399                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 181791.802054                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         31114                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3332                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.337935                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8821                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8858                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8821                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8861                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8821                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8861                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1164387158                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1167606158                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7277281417                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7277281417                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1164387158                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1167807158                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1164387158                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1167807158                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132001.718399                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 131813.745541                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.218940                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.218940                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 132001.718399                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 131791.802054                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 132001.718399                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 131791.802054                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               85994                       # Transaction distribution
system.membus.trans_dist::ReadResp             540915                       # Transaction distribution
system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
system.membus.trans_dist::Writeback           1480269                       # Transaction distribution
system.membus.trans_dist::CleanEvict           239619                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            39541                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           39543                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1253823                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1253823                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        454921                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6922                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5195008                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5324666                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341395                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       341395                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5666061                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13844                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    200030316                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    200200734                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7233472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7233472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               207434206                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3131                       # Total snoops (count)
system.membus.snoop_fanout::samples           3697223                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3697223    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3697223                       # Request fanout histogram
system.membus.reqLayer0.occupancy           102366500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5756000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9961724084                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         9396279986                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          228925719                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks

---------- End Simulation Statistics   ----------