path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.667482                       # Number of seconds simulated
sim_ticks                                51667481628000                       # Number of ticks simulated
final_tick                               51667481628000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 173876                       # Simulator instruction rate (inst/s)
host_op_rate                                   204307                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9745015544                       # Simulator tick rate (ticks/s)
host_mem_usage                                 682548                       # Number of bytes of host memory used
host_seconds                                  5301.94                       # Real time elapsed on the host
sim_insts                                   921877826                       # Number of instructions simulated
sim_ops                                    1083223459                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       355328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       294720                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10221184                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          93611976                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        405568                       # Number of bytes read from this memory
system.physmem.bytes_read::total            104888776                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst     10221184                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        10221184                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     87378688                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          87399268                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         5552                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         4605                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             159706                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1462700                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6337                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1638900                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1365292                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1367865                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           6877                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           5704                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               197826                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1811816                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7850                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2030073                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          197826                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             197826                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1691174                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1691572                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1691174                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          6877                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          5704                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              197826                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1812214                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7850                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3721645                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1638900                       # Number of read requests accepted
system.physmem.writeReqs                      1367865                       # Number of write requests accepted
system.physmem.readBursts                     1638900                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1367865                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                104832704                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     56896                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  87398080                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 104888776                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               87399268                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      889                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2255                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         381658                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               98450                       # Per bank write bursts
system.physmem.perBankRdBursts::1              107251                       # Per bank write bursts
system.physmem.perBankRdBursts::2               99188                       # Per bank write bursts
system.physmem.perBankRdBursts::3               95203                       # Per bank write bursts
system.physmem.perBankRdBursts::4               99955                       # Per bank write bursts
system.physmem.perBankRdBursts::5              109194                       # Per bank write bursts
system.physmem.perBankRdBursts::6               96838                       # Per bank write bursts
system.physmem.perBankRdBursts::7               98371                       # Per bank write bursts
system.physmem.perBankRdBursts::8               94736                       # Per bank write bursts
system.physmem.perBankRdBursts::9              155242                       # Per bank write bursts
system.physmem.perBankRdBursts::10              99865                       # Per bank write bursts
system.physmem.perBankRdBursts::11             104170                       # Per bank write bursts
system.physmem.perBankRdBursts::12              95009                       # Per bank write bursts
system.physmem.perBankRdBursts::13              96057                       # Per bank write bursts
system.physmem.perBankRdBursts::14              92133                       # Per bank write bursts
system.physmem.perBankRdBursts::15              96349                       # Per bank write bursts
system.physmem.perBankWrBursts::0               83734                       # Per bank write bursts
system.physmem.perBankWrBursts::1               87693                       # Per bank write bursts
system.physmem.perBankWrBursts::2               84639                       # Per bank write bursts
system.physmem.perBankWrBursts::3               83186                       # Per bank write bursts
system.physmem.perBankWrBursts::4               87134                       # Per bank write bursts
system.physmem.perBankWrBursts::5               92701                       # Per bank write bursts
system.physmem.perBankWrBursts::6               83787                       # Per bank write bursts
system.physmem.perBankWrBursts::7               85921                       # Per bank write bursts
system.physmem.perBankWrBursts::8               83051                       # Per bank write bursts
system.physmem.perBankWrBursts::9               88932                       # Per bank write bursts
system.physmem.perBankWrBursts::10              85543                       # Per bank write bursts
system.physmem.perBankWrBursts::11              89009                       # Per bank write bursts
system.physmem.perBankWrBursts::12              82580                       # Per bank write bursts
system.physmem.perBankWrBursts::13              83353                       # Per bank write bursts
system.physmem.perBankWrBursts::14              81127                       # Per bank write bursts
system.physmem.perBankWrBursts::15              83205                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          16                       # Number of times write queue was full causing retry
system.physmem.totGap                    51667479848500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1638885                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1365292                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1312759                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    318962                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       959                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       345                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       478                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       528                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       511                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1145                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       673                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       324                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      336                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      174                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      152                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      118                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      115                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       91                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       73                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       52                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    14965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    17095                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    65606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    80418                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    82482                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    82286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    83182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    83357                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    85216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    84108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    84794                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    89394                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    84174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    82879                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    91789                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    82005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    83224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    79922                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      349                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      336                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      305                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      376                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      299                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       40                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       647624                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      296.824083                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     173.411154                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     323.640423                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         254912     39.36%     39.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       156143     24.11%     63.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        60053      9.27%     72.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        34984      5.40%     78.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        25631      3.96%     82.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        18733      2.89%     85.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        14068      2.17%     87.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        12825      1.98%     89.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        70275     10.85%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         647624                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         79231                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.673638                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      283.409553                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          79228    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           79231                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         79231                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.235615                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.796201                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.303380                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           76926     97.09%     97.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             319      0.40%     97.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              70      0.09%     97.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             321      0.41%     97.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              45      0.06%     98.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             342      0.43%     98.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             202      0.25%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              22      0.03%     98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              52      0.07%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             126      0.16%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              31      0.04%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              49      0.06%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             483      0.61%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              36      0.05%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              14      0.02%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             128      0.16%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              11      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            28      0.04%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           79231                       # Writes before turning the bus around for reads
system.physmem.totQLat                    26417109815                       # Total ticks spent queuing
system.physmem.totMemAccLat               57129816065                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   8190055000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       16127.55                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34877.55                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.03                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.69                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.03                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.69                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.24                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1331553                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1024428                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.29                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.02                       # Row buffer hit rate for writes
system.physmem.avgGap                     17183743.94                       # Average gap between requests
system.physmem.pageHitRate                      78.44                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2488253040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1357677750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                6274663200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4463391600                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3374668374480                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1321909933950                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29840915681250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34552077975270                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.739417                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49642099754241                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1725290580000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    300090521259                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2407784400                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1313771250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                6501775800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4385664000                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3374668374480                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1318271769585                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29844107045250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34551656184765                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.731253                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49647373564820                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1725290580000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    294812186430                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             16                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               252485837                       # Number of BP lookups
system.cpu.branchPred.condPredicted         176433570                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          11949823                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            185211535                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               131480802                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             70.989532                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                30949299                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2133828                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    560555                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                560555                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        20820                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       178520                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples       560555                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0          560555    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       560555                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       199340                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 27109.310725                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 22940.792106                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 20958.396260                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       197062     98.86%     98.86% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071            8      0.00%     98.86% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607         1944      0.98%     99.84% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143           53      0.03%     99.86% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679          116      0.06%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           50      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751           75      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287           14      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       199340                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples  -1569959592                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0     -1569959592    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total  -1569959592                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        178521     89.56%     89.56% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         20820     10.44%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       199341                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       560555                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       560555                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       199341                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       199341                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       759896                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    178230117                       # DTB read hits
system.cpu.dtb.read_misses                     462749                       # DTB read misses
system.cpu.dtb.write_hits                   157902959                       # DTB write hits
system.cpu.dtb.write_misses                     97806                       # DTB write misses
system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               45299                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1089                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    78363                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1414                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  14783                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     23068                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                178692866                       # DTB read accesses
system.cpu.dtb.write_accesses               158000765                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         336133076                       # DTB hits
system.cpu.dtb.misses                          560555                       # DTB misses
system.cpu.dtb.accesses                     336693631                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    134868                       # Table walker walks requested
system.cpu.itb.walker.walksLong                134868                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1077                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       117569                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       134868                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          134868    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       134868                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       118646                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 30429.546719                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 26050.717125                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 23099.528150                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       116148     97.89%     97.89% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071            8      0.01%     97.90% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607         2266      1.91%     99.81% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           70      0.06%     99.87% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679          116      0.10%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           20      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       118646                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples  -1570990092                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0     -1570990092    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total  -1570990092                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        117569     99.09%     99.09% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1077      0.91%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       118646                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       134868                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       134868                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       118646                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       118646                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       253514                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    438855637                       # ITB inst hits
system.cpu.itb.inst_misses                     134868                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               45299                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1089                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    56516                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    359281                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                438990505                       # ITB inst accesses
system.cpu.itb.hits                         438855637                       # DTB hits
system.cpu.itb.misses                          134868                       # DTB misses
system.cpu.itb.accesses                     438990505                       # DTB accesses
system.cpu.numCycles                       2563496972                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   921877826                       # Number of instructions committed
system.cpu.committedOps                    1083223459                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      92885181                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      7623                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                 100772604966                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.780734                       # CPI: cycles per instruction
system.cpu.ipc                               0.359617                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16483                       # number of quiesce instructions executed
system.cpu.tickCycles                      1740911334                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       822585638                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements          10734176                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.930080                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           320289523                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          10734688                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.836873                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        7087675500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.930080                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999863                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999863                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          385                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1345515853                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1345515853                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    163941297                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       163941297                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    147439641                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      147439641                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       511618                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        511618                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       335027                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       335027                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3852667                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3852667                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      4161339                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4161339                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     311380938                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        311380938                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    311892556                       # number of overall hits
system.cpu.dcache.overall_hits::total       311892556                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      6369353                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       6369353                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      4134165                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4134165                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1400138                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1400138                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1239654                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1239654                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       310380                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       310380                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     10503518                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       10503518                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     11903656                       # number of overall misses
system.cpu.dcache.overall_misses::total      11903656                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 117431334000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 117431334000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 199634806500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 199634806500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  84591152000                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  84591152000                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5133902500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   5133902500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 317066140500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 317066140500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 317066140500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 317066140500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    170310650                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    170310650                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    151573806                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    151573806                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1911756                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1911756                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1574681                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1574681                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4163047                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4163047                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      4161340                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4161340                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    321884456                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    321884456                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    323796212                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    323796212                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037398                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.037398                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027275                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.027275                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.732383                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.732383                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787241                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.787241                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.074556                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.074556                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.032631                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.032631                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.036763                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.036763                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18436.932919                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18436.932919                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48289.027288                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48289.027288                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68237.711490                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68237.711490                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16540.700110                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16540.700110                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30186.661317                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30186.661317                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26636.030183                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26636.030183                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      8245378                       # number of writebacks
system.cpu.dcache.writebacks::total           8245378                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       770684                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       770684                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1822945                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1822945                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          152                       # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total          152                       # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69756                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        69756                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2593629                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2593629                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2593629                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2593629                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5598669                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5598669                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2311220                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2311220                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1392587                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1392587                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1239502                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1239502                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       240624                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       240624                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      7909889                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      7909889                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9302476                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9302476                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33697                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33706                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33706                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67403                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  96111391500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  96111391500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105871130000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 105871130000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  26586103000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  26586103000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  83345106500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  83345106500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3481164500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3481164500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        81000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 201982521500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 201982521500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228568624500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 228568624500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6197557500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6197557500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6207394000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6207394000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12404951500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  12404951500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032873                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032873                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015248                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015248                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.728433                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.728433                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787145                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787145                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057800                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057800                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024574                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024574                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028729                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.028729                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17166.828669                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17166.828669                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45807.465321                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45807.465321                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19091.161270                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19091.161270                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67240.800338                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67240.800338                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14467.237266                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14467.237266                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25535.443228                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25535.443228                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24570.729825                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24570.729825                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183920.156097                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183920.156097                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184162.879013                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184162.879013                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184041.533760                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184041.533760                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          24166189                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.872408                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           414317362                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          24166701                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             17.144142                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       39504620500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.872408                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999751                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999751                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          104                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         462650783                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        462650783                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    414317362                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       414317362                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     414317362                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        414317362                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    414317362                       # number of overall hits
system.cpu.icache.overall_hits::total       414317362                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     24166711                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      24166711                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     24166711                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       24166711                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     24166711                       # number of overall misses
system.cpu.icache.overall_misses::total      24166711                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 327482385000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 327482385000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 327482385000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 327482385000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 327482385000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 327482385000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    438484073                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    438484073                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    438484073                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    438484073                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    438484073                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    438484073                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.055114                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.055114                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.055114                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.055114                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.055114                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.055114                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13550.970382                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13550.970382                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13550.970382                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13550.970382                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13550.970382                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13550.970382                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks     24166189                       # number of writebacks
system.cpu.icache.writebacks::total          24166189                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24166711                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     24166711                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     24166711                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     24166711                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     24166711                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     24166711                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303315675000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 303315675000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303315675000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 303315675000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303315675000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 303315675000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   6746864000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   6746864000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   6746864000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   6746864000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.055114                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.055114                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.055114                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.055114                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.055114                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.055114                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12550.970424                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12550.970424                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12550.970424                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12550.970424                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12550.970424                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12550.970424                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1490419                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65266.902030                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           65881939                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1553674                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            42.403966                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      36600562500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36961.112074                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   325.532890                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   387.132710                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  7869.830371                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19723.293986                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.563982                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004967                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.005907                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.120084                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.300954                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995894                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          269                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        62986                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          268                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          528                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2448                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5559                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54399                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004105                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961090                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        573572775                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       573572775                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       919373                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       282584                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1201957                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks      8245378                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      8245378                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     24162502                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     24162502                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        10423                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        10423                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1645677                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1645677                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24059282                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     24059282                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6917053                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6917053                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       707885                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       707885                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       919373                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       282584                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     24059282                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8562730                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        33823969                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       919373                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       282584                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     24059282                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8562730                       # number of overall hits
system.cpu.l2cache.overall_hits::total       33823969                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         5552                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         4605                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        10157                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        37446                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        37446                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       617921                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       617921                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       107426                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total       107426                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       314580                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       314580                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       531617                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       531617                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         5552                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         4605                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       107426                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       932501                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1050084                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         5552                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         4605                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       107426                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       932501                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1050084                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    759647500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    632585000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1392232500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1488692000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total   1488692000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        79500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        79500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  81962510000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  81962510000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  14211686500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total  14211686500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  42390625000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  42390625000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  73785023000                       # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total  73785023000                       # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    759647500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    632585000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  14211686500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 124353135000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 139957054000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    759647500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    632585000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  14211686500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 124353135000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 139957054000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       924925                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       287189                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1212114                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks      8245378                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      8245378                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     24162502                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     24162502                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        47869                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        47869                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2263598                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2263598                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24166708                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     24166708                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7231633                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7231633                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1239502                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1239502                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       924925                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       287189                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     24166708                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9495231                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     34874053                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       924925                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       287189                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     24166708                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9495231                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     34874053                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006003                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.016035                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.008380                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782260                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782260                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.272982                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.272982                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004445                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004445                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043501                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043501                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.428896                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.428896                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006003                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.016035                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004445                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.098207                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.030111                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006003                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.016035                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004445                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.098207                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.030111                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136824.117435                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137369.163952                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137071.231663                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39755.701544                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39755.701544                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132642.376614                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132642.376614                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132292.801556                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132292.801556                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134753.083476                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134753.083476                       # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138793.573193                       # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138793.573193                       # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136824.117435                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137369.163952                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132292.801556                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133354.425357                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 133281.769839                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136824.117435                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137369.163952                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132292.801556                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133354.425357                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 133281.769839                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1258661                       # number of writebacks
system.cpu.l2cache.writebacks::total          1258661                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           22                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           25                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           25                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         5552                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4605                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        10157                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        37446                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        37446                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       617921                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       617921                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       107423                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total       107423                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       314558                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       314558                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       531617                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       531617                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         5552                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4605                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       107423                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       932479                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1050059                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         5552                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4605                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       107423                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       932479                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1050059                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        86006                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33706                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33706                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119712                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    704127500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    586535000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1290662500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2650319500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2650319500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        69500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        69500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  75783300000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  75783300000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  13137194000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  13137194000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  39242637500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  39242637500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  68468853000                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  68468853000                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    704127500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    586535000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  13137194000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115025937500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 129453794000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    704127500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    586535000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  13137194000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115025937500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 129453794000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5936074000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5776284500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  11712358500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5819171500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5819171500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   5936074000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11595456000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  17531530000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006003                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.016035                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008380                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782260                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782260                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.272982                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.272982                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004445                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004445                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043498                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043498                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.428896                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.428896                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006003                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.016035                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004445                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.098205                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.030110                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006003                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.016035                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004445                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.098205                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.030110                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127369.163952                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127071.231663                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70777.105699                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70777.105699                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122642.376614                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122642.376614                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122294.052484                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122294.052484                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124754.854431                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124754.854431                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128793.573193                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128793.573193                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127369.163952                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122294.052484                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123354.989764                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123282.400322                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127369.163952                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122294.052484                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123354.989764                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123282.400322                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171418.360685                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136180.714136                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172644.974189                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172644.974189                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.749329                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.557471                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests     70542716                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     35641283                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4403                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2298                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2298                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq        1728705                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      33127830                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33706                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33706                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      9610686                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     24162502                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2728698                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        47872                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        47873                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2263598                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2263598                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     24166711                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7240510                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1346166                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1239502                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     72600538                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32434260                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       690132                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2164681                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total         107889611                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3096417152                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1135639442                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2297512                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7399400                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         4241753506                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     2152838                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     38433190                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.018207                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.133699                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           37733441     98.18%     98.18% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             699749      1.82%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       38433190                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    68234466996                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1477892                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   36335720582                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   14937837927                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     402991902                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1239794423                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40325                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40325                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231008                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231008                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353792                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334464                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334464                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492384                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             42167500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               332500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               16000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25751500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            34145500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           565709151                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147768000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115486                       # number of replacements
system.iocache.tags.tagsinuse               10.440009                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115502                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13160148730000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.520855                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.919154                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.220053                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.432447                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.652501                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039893                       # Number of tag accesses
system.iocache.tags.data_accesses             1039893                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8840                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8877                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8840                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8880                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8840                       # number of overall misses
system.iocache.overall_misses::total             8880                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1638496114                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1643565614                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13864020537                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13864020537                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1638496114                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1643916614                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1638496114                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1643916614                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8840                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8877                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8840                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8880                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8840                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8880                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 185350.239140                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 185148.768052                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129978.441995                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129978.441995                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 185350.239140                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 185125.744820                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 185350.239140                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 185125.744820                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         33657                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3502                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.610794                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8840                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8877                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8840                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8880                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8840                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8880                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1196496114                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1199715614                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8530820537                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8530820537                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1196496114                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1199916614                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1196496114                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1199916614                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135350.239140                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 135148.768052                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79978.441995                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.441995                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 135350.239140                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 135125.744820                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 135350.239140                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 135125.744820                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               86006                       # Transaction distribution
system.membus.trans_dist::ReadResp             527021                       # Transaction distribution
system.membus.trans_dist::WriteReq              33706                       # Transaction distribution
system.membus.trans_dist::WriteResp             33706                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1365292                       # Transaction distribution
system.membus.trans_dist::CleanEvict           236782                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            38218                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           38219                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1148769                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1148769                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        441015                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4836672                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4966324                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341304                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       341304                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5307628                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13832                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    185058092                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    185228498                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7229952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7229952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               192458450                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3204                       # Total snoops (count)
system.membus.snoop_fanout::samples           3459197                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3459197    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3459197                       # Request fanout histogram
system.membus.reqLayer0.occupancy           102492500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5497000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9250665962                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         8763516637                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          227782427                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks

---------- End Simulation Statistics   ----------