path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.610037                       # Number of seconds simulated
sim_ticks                                51610036853000                       # Number of ticks simulated
final_tick                               51610036853000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 188716                       # Simulator instruction rate (inst/s)
host_op_rate                                   221745                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            10246213919                       # Simulator tick rate (ticks/s)
host_mem_usage                                 724572                       # Number of bytes of host memory used
host_seconds                                  5036.99                       # Real time elapsed on the host
sim_insts                                   950561948                       # Number of instructions simulated
sim_ops                                    1116924449                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       410048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       340288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10352448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          67122824                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        411200                       # Number of bytes read from this memory
system.physmem.bytes_read::total             78636808                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst     10352448                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        10352448                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     95202624                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          95223204                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         6407                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         5317                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             161757                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1048807                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6425                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1228713                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1487541                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1490114                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           7945                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           6593                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               200590                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1300577                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7967                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1523673                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          200590                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             200590                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1844653                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 399                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1845052                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1844653                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          7945                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          6593                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              200590                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1300976                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7967                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3368725                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1228713                       # Number of read requests accepted
system.physmem.writeReqs                      2143008                       # Number of write requests accepted
system.physmem.readBursts                     1228713                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    2143008                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 78600192                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     37440                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 133928256                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  78636808                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              137008420                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      585                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   50360                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          39728                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               75722                       # Per bank write bursts
system.physmem.perBankRdBursts::1               79954                       # Per bank write bursts
system.physmem.perBankRdBursts::2               72878                       # Per bank write bursts
system.physmem.perBankRdBursts::3               71278                       # Per bank write bursts
system.physmem.perBankRdBursts::4               72651                       # Per bank write bursts
system.physmem.perBankRdBursts::5               79829                       # Per bank write bursts
system.physmem.perBankRdBursts::6               73600                       # Per bank write bursts
system.physmem.perBankRdBursts::7               73320                       # Per bank write bursts
system.physmem.perBankRdBursts::8               65239                       # Per bank write bursts
system.physmem.perBankRdBursts::9              127420                       # Per bank write bursts
system.physmem.perBankRdBursts::10              73665                       # Per bank write bursts
system.physmem.perBankRdBursts::11              77478                       # Per bank write bursts
system.physmem.perBankRdBursts::12              72459                       # Per bank write bursts
system.physmem.perBankRdBursts::13              72712                       # Per bank write bursts
system.physmem.perBankRdBursts::14              69098                       # Per bank write bursts
system.physmem.perBankRdBursts::15              70825                       # Per bank write bursts
system.physmem.perBankWrBursts::0              130775                       # Per bank write bursts
system.physmem.perBankWrBursts::1              132563                       # Per bank write bursts
system.physmem.perBankWrBursts::2              131683                       # Per bank write bursts
system.physmem.perBankWrBursts::3              133448                       # Per bank write bursts
system.physmem.perBankWrBursts::4              132375                       # Per bank write bursts
system.physmem.perBankWrBursts::5              136941                       # Per bank write bursts
system.physmem.perBankWrBursts::6              129100                       # Per bank write bursts
system.physmem.perBankWrBursts::7              132855                       # Per bank write bursts
system.physmem.perBankWrBursts::8              124239                       # Per bank write bursts
system.physmem.perBankWrBursts::9              131924                       # Per bank write bursts
system.physmem.perBankWrBursts::10             130753                       # Per bank write bursts
system.physmem.perBankWrBursts::11             132768                       # Per bank write bursts
system.physmem.perBankWrBursts::12             128150                       # Per bank write bursts
system.physmem.perBankWrBursts::13             130180                       # Per bank write bursts
system.physmem.perBankWrBursts::14             126529                       # Per bank write bursts
system.physmem.perBankWrBursts::15             128346                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         140                       # Number of times write queue was full causing retry
system.physmem.totGap                    51610035211500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1228698                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                2140435                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1157126                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     64351                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       755                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       308                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       447                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       546                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       482                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       776                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       503                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1798                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      175                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      116                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      110                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       92                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       89                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       70                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       58                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    52200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    61876                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                   103140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   107216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   115340                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   154284                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   127380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   116704                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   115742                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   109222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   108713                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   142144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   115995                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   110189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   122630                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   110947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   107019                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   104847                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     5989                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     5575                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     6143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     7595                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     8109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     7187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     6881                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     8026                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     6843                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     6405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     5844                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     5760                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     4978                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     3912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     3857                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     3012                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     2330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1631                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      768                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1002                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      546                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      404                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      345                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      339                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      312                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       733749                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      289.646732                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     167.469062                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     324.982397                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         301017     41.02%     41.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       179214     24.42%     65.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        65174      8.88%     74.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        36623      4.99%     79.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        25257      3.44%     82.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        17346      2.36%     85.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        13099      1.79%     86.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        11628      1.58%     88.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        84391     11.50%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         733749                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples        100720                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        12.193388                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      124.138953                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023         100718    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total          100720                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples        100720                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.776698                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.274786                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       17.101890                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31           96977     96.28%     96.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47            2012      2.00%     98.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63             404      0.40%     98.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79             303      0.30%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95             157      0.16%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111            153      0.15%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127           320      0.32%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143           134      0.13%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            20      0.02%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175            11      0.01%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            66      0.07%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            35      0.03%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            14      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             5      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             7      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             6      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             7      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319            11      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             8      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351            12      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            21      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             5      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             5      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::432-447             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::464-479             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             5      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             5      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::688-703             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::720-735             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::736-751             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::912-927             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total          100720                       # Writes before turning the bus around for reads
system.physmem.totQLat                    16983547454                       # Total ticks spent queuing
system.physmem.totMemAccLat               40010947454                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6140640000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13828.81                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  32578.81                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.52                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.60                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.52                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.65                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.54                       # Average write queue length when enqueuing
system.physmem.readRowHits                     948457                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1638549                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.23                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.30                       # Row buffer hit rate for writes
system.physmem.avgGap                     15306733.63                       # Average gap between requests
system.physmem.pageHitRate                      77.90                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2845387440                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1552542750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4674001800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               6867115200                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3370916218800                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1311782988195                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29815330787250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34513969041435                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.745387                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49599639397461                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1723372300000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    287019858539                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2701755000                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1474171875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4905342000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               6693120720                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3370916218800                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1303897064130                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29822248264500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34512835937025                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.723432                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49611170347429                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1723372300000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    275493728071                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             16                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               260902420                       # Number of BP lookups
system.cpu.branchPred.condPredicted         182959992                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12222887                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            194114900                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               136429435                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             70.282825                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                31730781                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2172348                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    588227                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                588227                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        22315                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       191623                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples       588227                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0          588227    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       588227                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       213938                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 24858.035959                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 21008.300307                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 15796.225820                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       211313     98.77%     98.77% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         2233      1.04%     99.82% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607          146      0.07%     99.89% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          117      0.05%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679           91      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           23      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       213938                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    -15748296                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       -15748296    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    -15748296                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        191624     89.57%     89.57% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         22315     10.43%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       213939                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       588227                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       588227                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       213939                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       213939                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       802166                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    183548892                       # DTB read hits
system.cpu.dtb.read_misses                     485969                       # DTB read misses
system.cpu.dtb.write_hits                   162881584                       # DTB write hits
system.cpu.dtb.write_misses                    102258                       # DTB write misses
system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               47246                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    79791                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       811                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  15585                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     23526                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                184034861                       # DTB read accesses
system.cpu.dtb.write_accesses               162983842                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         346430476                       # DTB hits
system.cpu.dtb.misses                          588227                       # DTB misses
system.cpu.dtb.accesses                     347018703                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    136538                       # Table walker walks requested
system.cpu.itb.walker.walksLong                136538                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1085                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       118818                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       136538                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          136538    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       136538                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       119903                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 27208.529278                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 23313.702861                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 17744.151968                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       116996     97.58%     97.58% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071         2625      2.19%     99.76% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607          168      0.14%     99.90% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           53      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679           37      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           14      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       119903                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    -16365796                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       -16365796    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    -16365796                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        118818     99.10%     99.10% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1085      0.90%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       119903                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136538                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       136538                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       119903                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       119903                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       256441                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    454119408                       # ITB inst hits
system.cpu.itb.inst_misses                     136538                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               47246                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    57195                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    369083                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                454255946                       # ITB inst accesses
system.cpu.itb.hits                         454119408                       # DTB hits
system.cpu.itb.misses                          136538                       # DTB misses
system.cpu.itb.accesses                     454255946                       # DTB accesses
system.cpu.numCycles                       2495798541                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   950561948                       # Number of instructions committed
system.cpu.committedOps                    1116924449                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      97483728                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      7747                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                 100725440428                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.625603                       # CPI: cycles per instruction
system.cpu.ipc                               0.380865                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16607                       # number of quiesce instructions executed
system.cpu.tickCycles                      1794634441                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       701164100                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements          11128908                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.957332                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           330012577                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          11129420                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.652271                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4320792250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.957332                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999917                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999917                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          379                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1386837426                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1386837426                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    168701491                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       168701491                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    152033429                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      152033429                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       523995                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        523995                       # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       336687                       # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total       336687                       # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      4025252                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      4025252                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      4342024                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4342024                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     320734920                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        320734920                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    321258915                       # number of overall hits
system.cpu.dcache.overall_hits::total       321258915                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      6599201                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       6599201                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      4320372                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4320372                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1481368                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1481368                       # number of SoftPFReq misses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1244671                       # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total      1244671                       # number of WriteInvalidateReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       318506                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       318506                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     10919573                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       10919573                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     12400941                       # number of overall misses
system.cpu.dcache.overall_misses::total      12400941                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 107641538217                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 107641538217                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 155110738831                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 155110738831                       # number of WriteReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  35571203201                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::total  35571203201                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4850646421                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   4850646421                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 262752277048                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 262752277048                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 262752277048                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 262752277048                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    175300692                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    175300692                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    156353801                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    156353801                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      2005363                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      2005363                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1581358                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total      1581358                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4343758                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4343758                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      4342025                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4342025                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    331654493                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    331654493                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    333659856                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    333659856                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037645                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.037645                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027632                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.027632                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.738703                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.738703                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.787090                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.787090                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.073325                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.073325                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.032925                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.032925                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037166                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037166                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16311.298628                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16311.298628                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35902.172042                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35902.172042                       # average WriteReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28578.799700                       # average WriteInvalidateReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28578.799700                       # average WriteInvalidateReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15229.372197                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15229.372197                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24062.504738                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24062.504738                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21188.091859                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21188.091859                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            4                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      8539693                       # number of writebacks
system.cpu.dcache.writebacks::total           8539693                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       803144                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       803144                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1904565                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1904565                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data          147                       # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::total          147                       # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69655                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        69655                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2707709                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2707709                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2707709                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2707709                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5796057                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5796057                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2415807                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2415807                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1473891                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1473891                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1244524                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1244524                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       248851                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       248851                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      8211864                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      8211864                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9685755                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9685755                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33696                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33705                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33705                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67401                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67401                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  85294782786                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  85294782786                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  79878018296                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  79878018296                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23078167080                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23078167080                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  33700697799                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  33700697799                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3279664007                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3279664007                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        80500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        80500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165172801082                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 165172801082                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188250968162                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 188250968162                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5750649000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5750649000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5615353750                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5615353750                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11366002750                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11366002750                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033064                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033064                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015451                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015451                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.734975                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.734975                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.786997                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786997                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057289                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057289                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024760                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024760                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029029                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.029029                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14716.001376                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14716.001376                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33064.735012                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33064.735012                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15657.987653                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15657.987653                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27079.186740                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.186740                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13179.227759                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13179.227759                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        80500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        80500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20113.923110                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20113.923110                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19435.858966                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19435.858966                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170662.660256                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170662.660256                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166602.989171                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166602.989171                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168632.553671                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168632.553671                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          24596775                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.926998                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           429140951                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          24597287                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             17.446678                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       22329177250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.926998                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999857                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999857                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          103                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         478335544                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        478335544                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    429140951                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       429140951                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     429140951                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        429140951                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    429140951                       # number of overall hits
system.cpu.icache.overall_hits::total       429140951                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     24597297                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      24597297                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     24597297                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       24597297                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     24597297                       # number of overall misses
system.cpu.icache.overall_misses::total      24597297                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 327843901768                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 327843901768                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 327843901768                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 327843901768                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 327843901768                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 327843901768                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    453738248                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    453738248                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    453738248                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    453738248                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    453738248                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    453738248                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054210                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.054210                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.054210                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.054210                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.054210                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.054210                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13328.452381                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13328.452381                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13328.452381                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13328.452381                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13328.452381                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13328.452381                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24597297                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     24597297                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     24597297                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     24597297                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     24597297                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     24597297                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52294                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        52294                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52294                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        52294                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290898201664                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 290898201664                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290898201664                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 290898201664                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290898201664                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 290898201664                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   4024065500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   4024065500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   4024065500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   4024065500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054210                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054210                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054210                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.054210                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054210                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.054210                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11826.429614                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11826.429614                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11826.429614                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11826.429614                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11826.429614                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11826.429614                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76950.806976                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76950.806976                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76950.806976                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76950.806976                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1624472                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65307.335302                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           40176051                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1687699                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            23.805223                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       6393601000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36145.263997                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   333.648075                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   422.733439                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  8142.717924                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 20262.971868                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.551533                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005091                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006450                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124248                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.309188                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996511                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          253                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        62974                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          253                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          498                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2440                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5584                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54389                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003860                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.960907                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        369553553                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       369553553                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       980236                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       284775                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst     24487803                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      7183333                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total       32936147                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      8539693                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      8539693                       # number of Writeback hits
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       698094                       # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total       698094                       # number of WriteInvalidateReq hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        10791                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        10791                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1651497                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1651497                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       980236                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       284775                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     24487803                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8834830                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        34587644                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       980236                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       284775                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     24487803                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8834830                       # number of overall hits
system.cpu.l2cache.overall_hits::total       34587644                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6407                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5317                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst       109491                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       335212                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       456427                       # number of ReadReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       546430                       # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total       546430                       # number of WriteInvalidateReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        38901                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        38901                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       714872                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       714872                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         6407                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         5317                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       109491                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1050084                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1171299                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         6407                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         5317                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       109491                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1050084                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1171299                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    560042000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    465198251                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   8958985804                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  28447834598                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  38432060653                       # number of ReadReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data      6247800                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::total      6247800                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    584783300                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    584783300                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        79500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        79500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  58773696620                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  58773696620                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    560042000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    465198251                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   8958985804                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  87221531218                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  97205757273                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    560042000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    465198251                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   8958985804                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  87221531218                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  97205757273                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       986643                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       290092                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst     24597294                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7518545                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total     33392574                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      8539693                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      8539693                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1244524                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total      1244524                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        49692                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        49692                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2366369                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2366369                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       986643                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       290092                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     24597294                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9884914                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     35758943                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       986643                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       290092                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     24597294                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9884914                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     35758943                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006494                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.018329                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.004451                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.044585                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.013669                       # miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.439067                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.439067                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782842                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782842                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.302097                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.302097                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006494                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018329                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004451                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.106231                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.032755                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006494                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.018329                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004451                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.106231                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.032755                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87410.956766                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87492.618206                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81823.947210                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84865.203507                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84201.987729                       # average ReadReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data    11.433852                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total    11.433852                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15032.603275                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15032.603275                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82215.692627                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82215.692627                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87410.956766                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87492.618206                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81823.947210                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83061.480051                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82989.703972                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87410.956766                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87492.618206                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81823.947210                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83061.480051                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82989.703972                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1380910                       # number of writebacks
system.cpu.l2cache.writebacks::total          1380910                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           23                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           23                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           23                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6407                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5317                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       109489                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       335191                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       456404                       # number of ReadReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data       546430                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       546430                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        38901                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        38901                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       714872                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       714872                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6407                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5317                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       109489                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1050063                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1171276                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6407                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5317                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       109489                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1050063                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1171276                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52294                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        85990                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33705                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33705                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52294                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67401                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119695                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    479479000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    398285251                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   7586646696                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  24249187152                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  32713598099                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  18411194701                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  18411194701                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    691147894                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    691147894                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        67500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        67500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  49837354880                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  49837354880                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    479479000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    398285251                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7586646696                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  74086542032                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  82550952979                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    479479000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    398285251                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7586646696                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  74086542032                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  82550952979                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3108920000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5278320250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8387240250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176274500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176274500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3108920000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10454594750                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13563514750                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006494                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018329                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.004451                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.044582                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013668                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.439067                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.439067                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782842                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782842                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.302097                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.302097                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006494                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018329                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004451                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.106229                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.032755                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006494                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018329                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004451                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.106229                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.032755                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74907.889976                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69291.405493                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72344.386192                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71676.843540                       # average ReadReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33693.601561                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33693.601561                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17766.841315                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17766.841315                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        67500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        67500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69715.074699                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69715.074699                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74907.889976                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69291.405493                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70554.378196                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70479.505240                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74907.889976                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69291.405493                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70554.378196                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70479.505240                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156645.306565                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97537.390976                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153575.864115                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153575.864115                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155110.380410                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113317.304399                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq       33924038                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      33915953                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33705                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33705                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      8539693                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1351286                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1244524                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        49695                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        49696                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2366369                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2366369                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     49299178                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     31033537                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       698041                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2292039                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          83322795                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1577573568                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1259064522                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2320736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7893144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2846851970                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      553019                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     46264787                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.039533                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.194859                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1           44435816     96.05%     96.05% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2            1828971      3.95%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       46264787                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    32875768488                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1167000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   37011580552                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   15738706286                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     408640707                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1306185489                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40309                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40309                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp              29907                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230976                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230976                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353760                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334336                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334336                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           606954435                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148397760                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              174500                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115470                       # number of replacements
system.iocache.tags.tagsinuse               10.439534                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115486                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13142420796000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.524742                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.914791                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.220296                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.432174                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.652471                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039749                       # Number of tag accesses
system.iocache.tags.data_accesses             1039749                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8824                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8861                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8824                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8864                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8824                       # number of overall misses
system.iocache.overall_misses::total             8864                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1602204582                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1607276582                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       352500                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       352500                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19806517093                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  19806517093                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5424500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1602204582                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1607629082                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5424500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1602204582                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1607629082                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8824                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8861                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8824                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8864                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8824                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8864                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 181573.502040                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 181387.719445                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117500                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117500                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185690.740015                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 185690.740015                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 181573.502040                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 181366.096796                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 181573.502040                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 181366.096796                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        109809                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                16154                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.797635                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8824                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8861                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8824                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8864                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8824                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8864                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3142000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1142260060                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1145402060                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       193500                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       193500                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14259947135                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14259947135                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3335500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1142260060                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1145595560                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3335500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1142260060                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1145595560                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129449.236174                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 129263.295339                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        64500                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        64500                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133690.346649                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133690.346649                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 129449.236174                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 129241.376354                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 129449.236174                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 129241.376354                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              551255                       # Transaction distribution
system.membus.trans_dist::ReadResp             551255                       # Transaction distribution
system.membus.trans_dist::WriteReq              33705                       # Transaction distribution
system.membus.trans_dist::WriteResp             33705                       # Transaction distribution
system.membus.trans_dist::Writeback           1487541                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       652894                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       652894                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            39734                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           39735                       # Transaction distribution
system.membus.trans_dist::ReadExReq            714242                       # Transaction distribution
system.membus.trans_dist::ReadExResp           714242                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6912                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5003208                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5132856                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335248                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       335248                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5468104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13824                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    201583148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    201753546                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14062080                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14062080                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               215815626                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3099                       # Total snoops (count)
system.membus.snoop_fanout::samples           3479513                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3479513    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3479513                       # Request fanout histogram
system.membus.reqLayer0.occupancy           102597500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5574500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         12409067173                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7217145927                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          151545740                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped

---------- End Simulation Statistics   ----------