path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.688410                       # Number of seconds simulated
sim_ticks                                51688410348500                       # Number of ticks simulated
final_tick                               51688410348500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 152333                       # Simulator instruction rate (inst/s)
host_op_rate                                   179011                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             8275752383                       # Simulator tick rate (ticks/s)
host_mem_usage                                 662164                       # Number of bytes of host memory used
host_seconds                                  6245.77                       # Real time elapsed on the host
sim_insts                                   951433762                       # Number of instructions simulated
sim_ops                                    1118058358                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       411264                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       350272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          77213320                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        415808                       # Number of bytes read from this memory
system.physmem.bytes_read::total             78390664                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst     10284736                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        10284736                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     94966144                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.inst          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          94986724                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         6426                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         5473                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst            1206471                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6497                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1224867                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1483846                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.inst              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1486419                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           7957                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           6777                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst              1493823                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8045                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1516600                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          198976                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             198976                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1837281                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.inst                 398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1837679                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1837281                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          7957                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          6777                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1494221                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8045                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3354280                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1224867                       # Number of read requests accepted
system.physmem.writeReqs                      2137165                       # Number of write requests accepted
system.physmem.readBursts                     1224867                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    2137165                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 78347456                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     44032                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 136289472                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  78390664                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              136634468                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      688                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    7616                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          39979                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               71039                       # Per bank write bursts
system.physmem.perBankRdBursts::1               73325                       # Per bank write bursts
system.physmem.perBankRdBursts::2               71985                       # Per bank write bursts
system.physmem.perBankRdBursts::3               70214                       # Per bank write bursts
system.physmem.perBankRdBursts::4               72864                       # Per bank write bursts
system.physmem.perBankRdBursts::5               82821                       # Per bank write bursts
system.physmem.perBankRdBursts::6               75004                       # Per bank write bursts
system.physmem.perBankRdBursts::7               73137                       # Per bank write bursts
system.physmem.perBankRdBursts::8               67826                       # Per bank write bursts
system.physmem.perBankRdBursts::9              129786                       # Per bank write bursts
system.physmem.perBankRdBursts::10              72316                       # Per bank write bursts
system.physmem.perBankRdBursts::11              77203                       # Per bank write bursts
system.physmem.perBankRdBursts::12              71594                       # Per bank write bursts
system.physmem.perBankRdBursts::13              74115                       # Per bank write bursts
system.physmem.perBankRdBursts::14              68849                       # Per bank write bursts
system.physmem.perBankRdBursts::15              72101                       # Per bank write bursts
system.physmem.perBankWrBursts::0              128045                       # Per bank write bursts
system.physmem.perBankWrBursts::1              133141                       # Per bank write bursts
system.physmem.perBankWrBursts::2              133329                       # Per bank write bursts
system.physmem.perBankWrBursts::3              132983                       # Per bank write bursts
system.physmem.perBankWrBursts::4              135529                       # Per bank write bursts
system.physmem.perBankWrBursts::5              141007                       # Per bank write bursts
system.physmem.perBankWrBursts::6              130525                       # Per bank write bursts
system.physmem.perBankWrBursts::7              133720                       # Per bank write bursts
system.physmem.perBankWrBursts::8              132879                       # Per bank write bursts
system.physmem.perBankWrBursts::9              138815                       # Per bank write bursts
system.physmem.perBankWrBursts::10             133616                       # Per bank write bursts
system.physmem.perBankWrBursts::11             135999                       # Per bank write bursts
system.physmem.perBankWrBursts::12             129210                       # Per bank write bursts
system.physmem.perBankWrBursts::13             131804                       # Per bank write bursts
system.physmem.perBankWrBursts::14             128438                       # Per bank write bursts
system.physmem.perBankWrBursts::15             130483                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    51688408694500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1224852                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                2134592                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1187733                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     30120                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2405                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       606                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       760                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       444                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       307                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       227                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       158                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      142                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      131                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      110                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      105                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       92                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       90                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       69                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       54                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    48573                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    74403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                   119873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   132680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   128553                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   131972                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   134309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   139176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   138776                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   138399                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   133829                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   121319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   116942                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   113077                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   105310                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   103984                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   102748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   101616                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     4095                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     3572                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     3285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2974                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     2608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     2544                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     2490                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     2322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     2151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     2024                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     2001                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1597                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1076                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      961                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      816                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      540                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       728572                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      294.598947                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     169.664587                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     329.125501                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         296144     40.65%     40.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       177091     24.31%     64.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        64790      8.89%     73.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        35671      4.90%     78.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        25285      3.47%     82.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        17267      2.37%     84.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        13064      1.79%     86.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        11522      1.58%     87.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        87738     12.04%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         728572                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         97844                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        12.511242                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      125.941708                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          97842    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           97844                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         97844                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        21.764472                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       20.107027                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.533220                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23           71394     72.97%     72.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31           19346     19.77%     92.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39            3261      3.33%     96.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47             806      0.82%     96.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             888      0.91%     97.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63             399      0.41%     98.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71             342      0.35%     98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79             242      0.25%     98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             261      0.27%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95             243      0.25%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103            222      0.23%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111            63      0.06%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119            71      0.07%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127            48      0.05%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135           149      0.15%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143            24      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            24      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             7      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167            12      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             6      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183            10      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             4      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             6      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             5      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           97844                       # Writes before turning the bus around for reads
system.physmem.totQLat                    16127261998                       # Total ticks spent queuing
system.physmem.totMemAccLat               39080618248                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6120895000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13173.94                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31923.94                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.52                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.64                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.52                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.64                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.82                       # Average write queue length when enqueuing
system.physmem.readRowHits                     946951                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1678178                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.35                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.80                       # Row buffer hit rate for writes
system.physmem.avgGap                     15374157.26                       # Average gap between requests
system.physmem.pageHitRate                      78.27                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     49562808778250                       # Time in different power states
system.physmem.memoryStateTime::REF      1725989460000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      399611675250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                2776243680                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                2731760640                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                1514815500                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                1490544000                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               4604987400                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               4943562000                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0              6922447920                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1              6876861120                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          3376035383760                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          3376035383760                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          1310091236460                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          1307916167760                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          29863840623750                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          29865748578750                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            34565785738470                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            34565742858030                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.733833                       # Core power per rank (mW)
system.physmem.averagePower::1             668.733004                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu.inst          740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             16                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               261297703                       # Number of BP lookups
system.cpu.branchPred.condPredicted         183348683                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12210638                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            193789546                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               136743179                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             70.562722                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                31690204                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2146162                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    183672011                       # DTB read hits
system.cpu.dtb.read_misses                     484545                       # DTB read misses
system.cpu.dtb.write_hits                   163011983                       # DTB write hits
system.cpu.dtb.write_misses                    101734                       # DTB write misses
system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               47427                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1113                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    80165                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       779                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  14148                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     23574                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                184156556                       # DTB read accesses
system.cpu.dtb.write_accesses               163113717                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         346683994                       # DTB hits
system.cpu.dtb.misses                          586279                       # DTB misses
system.cpu.dtb.accesses                     347270273                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                    455292001                       # ITB inst hits
system.cpu.itb.inst_misses                     136900                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               47427                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1113                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    57667                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    366615                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                455428901                       # ITB inst accesses
system.cpu.itb.hits                         455292001                       # DTB hits
system.cpu.itb.misses                          136900                       # DTB misses
system.cpu.itb.accesses                     455428901                       # DTB accesses
system.cpu.numCycles                       2518825477                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   951433762                       # Number of instructions committed
system.cpu.committedOps                    1118058358                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      97427430                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      7769                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                 100859175256                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.647400                       # CPI: cycles per instruction
system.cpu.ipc                               0.377729                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16629                       # number of quiesce instructions executed
system.cpu.tickCycles                      1804872231                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       713953246                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements          11184340                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.959663                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           330369377                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          11184852                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.537215                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4089991250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst   511.959663                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.999921                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999921                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          387                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1387996074                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1387996074                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst    169370817                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       169370817                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst    152148495                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      152148495                       # number of WriteReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst       336885                       # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total       336885                       # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst      4109295                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      4109295                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst      4353813                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4353813                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst     321519312                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        321519312                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst    321519312                       # number of overall hits
system.cpu.dcache.overall_hits::total       321519312                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst      8065146                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       8065146                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst      4327048                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4327048                       # number of WriteReq misses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst      1245044                       # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total      1245044                       # number of WriteInvalidateReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.inst       246250                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       246250                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.inst            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.inst     12392194                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       12392194                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst     12392194                       # number of overall misses
system.cpu.dcache.overall_misses::total      12392194                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128575099737                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 128575099737                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 143976164605                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 143976164605                       # number of WriteReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.inst  29659207447                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::total  29659207447                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst   3578517253                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   3578517253                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst       150500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       150500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst 272551264342                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 272551264342                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst 272551264342                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 272551264342                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst    177435963                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    177435963                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst    156475543                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    156475543                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst      1581929                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total      1581929                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      4355545                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4355545                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst      4353815                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4353815                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst    333911506                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    333911506                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst    333911506                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    333911506                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.045454                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.045454                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.027653                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.027653                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.inst     0.787042                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.787042                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.056537                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.056537                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst     0.037112                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037112                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst     0.037112                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037112                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15942.067228                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15942.067228                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 33273.530732                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33273.530732                       # average WriteReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.inst 23821.814688                       # average WriteInvalidateReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23821.814688                       # average WriteInvalidateReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14532.049758                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14532.049758                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        75250                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        75250                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 21993.786116                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 21993.786116                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 21993.786116                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21993.786116                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      8574653                       # number of writebacks
system.cpu.dcache.writebacks::total           8574653                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       754189                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       754189                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst      1894189                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1894189                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.inst          150                       # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::total          150                       # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst      2648378                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2648378                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst      2648378                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2648378                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7310957                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7310957                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      2432859                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2432859                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.inst      1244894                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1244894                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst       246248                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       246248                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst      9743816                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9743816                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst      9743816                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9743816                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102346476258                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 102346476258                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  73412590018                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  73412590018                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst  27165305803                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  27165305803                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst   3084334247                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3084334247                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst       146500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       146500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 175759066276                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 175759066276                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 175759066276                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 175759066276                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5728692998                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5728692998                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   5585086250                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5585086250                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  11313779248                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11313779248                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.041203                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.041203                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015548                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015548                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.inst     0.786947                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786947                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.056537                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056537                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.029181                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.029181                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.029181                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.029181                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 13999.053237                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13999.053237                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 30175.439686                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30175.439686                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 21821.380618                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21821.380618                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12525.316945                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12525.316945                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        73250                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        73250                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18038.011625                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18038.011625                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18038.011625                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18038.011625                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          24658250                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.931964                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           430254710                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          24658762                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             17.448350                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       21183887000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.931964                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999867                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999867                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          132                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         479572253                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        479572253                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    430254710                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       430254710                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     430254710                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        430254710                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    430254710                       # number of overall hits
system.cpu.icache.overall_hits::total       430254710                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     24658772                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      24658772                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     24658772                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       24658772                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     24658772                       # number of overall misses
system.cpu.icache.overall_misses::total      24658772                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 327794821206                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 327794821206                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 327794821206                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 327794821206                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 327794821206                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 327794821206                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    454913482                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    454913482                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    454913482                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    454913482                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    454913482                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    454913482                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054205                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.054205                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.054205                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.054205                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.054205                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.054205                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13293.233791                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13293.233791                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13293.233791                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13293.233791                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13293.233791                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13293.233791                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24658772                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     24658772                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     24658772                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     24658772                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     24658772                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     24658772                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 278428644242                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 278428644242                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 278428644242                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 278428644242                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 278428644242                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 278428644242                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3812277750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3812277750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   3812277750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   3812277750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054205                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054205                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054205                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.054205                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054205                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.054205                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11291.261554                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11291.261554                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11291.261554                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11291.261554                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11291.261554                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11291.261554                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1618781                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65312.211718                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           40301488                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1682083                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            23.959274                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       5745484000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36153.667077                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   338.579375                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   416.289773                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 28403.675493                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.551661                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005166                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006352                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.433406                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996585                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63024                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          277                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          485                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2429                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5550                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54509                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961670                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        370683226                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       370683226                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       969390                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       282718                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst     31773452                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total       33025560                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      8574653                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      8574653                       # number of Writeback hits
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.inst       700619                       # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total       700619                       # number of WriteInvalidateReq hits
system.cpu.l2cache.UpgradeReq_hits::cpu.inst        10899                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        10899                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst      1669806                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1669806                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       969390                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       282718                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     33443258                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        34695366                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       969390                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       282718                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     33443258                       # number of overall hits
system.cpu.l2cache.overall_hits::total       34695366                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6426                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5473                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst       442244                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       454143                       # number of ReadReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.inst       544275                       # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total       544275                       # number of WriteInvalidateReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.inst        39165                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        39165                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst       713266                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       713266                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         6426                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         5473                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst      1155510                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1167409                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         6426                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         5473                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst      1155510                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1167409                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    506602500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    435256500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  33470920971                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  34412779971                       # number of ReadReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.inst      4488807                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::total      4488807                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst    437669201                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    437669201                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst       144500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       144500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  53261752624                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  53261752624                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    506602500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    435256500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  86732673595                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  87674532595                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    506602500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    435256500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  86732673595                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  87674532595                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       975816                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       288191                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst     32215696                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total     33479703                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      8574653                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      8574653                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.inst      1244894                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total      1244894                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.inst        50064                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        50064                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst      2383072                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2383072                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       975816                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       288191                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     34598768                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     35862775                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       975816                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       288191                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     34598768                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     35862775                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006585                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.018991                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.013728                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.013565                       # miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.inst     0.437206                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.437206                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.782299                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782299                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.299305                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.299305                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006585                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018991                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.033397                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.032552                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006585                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.018991                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.033397                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.032552                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78836.367880                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79527.955418                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75684.285080                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75775.207305                       # average ReadReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.inst     8.247314                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     8.247314                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11175.008324                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11175.008324                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        72250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        72250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74673.056930                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74673.056930                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78836.367880                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79527.955418                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75060.080480                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75101.813156                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78836.367880                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79527.955418                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75060.080480                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75101.813156                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1377216                       # number of writebacks
system.cpu.l2cache.writebacks::total          1377216                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           23                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           23                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           23                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           23                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           23                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           23                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6426                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5473                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       442221                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       454120                       # number of ReadReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.inst       544275                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       544275                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst        39165                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        39165                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       713266                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       713266                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6426                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5473                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst      1155487                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1167386                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6426                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5473                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst      1155487                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1167386                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    426390000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    366985500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  27899659527                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  28693035027                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst  12715651197                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  12715651197                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst    392011653                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    392011653                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst       120500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  44103603876                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  44103603876                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    426390000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    366985500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  72003263403                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  72796638903                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    426390000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    366985500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  72003263403                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  72796638903                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   8007275752                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8007275752                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   5177466000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5177466000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst  13184741752                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13184741752                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006585                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018991                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.013727                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013564                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.inst     0.437206                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.437206                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.782299                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782299                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.299305                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.299305                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006585                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018991                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.033397                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.032551                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006585                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018991                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.033397                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.032551                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67053.809611                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63089.856716                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63183.817112                       # average ReadReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 23362.548706                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23362.548706                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10009.234087                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.234087                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        60250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61833.318672                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61833.318672                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67053.809611                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62314.213317                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62358.670485                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67053.809611                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62314.213317                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62358.670485                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq       34021842                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      34013749                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33869                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33869                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      8574653                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1351558                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1244894                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        50067                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        50069                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2383072                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2383072                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     49422067                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     31180667                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       697225                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2277994                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          83577953                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1581505984                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1264852800                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2305528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7806528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2856470840                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      563561                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     46295151                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        5.002496                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.049898                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5           46179597     99.75%     99.75% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6             115554      0.25%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       46295151                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    32987192886                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1194000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   37103090732                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   15825165926                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     409755911                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1302956232                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40416                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40416                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231028                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231028                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354298                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334544                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334544                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492950                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy          1042369212                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           179072505                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115495                       # number of replacements
system.iocache.tags.tagsinuse               10.448328                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115511                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13141221301000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.519405                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.928922                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219963                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.433058                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653020                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039983                       # Number of tag accesses
system.iocache.tags.data_accesses             1039983                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8850                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8887                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8850                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8890                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8850                       # number of overall misses
system.iocache.overall_misses::total             8890                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5485000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1921500610                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1926985610                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28836803097                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  28836803097                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5824000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1921500610                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1927324610                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5824000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1921500610                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1927324610                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8850                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8887                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8850                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8890                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8850                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8890                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 217118.712994                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 216831.957916                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270351.787829                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 270351.787829                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 217118.712994                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 216796.919010                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 217118.712994                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 216796.919010                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        224459                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27520                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.156214                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8850                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8887                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8850                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8890                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8850                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8890                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3561000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1461199612                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1464760612                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23290267105                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23290267105                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3744000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1461199612                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1464943612                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3744000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1461199612                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1464943612                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165107.300791                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 164820.593226                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218351.712902                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218351.712902                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 165107.300791                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 164785.558155                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 165107.300791                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 164785.558155                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              549050                       # Transaction distribution
system.membus.trans_dist::ReadResp             549050                       # Transaction distribution
system.membus.trans_dist::WriteReq              33869                       # Transaction distribution
system.membus.trans_dist::WriteResp             33869                       # Transaction distribution
system.membus.trans_dist::Writeback           1483846                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       650746                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       650746                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            39985                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           39987                       # Transaction distribution
system.membus.trans_dist::ReadExReq            712642                       # Transaction distribution
system.membus.trans_dist::ReadExResp           712642                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6920                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4987889                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5118031                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335345                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       335345                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5453376                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    200958508                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    201129408                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14066624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14066624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               215196032                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3058                       # Total snoops (count)
system.membus.snoop_fanout::samples           3350229                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3350229    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3350229                       # Request fanout histogram
system.membus.reqLayer0.occupancy           113834500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               23328                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5697498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         21359860992                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy        12431404244                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          186704495                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped

---------- End Simulation Statistics   ----------