path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.609999                       # Number of seconds simulated
sim_ticks                                51609998980000                       # Number of ticks simulated
final_tick                               51609998980000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 182485                       # Simulator instruction rate (inst/s)
host_op_rate                                   214421                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9938249935                       # Simulator tick rate (ticks/s)
host_mem_usage                                 720032                       # Number of bytes of host memory used
host_seconds                                  5193.07                       # Real time elapsed on the host
sim_insts                                   947659008                       # Number of instructions simulated
sim_ops                                    1113505098                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       398592                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       332160                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10228032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          65553800                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        419072                       # Number of bytes read from this memory
system.physmem.bytes_read::total             76931656                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst     10228032                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        10228032                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     93992704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          94013284                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         6228                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         5190                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             159813                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1024291                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6548                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1202070                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1468636                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1471209                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           7723                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           6436                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               198179                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1270176                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8120                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1490635                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          198179                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             198179                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1821211                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 399                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1821610                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1821211                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          7723                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          6436                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              198179                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1270575                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8120                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3312245                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1202070                       # Number of read requests accepted
system.physmem.writeReqs                      2120779                       # Number of write requests accepted
system.physmem.readBursts                     1202070                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    2120779                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 76896960                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     35520                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 132496640                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  76931656                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              135585764                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      555                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   50494                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          39336                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               72977                       # Per bank write bursts
system.physmem.perBankRdBursts::1               77412                       # Per bank write bursts
system.physmem.perBankRdBursts::2               73227                       # Per bank write bursts
system.physmem.perBankRdBursts::3               70716                       # Per bank write bursts
system.physmem.perBankRdBursts::4               69716                       # Per bank write bursts
system.physmem.perBankRdBursts::5               78531                       # Per bank write bursts
system.physmem.perBankRdBursts::6               70002                       # Per bank write bursts
system.physmem.perBankRdBursts::7               72888                       # Per bank write bursts
system.physmem.perBankRdBursts::8               66687                       # Per bank write bursts
system.physmem.perBankRdBursts::9              126636                       # Per bank write bursts
system.physmem.perBankRdBursts::10              72169                       # Per bank write bursts
system.physmem.perBankRdBursts::11              76842                       # Per bank write bursts
system.physmem.perBankRdBursts::12              69750                       # Per bank write bursts
system.physmem.perBankRdBursts::13              69617                       # Per bank write bursts
system.physmem.perBankRdBursts::14              66498                       # Per bank write bursts
system.physmem.perBankRdBursts::15              67847                       # Per bank write bursts
system.physmem.perBankWrBursts::0              128572                       # Per bank write bursts
system.physmem.perBankWrBursts::1              129591                       # Per bank write bursts
system.physmem.perBankWrBursts::2              133621                       # Per bank write bursts
system.physmem.perBankWrBursts::3              133794                       # Per bank write bursts
system.physmem.perBankWrBursts::4              127990                       # Per bank write bursts
system.physmem.perBankWrBursts::5              135547                       # Per bank write bursts
system.physmem.perBankWrBursts::6              129190                       # Per bank write bursts
system.physmem.perBankWrBursts::7              132517                       # Per bank write bursts
system.physmem.perBankWrBursts::8              125103                       # Per bank write bursts
system.physmem.perBankWrBursts::9              133352                       # Per bank write bursts
system.physmem.perBankWrBursts::10             128272                       # Per bank write bursts
system.physmem.perBankWrBursts::11             129497                       # Per bank write bursts
system.physmem.perBankWrBursts::12             125797                       # Per bank write bursts
system.physmem.perBankWrBursts::13             127747                       # Per bank write bursts
system.physmem.perBankWrBursts::14             124476                       # Per bank write bursts
system.physmem.perBankWrBursts::15             125194                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         166                       # Number of times write queue was full causing retry
system.physmem.totGap                    51609997338500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1202055                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                2118206                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1132428                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     62352                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       724                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       310                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       460                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       547                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       490                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       762                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       454                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1875                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      116                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      114                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      110                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    51481                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    61019                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                   101890                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   106045                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   113976                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   152332                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   126167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   115190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   114656                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   107766                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   107346                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   140408                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   114567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   109101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   121792                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   109844                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   105744                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   103641                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     5730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     5398                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     6493                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     7698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     7852                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     7029                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     7221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     7920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     6653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     6549                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     5561                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     5785                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     4638                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     4213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     3839                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     3050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     2469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      631                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      605                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      519                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      428                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      385                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      344                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       720627                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      290.570872                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     167.798815                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     325.942314                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         295355     40.99%     40.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       175877     24.41%     65.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        63976      8.88%     74.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        35683      4.95%     79.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        24604      3.41%     82.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        16955      2.35%     84.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        13020      1.81%     86.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        11401      1.58%     88.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        83756     11.62%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         720627                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         99482                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        12.077512                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      124.901364                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          99480    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           99482                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         99482                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.810398                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.292150                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       17.172998                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31           95801     96.30%     96.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47            1933      1.94%     98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63             403      0.41%     98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79             315      0.32%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95             148      0.15%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111            160      0.16%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127           333      0.33%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143           129      0.13%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            31      0.03%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175            15      0.02%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            63      0.06%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            32      0.03%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            14      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             6      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             1      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             4      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             7      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             7      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             9      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             8      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            20      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             6      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             4      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415             5      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::432-447             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::448-463             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::464-479             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             8      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::688-703             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-719             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::720-735             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::736-751             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           99482                       # Writes before turning the bus around for reads
system.physmem.totQLat                    16741886044                       # Total ticks spent queuing
system.physmem.totMemAccLat               39270292294                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6007575000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13933.98                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  32683.98                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.49                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.57                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.49                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.63                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.76                       # Average write queue length when enqueuing
system.physmem.readRowHits                     927538                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1623609                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.20                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.42                       # Row buffer hit rate for writes
system.physmem.avgGap                     15531851.53                       # Average gap between requests
system.physmem.pageHitRate                      77.97                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2802990960                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1529409750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4566611400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               6809326560                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3370914184560                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1308588544890                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29818114243500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34513325311620                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.733317                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49604286854347                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1723371260000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    282340388153                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2644949160                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1443176625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4805158800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               6605958240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3370914184560                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1300507873200                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29825202552000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34512123852585                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.710038                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49616091454429                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1723371260000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    270535519321                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             16                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               260066829                       # Number of BP lookups
system.cpu.branchPred.condPredicted         182351604                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12179122                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            192997810                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               135975989                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             70.454680                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                31593975                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2147293                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    583127                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                583127                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        22581                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       191165                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples       583127                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0          583127    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       583127                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       213746                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 24576.454072                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 20707.683114                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 15710.461946                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       211230     98.82%     98.82% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         2148      1.00%     99.83% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607          131      0.06%     99.89% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          118      0.06%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679           73      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           32      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       213746                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    -15748296                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       -15748296    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    -15748296                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        191166     89.44%     89.44% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         22581     10.56%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       213747                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       583127                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       583127                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       213747                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       213747                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       796874                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    182952995                       # DTB read hits
system.cpu.dtb.read_misses                     481784                       # DTB read misses
system.cpu.dtb.write_hits                   162354187                       # DTB write hits
system.cpu.dtb.write_misses                    101343                       # DTB write misses
system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               47075                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1109                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    80213                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       854                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  14789                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     23472                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                183434779                       # DTB read accesses
system.cpu.dtb.write_accesses               162455530                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         345307182                       # DTB hits
system.cpu.dtb.misses                          583127                       # DTB misses
system.cpu.dtb.accesses                     345890309                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    136411                       # Table walker walks requested
system.cpu.itb.walker.walksLong                136411                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1074                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       118764                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       136411                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          136411    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       136411                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       119838                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 26864.678099                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 23079.638443                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 17315.603436                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       117018     97.65%     97.65% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071         2553      2.13%     99.78% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607          159      0.13%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           57      0.05%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679           28      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           18      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       119838                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    -16365796                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       -16365796    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    -16365796                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        118764     99.10%     99.10% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1074      0.90%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       119838                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136411                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       136411                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       119838                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       119838                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       256249                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    452746266                       # ITB inst hits
system.cpu.itb.inst_misses                     136411                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               47075                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1109                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    57592                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    369764                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                452882677                       # ITB inst accesses
system.cpu.itb.hits                         452746266                       # DTB hits
system.cpu.itb.misses                          136411                       # DTB misses
system.cpu.itb.accesses                     452882677                       # DTB accesses
system.cpu.numCycles                       2486475408                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   947659008                       # Number of instructions committed
system.cpu.committedOps                    1113505098                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      96546934                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      7735                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                 100734690731                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.623808                       # CPI: cycles per instruction
system.cpu.ipc                               0.381125                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16595                       # number of quiesce instructions executed
system.cpu.tickCycles                      1791502894                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       694972514                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements          11092406                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.957332                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           328965151                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          11092918                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.655421                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4320792250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.957332                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999917                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999917                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          395                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1382417296                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1382417296                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    168207875                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       168207875                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    151549113                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      151549113                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       490930                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        490930                       # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       335942                       # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total       335942                       # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      4008865                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      4008865                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      4323127                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4323127                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     319756988                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        319756988                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    320247918                       # number of overall hits
system.cpu.dcache.overall_hits::total       320247918                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      6578537                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       6578537                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      4302299                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4302299                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1473808                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1473808                       # number of SoftPFReq misses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1244599                       # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total      1244599                       # number of WriteInvalidateReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       315993                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       315993                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     10880836                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       10880836                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     12354644                       # number of overall misses
system.cpu.dcache.overall_misses::total      12354644                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 106697920457                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 106697920457                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 153242376598                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 153242376598                       # number of WriteReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  35461255171                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::total  35461255171                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4805977234                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   4805977234                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 259940297055                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 259940297055                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 259940297055                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 259940297055                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    174786412                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    174786412                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    155851412                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    155851412                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1964738                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1964738                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1580541                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total      1580541                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4324858                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4324858                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      4323128                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4323128                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    330637824                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    330637824                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    332602562                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    332602562                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037638                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.037638                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027605                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.027605                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.750130                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.750130                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.787451                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.787451                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.073064                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.073064                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.032909                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.032909                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037145                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037145                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.095592                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.095592                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35618.718410                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35618.718410                       # average WriteReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28492.112858                       # average WriteInvalidateReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28492.112858                       # average WriteInvalidateReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15209.125626                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15209.125626                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23889.735775                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23889.735775                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21039.885654                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21039.885654                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      8509656                       # number of writebacks
system.cpu.dcache.writebacks::total           8509656                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       799615                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       799615                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1895946                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1895946                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data          144                       # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::total          144                       # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69791                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        69791                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2695561                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2695561                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2695561                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2695561                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5778922                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5778922                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2406353                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2406353                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1466300                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1466300                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1244455                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1244455                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       246202                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       246202                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      8185275                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      8185275                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9651575                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9651575                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33696                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33705                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33705                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67401                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67401                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  84566997800                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  84566997800                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  78901247228                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  78901247228                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  22730570766                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  22730570766                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  33591268829                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  33591268829                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3240983258                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3240983258                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        80500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        80500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163468245028                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 163468245028                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186198815794                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 186198815794                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5751743992                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5751743992                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5611366250                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5611366250                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11363110242                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11363110242                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033063                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033063                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015440                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015440                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.746308                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.746308                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.787360                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.787360                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.056927                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056927                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024756                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024756                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029018                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.029018                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14633.697738                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14633.697738                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32788.725190                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32788.725190                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15501.991929                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15501.991929                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 26992.754924                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26992.754924                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13163.919294                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13163.919294                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        80500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        80500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170695.156458                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170695.156458                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166484.683281                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166484.683281                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168589.638759                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168589.638759                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          24538707                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.926996                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           427825373                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          24539219                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             17.434352                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       22330853250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.926996                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999857                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999857                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         476903830                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        476903830                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    427825373                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       427825373                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     427825373                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        427825373                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    427825373                       # number of overall hits
system.cpu.icache.overall_hits::total       427825373                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     24539229                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      24539229                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     24539229                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       24539229                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     24539229                       # number of overall misses
system.cpu.icache.overall_misses::total      24539229                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 326974610838                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 326974610838                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 326974610838                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 326974610838                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 326974610838                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 326974610838                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    452364602                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    452364602                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    452364602                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    452364602                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    452364602                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    452364602                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054247                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.054247                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.054247                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.054247                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.054247                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.054247                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13324.567403                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13324.567403                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13324.567403                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13324.567403                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13324.567403                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13324.567403                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24539229                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     24539229                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     24539229                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     24539229                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     24539229                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     24539229                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52294                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        52294                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52294                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        52294                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 290116862082                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290116862082                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 290116862082                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   4024065500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   4024065500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   4024065500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   4024065500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054247                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054247                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054247                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.054247                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054247                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.054247                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11822.574462                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11822.574462                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11822.574462                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11822.574462                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11822.574462                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11822.574462                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76950.806976                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76950.806976                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76950.806976                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76950.806976                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1594461                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65370.145273                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           40075906                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1658209                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            24.168187                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       6394381000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36356.724167                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   340.112458                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   426.747711                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  8173.252666                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 20073.308271                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.554760                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005190                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006512                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124714                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.306294                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.997469                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          294                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63454                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          294                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          492                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2445                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5512                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54953                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004486                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.968231                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        368332557                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       368332557                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       961086                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       281097                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst     24431679                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      7167695                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total       32841557                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      8509656                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      8509656                       # number of Writeback hits
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       701377                       # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total       701377                       # number of WriteInvalidateReq hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        10751                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        10751                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1655224                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1655224                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       961086                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       281097                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     24431679                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8822919                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        34496781                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       961086                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       281097                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     24431679                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8822919                       # number of overall hits
system.cpu.l2cache.overall_hits::total       34496781                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6228                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5190                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst       107547                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       323472                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       442437                       # number of ReadReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       543077                       # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total       543077                       # number of WriteInvalidateReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        38541                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        38541                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       702095                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       702095                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         6228                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         5190                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       107547                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1025567                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1144532                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         6228                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         5190                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       107547                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1025567                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1144532                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    538586008                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    452279750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   8825389448                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  27527866547                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  37344121753                       # number of ReadReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data      5340829                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::total      5340829                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    585352278                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    585352278                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        79500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        79500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  57779848170                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  57779848170                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    538586008                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    452279750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   8825389448                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  85307714717                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  95123969923                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    538586008                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    452279750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   8825389448                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  85307714717                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  95123969923                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       967314                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       286287                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst     24539226                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7491167                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total     33283994                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      8509656                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      8509656                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1244454                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total      1244454                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        49292                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        49292                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2357319                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2357319                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       967314                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       286287                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     24539226                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9848486                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     35641313                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       967314                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       286287                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     24539226                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9848486                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     35641313                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006438                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.018129                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.004383                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.043180                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.013293                       # miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.436398                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.436398                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.781892                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.781892                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.297836                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.297836                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006438                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018129                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004383                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.104134                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.032113                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006438                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.018129                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004383                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.104134                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.032113                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86478.164419                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87144.460501                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82060.768297                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85101.234564                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84405.512543                       # average ReadReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data     9.834386                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     9.834386                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15187.781272                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15187.781272                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82296.339057                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82296.339057                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86478.164419                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87144.460501                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82060.768297                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.025440                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 83111.673525                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86478.164419                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87144.460501                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82060.768297                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.025440                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 83111.673525                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1362005                       # number of writebacks
system.cpu.l2cache.writebacks::total          1362005                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           23                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           23                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           23                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6228                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5190                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       107545                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       323451                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       442414                       # number of ReadReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data       543077                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       543077                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        38541                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        38541                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       702095                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       702095                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6228                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5190                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       107545                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1025546                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1144509                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6228                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5190                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       107545                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1025546                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1144509                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52294                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        85990                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33705                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33705                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52294                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67401                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119695                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    460278992                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    386982750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   7477222552                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  23476189203                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  31800673497                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  18301171671                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  18301171671                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    683876035                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    683876035                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        67500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        67500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  49002604830                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  49002604830                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    460278992                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    386982750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7477222552                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  72478794033                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  80803278327                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    460278992                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    386982750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7477222552                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  72478794033                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  80803278327                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3108920000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5279396750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8388316750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5172507000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5172507000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3108920000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10451903750                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13560823750                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006438                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018129                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.004383                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.043178                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013292                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.436398                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.436398                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.781892                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.781892                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.297836                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.297836                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006438                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018129                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004383                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.104132                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.032112                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006438                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018129                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004383                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.104132                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.032112                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74563.150289                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69526.454526                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72580.357467                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71879.898685                       # average ReadReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33699.036547                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33699.036547                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17744.117563                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17744.117563                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        67500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        67500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.835215                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.835215                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74563.150289                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69526.454526                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70673.372070                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70600.823870                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73904.783558                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74563.150289                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156677.253977                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97549.909873                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153464.085447                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153464.085447                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155070.455186                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113294.822257                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq       33827953                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      33819864                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33705                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33705                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      8509656                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1351233                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1244454                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        49295                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        49296                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2357319                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2357319                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     49183042                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     30929702                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       693856                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2262449                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          83069049                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1573857216                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1254806154                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2290296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7738512                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2838692178                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      565529                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     46129162                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.039419                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.194589                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1           44310813     96.06%     96.06% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2            1818349      3.94%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       46129162                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    32777837483                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1164000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   36924053878                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   15679140875                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     408249695                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1295905979                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40311                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40311                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp              29907                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230980                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230980                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353764                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334352                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334352                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           607011706                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148422470                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              174500                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115472                       # number of replacements
system.iocache.tags.tagsinuse               10.439528                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115488                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13142428728000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.524738                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.914790                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.220296                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.432174                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.652471                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039767                       # Number of tag accesses
system.iocache.tags.data_accesses             1039767                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8826                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8863                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8826                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8866                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8826                       # number of overall misses
system.iocache.overall_misses::total             8866                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1599431674                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1604503674                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       352500                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       352500                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19839532562                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  19839532562                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5424500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1599431674                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1604856174                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5424500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1599431674                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1604856174                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8826                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8863                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8826                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8866                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8826                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8866                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 181218.181962                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 181033.924630                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117500                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117500                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186000.267775                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 186000.267775                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 181218.181962                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 181012.426573                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 181218.181962                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 181012.426573                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        109629                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                16167                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.781035                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8826                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8863                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8826                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8866                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8826                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8866                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3142000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1139388578                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1142530578                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       193500                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       193500                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14292968598                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14292968598                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3335500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1139388578                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1142724078                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3335500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1139388578                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1142724078                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129094.559030                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 128910.140810                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        64500                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        64500                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133999.930605                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133999.930605                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 129094.559030                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 128888.346267                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 129094.559030                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 128888.346267                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              537267                       # Transaction distribution
system.membus.trans_dist::ReadResp             537267                       # Transaction distribution
system.membus.trans_dist::WriteReq              33705                       # Transaction distribution
system.membus.trans_dist::WriteResp             33705                       # Transaction distribution
system.membus.trans_dist::Writeback           1468636                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       649570                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       649570                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            39342                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           39343                       # Transaction distribution
system.membus.trans_dist::ReadExReq            701468                       # Transaction distribution
system.membus.trans_dist::ReadExResp           701468                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6912                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4923341                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5052989                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335373                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       335373                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5388362                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13824                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198447468                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    198617866                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14069952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14069952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               212687818                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2980                       # Total snoops (count)
system.membus.snoop_fanout::samples           3430156                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3430156    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3430156                       # Request fanout histogram
system.membus.reqLayer0.occupancy            99903000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5637000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         12263986868                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7071367467                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          151550030                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped

---------- End Simulation Statistics   ----------