path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.643658                       # Number of seconds simulated
sim_ticks                                51643657651000                       # Number of ticks simulated
final_tick                               51643657651000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 290656                       # Simulator instruction rate (inst/s)
host_op_rate                                   346501                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            16573581112                       # Simulator tick rate (ticks/s)
host_mem_usage                                 686852                       # Number of bytes of host memory used
host_seconds                                  3116.02                       # Real time elapsed on the host
sim_insts                                   905689769                       # Number of instructions simulated
sim_ops                                    1079705427                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker       481856                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       390720                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           7301696                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          78480968                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        396608                       # Number of bytes read from this memory
system.physmem.bytes_read::total             87051848                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      7301696                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7301696                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    106840192                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total         106860772                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         7529                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         6105                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             114089                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1226278                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6197                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1360198                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1669378                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1671951                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           9330                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           7566                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               141386                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1519663                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7680                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1685625                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          141386                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             141386                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2068796                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 399                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2069194                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2068796                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          9330                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          7566                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              141386                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1520062                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7680                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3754820                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1360198                       # Number of read requests accepted
system.physmem.writeReqs                      1671951                       # Number of write requests accepted
system.physmem.readBursts                     1360198                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1671951                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 86990528                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     62144                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 106858944                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  87051848                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              106860772                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      971                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2249                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               83237                       # Per bank write bursts
system.physmem.perBankRdBursts::1               85225                       # Per bank write bursts
system.physmem.perBankRdBursts::2               82489                       # Per bank write bursts
system.physmem.perBankRdBursts::3               80125                       # Per bank write bursts
system.physmem.perBankRdBursts::4               87648                       # Per bank write bursts
system.physmem.perBankRdBursts::5               94125                       # Per bank write bursts
system.physmem.perBankRdBursts::6               89556                       # Per bank write bursts
system.physmem.perBankRdBursts::7               88166                       # Per bank write bursts
system.physmem.perBankRdBursts::8               78937                       # Per bank write bursts
system.physmem.perBankRdBursts::9               92012                       # Per bank write bursts
system.physmem.perBankRdBursts::10              85547                       # Per bank write bursts
system.physmem.perBankRdBursts::11              87304                       # Per bank write bursts
system.physmem.perBankRdBursts::12              77322                       # Per bank write bursts
system.physmem.perBankRdBursts::13              84061                       # Per bank write bursts
system.physmem.perBankRdBursts::14              80795                       # Per bank write bursts
system.physmem.perBankRdBursts::15              82678                       # Per bank write bursts
system.physmem.perBankWrBursts::0              101181                       # Per bank write bursts
system.physmem.perBankWrBursts::1              102649                       # Per bank write bursts
system.physmem.perBankWrBursts::2              102280                       # Per bank write bursts
system.physmem.perBankWrBursts::3              101626                       # Per bank write bursts
system.physmem.perBankWrBursts::4              106705                       # Per bank write bursts
system.physmem.perBankWrBursts::5              111943                       # Per bank write bursts
system.physmem.perBankWrBursts::6              107546                       # Per bank write bursts
system.physmem.perBankWrBursts::7              108809                       # Per bank write bursts
system.physmem.perBankWrBursts::8              101631                       # Per bank write bursts
system.physmem.perBankWrBursts::9              107791                       # Per bank write bursts
system.physmem.perBankWrBursts::10             102979                       # Per bank write bursts
system.physmem.perBankWrBursts::11             104017                       # Per bank write bursts
system.physmem.perBankWrBursts::12              98121                       # Per bank write bursts
system.physmem.perBankWrBursts::13             104909                       # Per bank write bursts
system.physmem.perBankWrBursts::14             102656                       # Per bank write bursts
system.physmem.perBankWrBursts::15             104828                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         458                       # Number of times write queue was full causing retry
system.physmem.totGap                    51643655791000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1360183                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1669378                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1282957                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     70161                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       871                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       328                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       466                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       444                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       571                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       445                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       945                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       570                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      281                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      269                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      186                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      159                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      112                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      100                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       95                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       95                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       86                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       78                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    31821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    39955                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    90821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    97628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   100256                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    96883                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   101095                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    99439                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   101345                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    97950                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   101005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   102593                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    99923                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    96951                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    96056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    95043                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    92451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    92535                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2699                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2382                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1311                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      933                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      851                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      726                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      998                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      719                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      738                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      777                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      867                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      880                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                     1479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                     1458                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                     1009                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       752315                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      257.670024                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     155.219861                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     291.691185                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         319843     42.51%     42.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       192789     25.63%     68.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        70379      9.35%     77.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        39533      5.25%     82.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        27835      3.70%     86.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        18762      2.49%     88.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        14354      1.91%     90.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        11626      1.55%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        57194      7.60%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         752315                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         89671                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        15.157342                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       22.777727                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-255           89658     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-511             7      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-767             1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-1023            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1279            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-1791            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5632-5887            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           89671                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         89671                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.619966                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.881543                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.948219                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23           81046     90.38%     90.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31            5562      6.20%     96.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39            1304      1.45%     98.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47             395      0.44%     98.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             213      0.24%     98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63             159      0.18%     98.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71             654      0.73%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79             203      0.23%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              30      0.03%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               3      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103              5      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111            17      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119             4      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             4      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            32      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143            13      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151             6      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199            10      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           89671                       # Writes before turning the bus around for reads
system.physmem.totQLat                    40684785332                       # Total ticks spent queuing
system.physmem.totMemAccLat               66170291582                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6796135000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       29932.30                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  48682.30                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.68                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.07                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.69                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.07                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.41                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1052962                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1223619                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.47                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.28                       # Row buffer hit rate for writes
system.physmem.avgGap                     17032031.01                       # Average gap between requests
system.physmem.pageHitRate                      75.16                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2732670780                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1452445170                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4930676940                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4399097580                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           51881762400.000015                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            47976087180                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             3104058720                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy      109980529290                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy       71485388640                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       12273611587950                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             12571576503750                       # Total energy per rank (pJ)
system.physmem_0.averagePower              243.429243                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           51530314812756                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE     5413929000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     22045432000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   51102968874750                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 186159553736                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     85883432494                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 241186429020                       # Time in different power states
system.physmem_1.actEnergy                 2638872600                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1402590255                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4774203840                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4316585040                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           51214263360.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            48316306500                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             3067085280                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy      106463182980                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy       70942598400                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       12275647651350                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             12568805141895                       # Total energy per rank (pJ)
system.physmem_1.averagePower              243.375580                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           51529660585796                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE     5336166484                       # Time in different power states
system.physmem_1.memoryStateTime::REF     21762952000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   51111446865750                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 184746715790                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     86892179220                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 233472771756                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             16                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               230671595                       # Number of BP lookups
system.cpu.branchPred.condPredicted         148977251                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12591272                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            161205478                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                94166388                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             58.413888                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                32707519                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2199358                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         7428890                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            5357971                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses          2070919                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       851352                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                    612824                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                612824                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        25045                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       213625                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples       612824                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0          612824    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       612824                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       238670                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 26656.848368                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 22869.063207                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 18178.269726                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       235680     98.75%     98.75% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         2495      1.05%     99.79% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607          126      0.05%     99.85% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          157      0.07%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679          125      0.05%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           32      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751           14      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287            6      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359           28      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::786432-851967            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::917504-983039            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       238670                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    411876000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       411876000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    411876000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        213626     89.51%     89.51% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         25045     10.49%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       238671                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       612824                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       612824                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       238671                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       238671                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       851495                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    191427667                       # DTB read hits
system.cpu.dtb.read_misses                     503751                       # DTB read misses
system.cpu.dtb.write_hits                   170371453                       # DTB write hits
system.cpu.dtb.write_misses                    109073                       # DTB write misses
system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               50563                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1145                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    82805                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       891                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  16210                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     24062                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                191931418                       # DTB read accesses
system.cpu.dtb.write_accesses               170480526                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         361799120                       # DTB hits
system.cpu.dtb.misses                          612824                       # DTB misses
system.cpu.dtb.accesses                     362411944                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                    137744                       # Table walker walks requested
system.cpu.itb.walker.walksLong                137744                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1060                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       119122                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       137744                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          137744    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       137744                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       120182                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28731.482252                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24330.551658                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 24049.037609                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       116919     97.28%     97.28% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071         2876      2.39%     99.68% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607          146      0.12%     99.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143          107      0.09%     99.89% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679           36      0.03%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           28      0.02%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751            3      0.00%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            3      0.00%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359           64      0.05%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       120182                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    411203500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       411203500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    411203500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        119122     99.12%     99.12% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1060      0.88%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       120182                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       137744                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       137744                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       120182                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       120182                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       257926                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    367199991                       # ITB inst hits
system.cpu.itb.inst_misses                     137744                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               50563                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1145                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    59110                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    331525                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                367337735                       # ITB inst accesses
system.cpu.itb.hits                         367199991                       # DTB hits
system.cpu.itb.misses                          137744                       # DTB misses
system.cpu.itb.accesses                     367337735                       # DTB accesses
system.cpu.numPwrStateTransitions               33588                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples         16794                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     3006267839.468917                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    59370181603.459618                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         7493     44.62%     44.62% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10         9266     55.17%     99.79% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.82% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            3      0.02%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::9e+11-9.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 1988777658384                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total           16794                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    1156395554959                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 50487262096041                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                       2312845645                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   905689769                       # Number of instructions committed
system.cpu.committedOps                    1079705427                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      38872378                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      7934                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                 100975614107                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.553684                       # CPI: cycles per instruction
system.cpu.ipc                               0.391591                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                   1      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu               721452382     66.82%     66.82% # Class of committed instruction
system.cpu.op_class_0::IntMult                2371003      0.22%     67.04% # Class of committed instruction
system.cpu.op_class_0::IntDiv                  100622      0.01%     67.05% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     8      0.00%     67.05% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                    13      0.00%     67.05% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                    21      0.00%     67.05% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     67.05% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc                 0      0.00%     67.05% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     67.05% # Class of committed instruction
system.cpu.op_class_0::FloatMisc               107773      0.01%     67.06% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.06% # Class of committed instruction
system.cpu.op_class_0::MemRead              185747611     17.20%     84.26% # Class of committed instruction
system.cpu.op_class_0::MemWrite             169152555     15.67%     99.93% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead            112557      0.01%     99.94% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite           660881      0.06%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total               1079705427                       # Class of committed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16794                       # number of quiesce instructions executed
system.cpu.tickCycles                      1555844114                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       757001531                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements          11832637                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.995677                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           345046750                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          11833149                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.159335                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         456752500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.995677                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999992                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999992                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          398                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           45                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1449239878                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1449239878                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    176307264                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       176307264                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    158900158                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      158900158                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       537417                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        537417                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       337852                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       337852                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      4300418                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      4300418                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      4627725                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4627725                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     335545274                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        335545274                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    336082691                       # number of overall hits
system.cpu.dcache.overall_hits::total       336082691                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      6490291                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       6490291                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      4646590                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4646590                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1620869                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1620869                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1254011                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1254011                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       329077                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       329077                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     12390892                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       12390892                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     14011761                       # number of overall misses
system.cpu.dcache.overall_misses::total      14011761                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 114759870500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 114759870500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 196713087999                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 196713087999                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  27879484500                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  27879484500                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5348350500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   5348350500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        83000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        83000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 339352442999                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 339352442999                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 339352442999                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 339352442999                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    182797555                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    182797555                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    163546748                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    163546748                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      2158286                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      2158286                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1591863                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1591863                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4629495                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4629495                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      4627726                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4627726                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    347936166                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    347936166                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    350094452                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    350094452                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035505                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.035505                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.028411                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.028411                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.750998                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.750998                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787763                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.787763                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.071083                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.071083                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.035613                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.035613                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.040023                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.040023                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.775825                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17681.775825                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42334.935512                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42334.935512                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22232.248760                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22232.248760                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16252.580703                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16252.580703                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 27387.248876                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 27387.248876                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24219.114428                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24219.114428                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          135                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    67.500000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      9058668                       # number of writebacks
system.cpu.dcache.writebacks::total           9058668                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       331345                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       331345                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2059664                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2059664                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          161                       # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total          161                       # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        73138                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        73138                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2391170                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2391170                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2391170                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2391170                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      6158946                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      6158946                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2586926                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2586926                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1613436                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1613436                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1253850                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1253850                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       255939                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       255939                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9999722                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9999722                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data     11613158                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total     11613158                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33608                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33608                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33620                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33620                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67228                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67228                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 101472833000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 101472833000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 102652778000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 102652778000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  27900020500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  27900020500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  26619580500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  26619580500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3678632000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3678632000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        82000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        82000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230745191500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 230745191500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 258645212000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 258645212000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6209488500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6209488500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6209488500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6209488500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033693                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033693                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015818                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015818                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.747554                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.747554                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787662                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787662                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.055284                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.055284                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028740                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.028740                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.033171                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.033171                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16475.681553                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16475.681553                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39681.373955                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39681.373955                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17292.300717                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17292.300717                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21230.275153                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21230.275153                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14373.081086                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14373.081086                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23075.160639                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23075.160639                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22271.737972                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22271.737972                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184762.214354                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184762.214354                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92364.617421                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92364.617421                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements          25121901                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.967924                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           341735076                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          25122413                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             13.602797                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       17226930500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.967924                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999937                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999937                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          315                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         391979921                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        391979921                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    341735076                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       341735076                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     341735076                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        341735076                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    341735076                       # number of overall hits
system.cpu.icache.overall_hits::total       341735076                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     25122423                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      25122423                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     25122423                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       25122423                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     25122423                       # number of overall misses
system.cpu.icache.overall_misses::total      25122423                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 337360587000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 337360587000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 337360587000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 337360587000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 337360587000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 337360587000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    366857499                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    366857499                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    366857499                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    366857499                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    366857499                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    366857499                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.068480                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.068480                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.068480                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.068480                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.068480                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.068480                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13428.664385                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13428.664385                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13428.664385                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13428.664385                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13428.664385                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13428.664385                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks     25121901                       # number of writebacks
system.cpu.icache.writebacks::total          25121901                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     25122423                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     25122423                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     25122423                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     25122423                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     25122423                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     25122423                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         4291                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         4291                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         4291                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         4291                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312238165000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 312238165000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312238165000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 312238165000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312238165000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 312238165000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    366344000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    366344000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    366344000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    366344000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.068480                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.068480                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.068480                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.068480                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.068480                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.068480                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12428.664425                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12428.664425                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12428.664425                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12428.664425                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12428.664425                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12428.664425                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85374.970869                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85374.970869                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85374.970869                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85374.970869                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements          1823253                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65445.001874                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           72021344                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1886697                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            38.173244                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       2050526000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  9044.623983                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   456.585654                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   458.430752                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  7955.769070                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 47529.592416                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.138010                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.006967                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006995                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.121395                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.725244                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.998611                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          236                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63208                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          233                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          882                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5962                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56005                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003601                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.964478                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        604501194                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       604501194                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker      1016248                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       265268                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1281516                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks      9058668                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      9058668                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     25118324                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     25118324                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        31922                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        31922                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1691397                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1691397                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     25012596                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     25012596                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7660453                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      7660453                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       687915                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       687915                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker      1016248                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       265268                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     25012596                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      9351850                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        35645962                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker      1016248                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       265268                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     25012596                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      9351850                       # number of overall hits
system.cpu.l2cache.overall_hits::total       35645962                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         7529                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         6105                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        13634                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         3989                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         3989                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       859845                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       859845                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       109826                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total       109826                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       367641                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       367641                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       565935                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       565935                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         7529                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         6105                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       109826                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1227486                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1350946                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         7529                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         6105                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       109826                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1227486                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1350946                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    877005000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    644825000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1521830000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     72113000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     72113000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        80500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        80500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  80528268500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  80528268500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  11692993000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total  11692993000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  40327835000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  40327835000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    877005000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    644825000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  11692993000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 120856103500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 134070926500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    877005000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    644825000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  11692993000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 120856103500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 134070926500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker      1023777                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       271373                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1295150                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks      9058668                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      9058668                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     25118324                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     25118324                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        35911                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        35911                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2551242                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2551242                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     25122422                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     25122422                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      8028094                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      8028094                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1253850                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1253850                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker      1023777                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       271373                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     25122422                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data     10579336                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     36996908                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker      1023777                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       271373                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     25122422                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data     10579336                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     36996908                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.007354                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.022497                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.010527                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.111080                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.111080                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.337030                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.337030                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004372                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004372                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.045794                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.045794                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.451358                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.451358                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.007354                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022497                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004372                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.116027                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.036515                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.007354                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022497                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004372                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.116027                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.036515                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 116483.596759                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 105622.440622                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 111620.214170                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18077.964402                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18077.964402                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93654.401084                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93654.401084                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106468.349935                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106468.349935                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109693.518949                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109693.518949                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 116483.596759                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 105622.440622                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106468.349935                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98458.233740                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 99242.254317                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 116483.596759                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 105622.440622                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106468.349935                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98458.233740                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 99242.254317                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks      1562747                       # number of writebacks
system.cpu.l2cache.writebacks::total          1562747                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           22                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         7529                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         6105                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        13634                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         3989                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         3989                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       859845                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       859845                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       109824                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total       109824                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       367619                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       367619                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       565935                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       565935                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         7529                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         6105                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       109824                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1227464                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1350922                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         7529                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         6105                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       109824                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1227464                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1350922                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         4291                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33608                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        37899                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33620                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33620                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         4291                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67228                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        71519                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    801715000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    583775000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1385490000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     76139500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     76139500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  71929817502                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  71929817502                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10594574503                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10594574503                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  36650353047                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  36650353047                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  11657372001                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  11657372001                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    801715000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    583775000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10594574503                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108580170549                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 120560235052                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    801715000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    583775000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10594574503                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108580170549                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 120560235052                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    299820000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5789264500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6089084500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    299820000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5789264500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6089084500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.007354                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.022497                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010527                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.111080                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.111080                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.337030                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.337030                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004372                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004372                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.045792                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.045792                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.451358                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.451358                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.007354                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.022497                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004372                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.116025                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.036514                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.007354                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.022497                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004372                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.116025                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.036514                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 95622.440622                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 101620.214170                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19087.365254                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19087.365254                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83654.399923                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 83654.399923                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96468.663525                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96468.663525                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99696.569130                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99696.569130                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20598.429150                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20598.429150                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 95622.440622                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96468.663525                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88458.945068                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89242.928202                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 95622.440622                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96468.663525                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88458.945068                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89242.928202                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69871.824749                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172258.524756                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160666.099369                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69871.824749                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86113.888558                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85139.396524                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests     74678701                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     37723093                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4208                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1985                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1985                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq        1826986                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      34978302                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33620                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33620                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty     10621415                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     25121901                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      3034475                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        35914                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        35915                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2551242                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2551242                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     25122423                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      8030982                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1284314                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1253880                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     75375327                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     35706122                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       683214                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2401023                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total         114165686                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3215911232                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1257073518                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2170984                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      8190216                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         4483345950                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     2351379                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic             104018568                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples     40708735                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.018149                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.133491                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           39969899     98.19%     98.19% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             738836      1.81%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       40708735                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    72100713496                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1533365                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   37694541038                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   16565349400                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     411872936                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1377265960                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40237                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40237                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136485                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136485                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122360                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231004                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231004                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353444                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47498                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155490                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334448                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334448                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492024                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             37126500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               334500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               16000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25225000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36490500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569036756                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92542000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147764000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115484                       # number of replacements
system.iocache.tags.tagsinuse               10.444243                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115500                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13137487927000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     5.867221                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     4.577022                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.366701                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.286064                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.652765                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039875                       # Number of tag accesses
system.iocache.tags.data_accesses             1039875                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8838                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8875                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115502                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115542                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115502                       # number of overall misses
system.iocache.overall_misses::total           115542                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   2014766150                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   2019852150                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13376583606                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13376583606                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15391349756                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15396786756                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15391349756                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15396786756                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8838                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8875                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115502                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115542                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115502                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115542                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 227966.298936                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 227588.974648                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125408.606521                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125408.606521                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 133256.131980                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 133257.055928                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 133256.131980                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 133257.055928                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         51744                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3369                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    15.358860                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8838                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8875                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115502                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115542                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115502                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115542                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1572866150                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1576102150                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8037847459                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8037847459                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9610713609                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9614150609                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9610713609                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9614150609                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177966.298936                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 177588.974648                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75356.703846                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75356.703846                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 83208.200802                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 83209.141343                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 83208.200802                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 83209.141343                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests       3974449                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1973040                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3773                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               37899                       # Transaction distribution
system.membus.trans_dist::ReadResp             537851                       # Transaction distribution
system.membus.trans_dist::WriteReq              33620                       # Transaction distribution
system.membus.trans_dist::WriteResp             33620                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1669378                       # Transaction distribution
system.membus.trans_dist::CleanEvict           268224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4552                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               7                       # Transaction distribution
system.membus.trans_dist::ReadExReq            859285                       # Transaction distribution
system.membus.trans_dist::ReadExResp           859285                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        499952                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        672599                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        30234                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122360                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6910                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5106407                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5235709                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237223                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237223                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5472932                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155490                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13820                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    186691628                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    186861678                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7220992                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7220992                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               194082670                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            33575                       # Total snoops (count)
system.membus.snoopTraffic                     213376                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2107909                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.016147                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.126040                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2073873     98.39%     98.39% # Request fanout histogram
system.membus.snoop_fanout::1                   34036      1.61%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2107909                       # Request fanout histogram
system.membus.reqLayer0.occupancy            99276000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5601000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         10934593718                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7287611424                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           76573457                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------