path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.557115                       # Number of seconds simulated
sim_ticks                                51557114994500                       # Number of ticks simulated
final_tick                               51557114994500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  81227                       # Simulator instruction rate (inst/s)
host_op_rate                                    95475                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3758004040                       # Simulator tick rate (ticks/s)
host_mem_usage                                 668380                       # Number of bytes of host memory used
host_seconds                                 13719.28                       # Real time elapsed on the host
sim_insts                                  1114380469                       # Number of instructions simulated
sim_ops                                    1309844804                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.ide        437568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker      1002304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker      1237760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           6145632                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         128560840                       # Number of bytes read from this memory
system.physmem.bytes_read::total            137384104                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      6145632                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6145632                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    102180288                       # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data      102783780                       # Number of bytes written to this memory
system.physmem.bytes_written::total         211790564                       # Number of bytes written to this memory
system.physmem.num_reads::realview.ide           6837                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker        15661                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker        19340                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             111978                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            2008776                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               2162592                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1596567                       # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data           1608248                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              3311479                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.ide             8487                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker          19441                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker          24008                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               119200                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2493562                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2664697                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          119200                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             119200                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1981885                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide          132406                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1993591                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4107882                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1981885                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide          140894                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker         19441                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker         24008                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              119200                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4487152                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6772580                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       2162592                       # Number of read requests accepted
system.physmem.writeReqs                      3311479                       # Number of write requests accepted
system.physmem.readBursts                     2162592                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    3311479                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                138204608                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    201280                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 207618304                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 137384104                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              211790564                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     3145                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   67428                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          48470                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              140382                       # Per bank write bursts
system.physmem.perBankRdBursts::1              139333                       # Per bank write bursts
system.physmem.perBankRdBursts::2              140658                       # Per bank write bursts
system.physmem.perBankRdBursts::3              133921                       # Per bank write bursts
system.physmem.perBankRdBursts::4              130324                       # Per bank write bursts
system.physmem.perBankRdBursts::5              134612                       # Per bank write bursts
system.physmem.perBankRdBursts::6              126217                       # Per bank write bursts
system.physmem.perBankRdBursts::7              133097                       # Per bank write bursts
system.physmem.perBankRdBursts::8              129592                       # Per bank write bursts
system.physmem.perBankRdBursts::9              157619                       # Per bank write bursts
system.physmem.perBankRdBursts::10             133394                       # Per bank write bursts
system.physmem.perBankRdBursts::11             133867                       # Per bank write bursts
system.physmem.perBankRdBursts::12             132326                       # Per bank write bursts
system.physmem.perBankRdBursts::13             132284                       # Per bank write bursts
system.physmem.perBankRdBursts::14             133117                       # Per bank write bursts
system.physmem.perBankRdBursts::15             128704                       # Per bank write bursts
system.physmem.perBankWrBursts::0              201659                       # Per bank write bursts
system.physmem.perBankWrBursts::1              203665                       # Per bank write bursts
system.physmem.perBankWrBursts::2              231223                       # Per bank write bursts
system.physmem.perBankWrBursts::3              188549                       # Per bank write bursts
system.physmem.perBankWrBursts::4              224931                       # Per bank write bursts
system.physmem.perBankWrBursts::5              188791                       # Per bank write bursts
system.physmem.perBankWrBursts::6              176287                       # Per bank write bursts
system.physmem.perBankWrBursts::7              226882                       # Per bank write bursts
system.physmem.perBankWrBursts::8              203233                       # Per bank write bursts
system.physmem.perBankWrBursts::9              233524                       # Per bank write bursts
system.physmem.perBankWrBursts::10             253232                       # Per bank write bursts
system.physmem.perBankWrBursts::11             198347                       # Per bank write bursts
system.physmem.perBankWrBursts::12             181957                       # Per bank write bursts
system.physmem.perBankWrBursts::13             175879                       # Per bank write bursts
system.physmem.perBankWrBursts::14             180282                       # Per bank write bursts
system.physmem.perBankWrBursts::15             175595                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         190                       # Number of times write queue was full causing retry
system.physmem.totGap                    51557113761500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 2141307                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                3308906                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1296550                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    764534                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     68768                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     25837                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       916                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       532                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       444                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       333                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       233                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       165                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      157                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      144                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      129                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      131                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      122                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    55343                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    88539                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                   132669                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   172060                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   179259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   199827                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   201826                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   215089                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   217686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   234764                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   216813                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   209096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   190795                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   202440                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   157954                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   153989                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   157951                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   145311                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     9323                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     7805                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     6801                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     6277                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     6099                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     5695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     5430                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     5062                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     4998                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     4548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     4335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     4121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     4055                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     3702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     3601                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     3413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     3461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     3051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     2987                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     2852                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     2836                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     2345                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                     2139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                     1813                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                     1591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                     1247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      993                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      356                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      474                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1034839                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      334.179783                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     188.532509                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     356.014667                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         392208     37.90%     37.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       234584     22.67%     60.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        87901      8.49%     69.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        49413      4.77%     73.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        38348      3.71%     77.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        26689      2.58%     80.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        21988      2.12%     82.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        25501      2.46%     84.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       158207     15.29%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1034839                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples        135592                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        15.925969                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      128.724301                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047         135587    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total          135592                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples        135592                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.924981                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       20.930688                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       17.164557                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23          101303     74.71%     74.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31            7599      5.60%     80.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39           12845      9.47%     89.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47            3908      2.88%     92.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55            2324      1.71%     94.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63             925      0.68%     95.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71            2932      2.16%     97.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79            1250      0.92%     98.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             889      0.66%     98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95             249      0.18%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103            327      0.24%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111           193      0.14%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119           473      0.35%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127            16      0.01%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            22      0.02%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143            28      0.02%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            17      0.01%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159            31      0.02%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167            89      0.07%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175            56      0.04%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183            42      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             7      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199            15      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             2      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215            15      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             6      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             9      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             5      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             5      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-279             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total          135592                       # Writes before turning the bus around for reads
system.physmem.totQLat                    43990891280                       # Total ticks spent queuing
system.physmem.totMemAccLat               84480522530                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  10797235000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       20371.37                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  39121.37                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.68                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.03                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.66                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.11                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.29                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1747291                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   2621349                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.91                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.80                       # Row buffer hit rate for writes
system.physmem.avgGap                      9418422.55                       # Average gap between requests
system.physmem.pageHitRate                      80.85                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     49290195125250                       # Time in different power states
system.physmem.memoryStateTime::REF      1721605340000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      545313634750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                3951453240                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                3871929600                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                2156050875                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                2112660000                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               8412588600                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               8431020000                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0             10640075760                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1             10381277520                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          3367460045040                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          3367460045040                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          1383947967870                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          1368871606665                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          29720278968750                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          29733503847000                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            34496847150135                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            34494632385825                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.099654                       # Core power per rank (mW)
system.physmem.averagePower::1             669.056696                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           436                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          400                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          400                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           25                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq              657217                       # Transaction distribution
system.membus.trans_dist::ReadResp             657217                       # Transaction distribution
system.membus.trans_dist::WriteReq              33865                       # Transaction distribution
system.membus.trans_dist::WriteResp             33865                       # Transaction distribution
system.membus.trans_dist::Writeback           1596567                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq      1712339                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp      1712339                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            48473                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           48476                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1541174                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1541174                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      9221519                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      9351669                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       229018                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       229018                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                9580687                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13800                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    341910604                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    342081160                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7264064                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7264064                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               349345224                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2022                       # Total snoops (count)
system.membus.snoop_fanout::samples           5500895                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 5500895    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             5500895                       # Request fanout histogram
system.membus.reqLayer0.occupancy           109641999                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               42500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5450500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         32462148974                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy        21571101815                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          186532342                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                40379                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40379                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136716                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136733                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq           17                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354224                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492654                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           981079506                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           179002658                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               291488483                       # Number of BP lookups
system.cpu.branchPred.condPredicted         200150149                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          13608043                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            209143322                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               138326751                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             66.139693                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                37688944                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             403819                       # Number of incorrect RAS predictions.
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.dtb.read_hits            206311750                       # DTB read hits
system.cpu.checker.dtb.read_misses             258027                       # DTB read misses
system.cpu.checker.dtb.write_hits           190103200                       # DTB write hits
system.cpu.checker.dtb.write_misses             94684                       # DTB write misses
system.cpu.checker.dtb.flush_tlb                   22                       # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid       127936                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid            2418                       # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries            89489                       # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults          10233                       # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults             24751                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses        206569777                       # DTB read accesses
system.cpu.checker.dtb.write_accesses       190197884                       # DTB write accesses
system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.dtb.hits                 396414950                       # DTB hits
system.cpu.checker.dtb.misses                  352711                       # DTB misses
system.cpu.checker.dtb.accesses             396767661                       # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.checker.itb.inst_hits           1114925280                       # ITB inst hits
system.cpu.checker.itb.inst_misses             131008                       # ITB inst misses
system.cpu.checker.itb.read_hits                    0                       # DTB read hits
system.cpu.checker.itb.read_misses                  0                       # DTB read misses
system.cpu.checker.itb.write_hits                   0                       # DTB write hits
system.cpu.checker.itb.write_misses                 0                       # DTB write misses
system.cpu.checker.itb.flush_tlb                   22                       # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid       127936                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid            2418                       # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries            61860                       # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
system.cpu.checker.itb.inst_accesses       1115056288                       # ITB inst accesses
system.cpu.checker.itb.hits                1114925280                       # DTB hits
system.cpu.checker.itb.misses                  131008                       # DTB misses
system.cpu.checker.itb.accesses            1115056288                       # DTB accesses
system.cpu.checker.numCycles               1310563748                       # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    220000246                       # DTB read hits
system.cpu.dtb.read_misses                    1007031                       # DTB read misses
system.cpu.dtb.write_hits                   193886106                       # DTB write hits
system.cpu.dtb.write_misses                    416122                       # DTB write misses
system.cpu.dtb.flush_tlb                           22                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid              127936                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    2418                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    89690                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       112                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  15179                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     87251                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                221007277                       # DTB read accesses
system.cpu.dtb.write_accesses               194302228                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         413886352                       # DTB hits
system.cpu.dtb.misses                         1423153                       # DTB misses
system.cpu.dtb.accesses                     415309505                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                    465588468                       # ITB inst hits
system.cpu.itb.inst_misses                     176797                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           22                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid              127936                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    2418                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    63536                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    462381                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                465765265                       # ITB inst accesses
system.cpu.itb.hits                         465588468                       # DTB hits
system.cpu.itb.misses                          176797                       # DTB misses
system.cpu.itb.accesses                     465765265                       # DTB accesses
system.cpu.numCycles                       2146849645                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          791511347                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1301628389                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   291488483                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          176015695                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                    1268750537                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                29307286                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                    4254748                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                27926                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles      12217982                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles      1219824                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          381                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 465107423                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               6746831                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                   53918                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples         2092636388                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.729302                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.142136                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0               1367675983     65.36%     65.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                280886167     13.42%     78.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 86945610      4.15%     82.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                357128628     17.07%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           2092636388                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.135775                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.606297                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                614820490                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             852644163                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 531180111                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              83391963                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               10599661                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             41490545                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred               4112846                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1415541998                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              32718079                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               10599661                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                678805488                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                83662136                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles      556428904                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 549849830                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             213290369                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1391734034                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               7977079                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               7435136                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 893230                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1023922                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents              127479585                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents            25199                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          1342075875                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            2217645602                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1652184740                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           1639045                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1263873564                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 78202308                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts           44203192                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts       39719264                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 172796539                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            223511224                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           198396121                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          12647992                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         11061331                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1338396177                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded            44508712                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1370133902                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           4153047                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        65240654                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     41320787                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         373617                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    2092636388                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.654741                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.915536                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0          1237717942     59.15%     59.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           455529583     21.77%     80.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           292996726     14.00%     94.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            96986296      4.63%     99.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             9377226      0.45%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5               28615      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      2092636388                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                74528454     34.28%     34.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  90672      0.04%     34.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                   26772      0.01%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc              287      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.34% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               58830485     27.06%     61.40% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              83911289     38.60%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 1      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             945793660     69.03%     69.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2946266      0.22%     69.24% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                129775      0.01%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   1      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         114397      0.01%     69.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.26% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            224851656     16.41%     85.67% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           196298100     14.33%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1370133902                       # Type of FU issued
system.cpu.iq.rate                           0.638207                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   217387959                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.158662                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         5052021388                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1447405501                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1347303683                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             2423809                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             923681                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       885699                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1585997449                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 1524411                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          5766333                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     16996131                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        24128                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       185382                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      8259714                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      3623609                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       3385962                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               10599661                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                11961718                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               7304667                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1383179145                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             223511224                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            198396121                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts           39177517                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 185228                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               6936317                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         185382                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4274350                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      5730421                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             10004771                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1356817685                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             220004444                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          11924579                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        274256                       # number of nop insts executed
system.cpu.iew.exec_refs                    413901554                       # number of memory reference insts executed
system.cpu.iew.exec_branches                257473473                       # Number of branches executed
system.cpu.iew.exec_stores                  193897110                       # Number of stores executed
system.cpu.iew.exec_rate                     0.632004                       # Inst execution rate
system.cpu.iew.wb_sent                     1349182874                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1348189382                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 579023420                       # num instructions producing a value
system.cpu.iew.wb_consumers                 949767765                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.627985                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.609647                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        62443917                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls        44135095                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           9554061                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   2078483160                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.630193                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.269789                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0   1396354428     67.18%     67.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    397736022     19.14%     86.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    152396085      7.33%     93.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     44287772      2.13%     95.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     35996912      1.73%     97.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     18656723      0.90%     98.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     10905184      0.52%     98.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      5449343      0.26%     99.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     16700691      0.80%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   2078483160                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1114380469                       # Number of instructions committed
system.cpu.commit.committedOps             1309844804                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      396651499                       # Number of memory references committed
system.cpu.commit.loads                     206515092                       # Number of loads committed
system.cpu.commit.membars                     9189565                       # Number of memory barriers committed
system.cpu.commit.branches                  249089949                       # Number of branches committed
system.cpu.commit.fp_insts                     873640                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1196978104                       # Number of committed integer instructions.
system.cpu.commit.function_calls             31078874                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        910428363     69.51%     69.51% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         2554988      0.20%     69.70% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           104143      0.01%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       105769      0.01%     69.72% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.72% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.72% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.72% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       206515092     15.77%     85.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      190136407     14.52%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1309844804                       # Class of committed instruction
system.cpu.commit.bw_lim_events              16700691                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   3424556806                       # The number of ROB reads
system.cpu.rob.rob_writes                  2758622493                       # The number of ROB writes
system.cpu.timesIdled                         9031521                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        54213257                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                 100967380384                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                  1114380469                       # Number of Instructions Simulated
system.cpu.committedOps                    1309844804                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.926496                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.926496                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.519077                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.519077                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1611998606                       # number of integer regfile reads
system.cpu.int_regfile_writes               948639329                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   1420015                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   765124                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 315259155                       # number of cc regfile reads
system.cpu.cc_regfile_writes                316098925                       # number of cc regfile writes
system.cpu.misc_regfile_reads              6952427793                       # number of misc regfile reads
system.cpu.misc_regfile_writes               45059384                       # number of misc regfile writes
system.cpu.toL2Bus.trans_dist::ReadReq       28539920                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      28531649                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33865                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33865                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      9369509                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1712344                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1605675                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        61529                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            6                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        61535                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      3074731                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      3074731                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     33703094                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     37825776                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       810571                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3115869                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          75455310                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1077469744                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1502191576                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2724416                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side     10868120                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2593253856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      644632                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     42703026                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        9.002705                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.051942                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::9           42587504     99.73%     99.73% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::10            115522      0.27%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value           10                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       42703026                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    32333793873                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       871500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   25296093441                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   19876823538                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     472614279                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1760067316                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements          16829629                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.959617                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           447510611                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          16830141                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             26.589831                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       12236526000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.959617                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999921                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999921                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          291                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         481916487                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        481916487                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    447510611                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       447510611                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     447510611                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        447510611                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    447510611                       # number of overall hits
system.cpu.icache.overall_hits::total       447510611                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     17575514                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      17575514                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     17575514                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       17575514                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     17575514                       # number of overall misses
system.cpu.icache.overall_misses::total      17575514                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 231527181766                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 231527181766                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 231527181766                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 231527181766                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 231527181766                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 231527181766                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    465086125                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    465086125                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    465086125                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    465086125                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    465086125                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    465086125                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.037790                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.037790                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.037790                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.037790                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.037790                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.037790                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13173.280836                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13173.280836                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13173.280836                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13173.280836                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13173.280836                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13173.280836                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        11084                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               920                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    12.047826                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst       745151                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total       745151                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst       745151                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total       745151                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst       745151                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total       745151                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     16830363                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     16830363                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     16830363                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     16830363                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     16830363                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     16830363                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191394786019                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 191394786019                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191394786019                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 191394786019                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191394786019                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 191394786019                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1413030250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   1413030250                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.036188                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.036188                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.036188                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.036188                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.036188                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.036188                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.993939                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.993939                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.993939                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.993939                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.993939                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.993939                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1866229                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64521.528187                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           35312731                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1928499                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            18.310993                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     13813873928000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 34323.724648                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   307.320059                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   449.834309                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  7078.453286                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 22362.195885                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.523738                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004689                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006864                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.108009                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.341220                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.984520                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          496                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        61774                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          485                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2102                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5030                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54369                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.007568                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.942596                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        341864435                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       341864435                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker      1342854                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       321211                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst     16739434                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      8950656                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total       27354155                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      9369509                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      9369509                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        13684                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        13684                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1532929                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1532929                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker      1342854                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       321211                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     16739434                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data     10483585                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        28887084                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker      1342854                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       321211                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     16739434                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data     10483585                       # number of overall hits
system.cpu.l2cache.overall_hits::total       28887084                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker        15661                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker        19341                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        90708                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       467610                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       593320                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        47842                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        47842                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data      1541802                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total      1541802                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker        15661                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker        19341                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        90708                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      2009412                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       2135122                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker        15661                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker        19341                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        90708                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      2009412                       # number of overall misses
system.cpu.l2cache.overall_misses::total      2135122                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker   1242745748                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker   1521537709                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   6968907733                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  38087084418                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  47820275608                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    470429308                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    470429308                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        46998                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        46998                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128470228063                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 128470228063                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker   1242745748                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker   1521537709                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   6968907733                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 166557312481                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 176290503671                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker   1242745748                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker   1521537709                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   6968907733                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 166557312481                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 176290503671                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker      1358515                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       340552                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst     16830142                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      9418266                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total     27947475                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      9369509                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      9369509                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        61526                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        61526                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            6                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            6                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      3074731                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      3074731                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker      1358515                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       340552                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     16830142                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data     12492997                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     31022206                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker      1358515                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       340552                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     16830142                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data     12492997                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     31022206                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.011528                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.056793                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005390                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.049649                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021230                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.777590                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.777590                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.501443                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.501443                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.011528                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.056793                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005390                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.160843                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.068826                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.011528                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.056793                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005390                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.160843                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.068826                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79352.898793                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78669.029988                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76827.928441                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81450.534458                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80597.781312                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  9832.977467                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  9832.977467                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        15666                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        15666                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83324.725265                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83324.725265                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79352.898793                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78669.029988                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76827.928441                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82888.582571                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82566.946372                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79352.898793                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78669.029988                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76827.928441                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82888.582571                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82566.946372                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1596567                       # number of writebacks
system.cpu.l2cache.writebacks::total          1596567                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           20                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           21                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           20                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           20                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker        15661                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker        19340                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        90708                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       467590                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       593299                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        47842                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        47842                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data      1541802                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total      1541802                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker        15661                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker        19340                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        90708                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      2009392                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      2135101                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker        15661                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker        19340                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        90708                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      2009392                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      2135101                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1047833748                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker   1280582209                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   5831343267                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  32265741244                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  40425500468                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  38940123401                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  38940123401                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    478734836                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    478734836                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 109487402329                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 109487402329                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker   1047833748                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker   1280582209                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5831343267                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 141753143573                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 149912902797                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker   1047833748                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker   1280582209                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5831343267                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 141753143573                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 149912902797                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289773250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393755500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176184000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176184000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465957250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569939500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.011528                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.056790                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005390                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.049647                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021229                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.777590                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.777590                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.501443                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.501443                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.011528                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.056790                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005390                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.160841                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.068825                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.011528                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.056790                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005390                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.160841                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.068825                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66214.178335                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64286.978734                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69004.344071                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68136.808705                       # average ReadReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10006.580745                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10006.580745                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71012.621808                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71012.621808                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66214.178335                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64286.978734                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70545.291099                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70213.494723                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66214.178335                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64286.978734                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70545.291099                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70213.494723                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements          13756884                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.985330                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           363427258                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          13757396                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             26.416864                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1485814250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.985330                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999971                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999971                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          382                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1609448196                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1609448196                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    188132338                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       188132338                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    164232223                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      164232223                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       465761                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        465761                       # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data      1605675                       # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total      1605675                       # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      4847947                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      4847947                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      5335203                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      5335203                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     352364561                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        352364561                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    352830322                       # number of overall hits
system.cpu.dcache.overall_hits::total       352830322                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data     12712279                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total      12712279                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data     18968725                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total     18968725                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      2072118                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      2072118                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       550419                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       550419                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            6                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            6                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     31681004                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       31681004                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     33753122                       # number of overall misses
system.cpu.dcache.overall_misses::total      33753122                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 203403538452                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 203403538452                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1021678237791                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1021678237791                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   8626183252                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   8626183252                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       117003                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       117003                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 1225081776243                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 1225081776243                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 1225081776243                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 1225081776243                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    200844617                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    200844617                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    183200948                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    183200948                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      2537879                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      2537879                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1605675                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total      1605675                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      5398366                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      5398366                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      5335209                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      5335209                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    384045565                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    384045565                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    386583444                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    386583444                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.063294                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.063294                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.103541                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.103541                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.816476                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.816476                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.101960                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.101960                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.082493                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.082493                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.087311                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.087311                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16000.556505                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16000.556505                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53861.197196                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53861.197196                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15672.030311                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15672.030311                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38669.285110                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38669.285110                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36295.361841                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36295.361841                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     38319499                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs           2284719                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    16.772084                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                 1605675                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      9369509                       # number of writebacks
system.cpu.dcache.writebacks::total           9369509                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5628309                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      5628309                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data     15829986                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total     15829986                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       265840                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total       265840                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data     21458295                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total     21458295                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data     21458295                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total     21458295                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7083970                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7083970                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      3120649                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      3120649                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      2065320                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      2065320                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       284579                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       284579                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            6                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data     10204619                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total     10204619                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data     12269939                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total     12269939                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102477717871                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 102477717871                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148263766896                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 148263766896                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  31611668497                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  31611668497                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  59007365277                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  59007365277                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3751055249                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3751055249                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       104997                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       104997                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250741484767                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 250741484767                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 282353153264                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 282353153264                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729434750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729434750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587276983                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587276983                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316711733                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316711733                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035271                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035271                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.017034                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.017034                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.813798                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.813798                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.052716                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.052716                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026571                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.026571                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031739                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.031739                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.142272                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.142272                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13181.068347                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13181.068347                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24571.371530                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24571.371530                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23011.781335                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23011.781335                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.tags.replacements               115458                       # number of replacements
system.iocache.tags.tagsinuse               10.450727                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13090278324000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.528058                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.922669                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.220504                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.432667                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653170                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039786                       # Number of tag accesses
system.iocache.tags.data_accesses             1039786                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide       106664                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide           17                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total           17                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
system.iocache.overall_misses::total             8853                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5547000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1929395843                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1934942843                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5886000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1929395843                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1935281843                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5886000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1929395843                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1935281843                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106681                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106681                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000159                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.000159                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149918.918919                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 218926.114036                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 218637.609379                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       147150                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 218926.114036                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 218601.812154                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       147150                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 218926.114036                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 218601.812154                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         53350                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.717668                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                     106664                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8853                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3623000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1470987863                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1474610863                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6546677301                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6546677301                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3806000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1470987863                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1474793863                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3806000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1470987863                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1474793863                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97918.918919                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        95150                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 166586.904213                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        95150                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 166586.904213                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    17164                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------