path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.320621                       # Number of seconds simulated
sim_ticks                                51320620981500                       # Number of ticks simulated
final_tick                               51320620981500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  75246                       # Simulator instruction rate (inst/s)
host_op_rate                                    88415                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4505389037                       # Simulator tick rate (ticks/s)
host_mem_usage                                 667676                       # Number of bytes of host memory used
host_seconds                                 11390.94                       # Real time elapsed on the host
sim_insts                                   857117694                       # Number of instructions simulated
sim_ops                                    1007133124                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       227264                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       206272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           5756576                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          43073416                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        400256                       # Number of bytes read from this memory
system.physmem.bytes_read::total             49663784                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      5756576                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5756576                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     69780544                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          69801124                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         3551                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         3223                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             105899                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             673035                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6254                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                791962                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1090321                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1092894                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           4428                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           4019                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               112169                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               839300                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7799                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                  967716                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          112169                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             112169                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1359698                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1360099                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1359698                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          4428                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          4019                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              112169                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              839701                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7799                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2327815                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        791962                       # Number of read requests accepted
system.physmem.writeReqs                      1696531                       # Number of write requests accepted
system.physmem.readBursts                      791962                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1696531                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 50649920                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     35648                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 108090368                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  49663784                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              108433892                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      557                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    7601                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          35291                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               50546                       # Per bank write bursts
system.physmem.perBankRdBursts::1               51810                       # Per bank write bursts
system.physmem.perBankRdBursts::2               46789                       # Per bank write bursts
system.physmem.perBankRdBursts::3               46242                       # Per bank write bursts
system.physmem.perBankRdBursts::4               46096                       # Per bank write bursts
system.physmem.perBankRdBursts::5               52242                       # Per bank write bursts
system.physmem.perBankRdBursts::6               46925                       # Per bank write bursts
system.physmem.perBankRdBursts::7               49452                       # Per bank write bursts
system.physmem.perBankRdBursts::8               44750                       # Per bank write bursts
system.physmem.perBankRdBursts::9               73148                       # Per bank write bursts
system.physmem.perBankRdBursts::10              48402                       # Per bank write bursts
system.physmem.perBankRdBursts::11              51457                       # Per bank write bursts
system.physmem.perBankRdBursts::12              45806                       # Per bank write bursts
system.physmem.perBankRdBursts::13              48601                       # Per bank write bursts
system.physmem.perBankRdBursts::14              42635                       # Per bank write bursts
system.physmem.perBankRdBursts::15              46504                       # Per bank write bursts
system.physmem.perBankWrBursts::0              106325                       # Per bank write bursts
system.physmem.perBankWrBursts::1              106592                       # Per bank write bursts
system.physmem.perBankWrBursts::2              106293                       # Per bank write bursts
system.physmem.perBankWrBursts::3              105191                       # Per bank write bursts
system.physmem.perBankWrBursts::4              106687                       # Per bank write bursts
system.physmem.perBankWrBursts::5              109171                       # Per bank write bursts
system.physmem.perBankWrBursts::6              103226                       # Per bank write bursts
system.physmem.perBankWrBursts::7              105745                       # Per bank write bursts
system.physmem.perBankWrBursts::8              103090                       # Per bank write bursts
system.physmem.perBankWrBursts::9              109771                       # Per bank write bursts
system.physmem.perBankWrBursts::10             107182                       # Per bank write bursts
system.physmem.perBankWrBursts::11             108709                       # Per bank write bursts
system.physmem.perBankWrBursts::12             102154                       # Per bank write bursts
system.physmem.perBankWrBursts::13             106063                       # Per bank write bursts
system.physmem.perBankWrBursts::14             100653                       # Per bank write bursts
system.physmem.perBankWrBursts::15             102060                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          63                       # Number of times write queue was full causing retry
system.physmem.totGap                    51320619748500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  770677                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1693958                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    524690                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    218670                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     33629                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     11094                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       783                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       426                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       389                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       320                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       222                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       146                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      143                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      129                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      115                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      108                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       94                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       76                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       56                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    66510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    80685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    95220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    95674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   107871                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   105650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   115186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   109604                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   123316                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   110089                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    98131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    89808                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    90193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    76388                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    75197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    74826                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    71320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     5232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     4640                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     4117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     3862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     3608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     3366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     3244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     3200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     3037                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     2834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     2761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     2689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     2623                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     2429                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     2386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     2389                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     2289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     2041                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1971                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     1782                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     1297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                     1152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      990                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      767                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      573                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      151                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       519847                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      305.358892                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     172.693203                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     342.458813                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         210597     40.51%     40.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       125304     24.10%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        44434      8.55%     73.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        23828      4.58%     77.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        16026      3.08%     80.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        10297      1.98%     82.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8038      1.55%     84.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         7736      1.49%     85.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        73587     14.16%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         519847                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         65806                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        12.026092                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       69.420005                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           65801     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            3      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           65806                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         65806                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        25.665015                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       22.295407                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       18.784846                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23           44130     67.06%     67.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31            6726     10.22%     77.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39            8110     12.32%     89.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47            2086      3.17%     92.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55            1158      1.76%     94.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63             536      0.81%     95.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71             588      0.89%     96.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79             530      0.81%     97.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             479      0.73%     97.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95             220      0.33%     98.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103            383      0.58%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111           149      0.23%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119           276      0.42%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127            79      0.12%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135           128      0.19%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143            41      0.06%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            35      0.05%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159            20      0.03%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167            44      0.07%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175            20      0.03%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183            23      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191            10      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             5      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             3      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215            10      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             5      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           65806                       # Writes before turning the bus around for reads
system.physmem.totQLat                    15790981009                       # Total ticks spent queuing
system.physmem.totMemAccLat               30629824759                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   3957025000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       19953.10                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  38703.10                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.99                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.11                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.97                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.11                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.05                       # Average write queue length when enqueuing
system.physmem.readRowHits                     603831                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1356638                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.30                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.33                       # Row buffer hit rate for writes
system.physmem.avgGap                     20623172.24                       # Average gap between requests
system.physmem.pageHitRate                      79.04                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     49368372569000                       # Time in different power states
system.physmem.memoryStateTime::REF      1713708100000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      238539960500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                1984348800                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                1945694520                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                1082730000                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                1061638875                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               3042748800                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               3130163400                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0              5503010400                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1              5441139360                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          3352013043600                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          3352013043600                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          1228384903950                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          1226638074825                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          29714838054000                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          29716370360250                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            34306848839550                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            34306600114830                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.480867                       # Core power per rank (mW)
system.physmem.averagePower::1             668.476020                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           436                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          400                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          400                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           25                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               226428976                       # Number of BP lookups
system.cpu.branchPred.condPredicted         151471445                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12246087                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            159886473                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               104578062                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             65.407698                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                31061917                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             345275                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.dtb.read_hits            161215407                       # DTB read hits
system.cpu.checker.dtb.read_misses             149229                       # DTB read misses
system.cpu.checker.dtb.write_hits           146260364                       # DTB write hits
system.cpu.checker.dtb.write_misses             51460                       # DTB write misses
system.cpu.checker.dtb.flush_tlb                   20                       # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid        80016                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid            2058                       # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries            72721                       # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults           7177                       # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults             19208                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses        161364636                       # DTB read accesses
system.cpu.checker.dtb.write_accesses       146311824                       # DTB write accesses
system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.dtb.hits                 307475771                       # DTB hits
system.cpu.checker.dtb.misses                  200689                       # DTB misses
system.cpu.checker.dtb.accesses             307676460                       # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.checker.itb.inst_hits            857529218                       # ITB inst hits
system.cpu.checker.itb.inst_misses             120798                       # ITB inst misses
system.cpu.checker.itb.read_hits                    0                       # DTB read hits
system.cpu.checker.itb.read_misses                  0                       # DTB read misses
system.cpu.checker.itb.write_hits                   0                       # DTB write hits
system.cpu.checker.itb.write_misses                 0                       # DTB write misses
system.cpu.checker.itb.flush_tlb                   20                       # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid        80016                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid            2058                       # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries            52233                       # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
system.cpu.checker.itb.inst_accesses        857650016                       # ITB inst accesses
system.cpu.checker.itb.hits                 857529218                       # DTB hits
system.cpu.checker.itb.misses                  120798                       # DTB misses
system.cpu.checker.itb.accesses             857650016                       # DTB accesses
system.cpu.checker.numCycles               1007708571                       # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    171196432                       # DTB read hits
system.cpu.dtb.read_misses                     671544                       # DTB read misses
system.cpu.dtb.write_hits                   149025904                       # DTB write hits
system.cpu.dtb.write_misses                    258759                       # DTB write misses
system.cpu.dtb.flush_tlb                           20                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               80016                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    2058                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    72979                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       104                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  10362                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     68614                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                171867976                       # DTB read accesses
system.cpu.dtb.write_accesses               149284663                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         320222336                       # DTB hits
system.cpu.dtb.misses                          930303                       # DTB misses
system.cpu.dtb.accesses                     321152639                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                    360051885                       # ITB inst hits
system.cpu.itb.inst_misses                     161655                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           20                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               80016                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    2058                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    53701                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    372863                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                360213540                       # ITB inst accesses
system.cpu.itb.hits                         360051885                       # DTB hits
system.cpu.itb.misses                          161655                       # DTB misses
system.cpu.itb.accesses                     360213540                       # DTB accesses
system.cpu.numCycles                       1576874693                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          648679854                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1010290403                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   226428976                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          135639979                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     852655064                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                26160452                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                    3389644                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                26807                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles       9240220                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles      1021673                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          362                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 359662567                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               6136086                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                   47510                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples         1528093850                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.774691                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.161324                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                965958627     63.21%     63.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                215893777     14.13%     77.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 70817340      4.63%     81.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                275424106     18.02%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1528093850                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.143594                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.640692                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                527180052                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             504302107                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 436284853                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              51059674                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                9267164                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             33905862                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred               3872221                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1095429909                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              29099398                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                9267164                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                572442291                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                46180186                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles      363186865                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 441948285                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              95069059                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1075584704                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               6788495                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               4945824                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 318864                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 589123                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               42956715                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents            21763                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          1023437611                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1659121727                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1272319582                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           1685396                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             957674620                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 65762988                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts           27435128                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts       23745394                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 104747763                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            175168030                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           152601618                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           9963388                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          9061948                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1040022976                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded            27737741                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1056135120                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           3300763                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        53598061                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33623556                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         314928                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1528093850                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.691145                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.927830                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           873977548     57.19%     57.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           338098484     22.13%     79.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           236626258     15.49%     94.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            72801252      4.76%     99.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6571176      0.43%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5               19132      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1528093850                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                58371154     35.14%     35.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                 100885      0.06%     35.20% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                   26756      0.02%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc              767      0.00%     35.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.22% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               44544414     26.81%     62.03% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              63075062     37.97%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 2      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             727332382     68.87%     68.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2546997      0.24%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                123061      0.01%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   4      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         120668      0.01%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            175096796     16.58%     85.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           150915164     14.29%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1056135120                       # Type of FU issued
system.cpu.iq.rate                           0.669765                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   166119038                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.157290                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         3807304115                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1120557954                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1038099529                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             2479775                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             941816                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       907592                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1220693938                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 1560218                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          4348848                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     13855252                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14404                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       142361                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      6337064                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2552747                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1859122                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                9267164                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 6379535                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               3965873                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1067985048                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             175168030                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            152601618                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts           23314125                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  62024                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               3832996                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         142361                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3691152                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      5135953                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8827105                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1044930592                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             171186057                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10287379                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        224331                       # number of nop insts executed
system.cpu.iew.exec_refs                    320208959                       # number of memory reference insts executed
system.cpu.iew.exec_branches                198322451                       # Number of branches executed
system.cpu.iew.exec_stores                  149022902                       # Number of stores executed
system.cpu.iew.exec_rate                     0.662659                       # Inst execution rate
system.cpu.iew.wb_sent                     1039793819                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1039007121                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 442154878                       # num instructions producing a value
system.cpu.iew.wb_consumers                 715627882                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.658903                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.617856                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        51471265                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls        27422813                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           8433025                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1516084212                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.664299                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.291990                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    998537580     65.86%     65.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    291350566     19.22%     85.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    121957393      8.04%     93.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     36696853      2.42%     95.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     28610485      1.89%     97.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     14255849      0.94%     98.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      8557612      0.56%     98.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      4232636      0.28%     99.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     11885238      0.78%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1516084212                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            857117694                       # Number of instructions committed
system.cpu.commit.committedOps             1007133124                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      307577331                       # Number of memory references committed
system.cpu.commit.loads                     161312777                       # Number of loads committed
system.cpu.commit.membars                     7014752                       # Number of memory barriers committed
system.cpu.commit.branches                  191334741                       # Number of branches committed
system.cpu.commit.fp_insts                     896026                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 925144388                       # Number of committed integer instructions.
system.cpu.commit.function_calls             25493443                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        697181314     69.22%     69.22% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         2164633      0.21%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv            98281      0.01%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       111523      0.01%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       161312777     16.02%     85.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      146264554     14.52%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1007133124                       # Class of committed instruction
system.cpu.commit.bw_lim_events              11885238                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   2555181565                       # The number of ROB reads
system.cpu.rob.rob_writes                  2129123637                       # The number of ROB writes
system.cpu.timesIdled                         8137810                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        48780843                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                 101064367400                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   857117694                       # Number of Instructions Simulated
system.cpu.committedOps                    1007133124                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.839741                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.839741                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.543555                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.543555                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1237020079                       # number of integer regfile reads
system.cpu.int_regfile_writes               738429838                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   1457787                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   782552                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 228125574                       # number of cc regfile reads
system.cpu.cc_regfile_writes                228731881                       # number of cc regfile writes
system.cpu.misc_regfile_reads              5247037954                       # number of misc regfile reads
system.cpu.misc_regfile_writes               27486572                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           9822538                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.985265                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           286045243                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9823050                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.119799                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1485814250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.985265                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999971                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999971                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1249214859                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1249214859                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    148712432                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       148712432                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    129479125                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      129479125                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       381594                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        381594                       # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       324870                       # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total       324870                       # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3352883                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3352883                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      3750315                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      3750315                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     278191557                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        278191557                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    278573151                       # number of overall hits
system.cpu.dcache.overall_hits::total       278573151                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      9502058                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       9502058                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data     11465174                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total     11465174                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1197022                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1197022                       # number of SoftPFReq misses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1233022                       # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total      1233022                       # number of WriteInvalidateReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       449448                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       449448                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     20967232                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       20967232                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     22164254                       # number of overall misses
system.cpu.dcache.overall_misses::total      22164254                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 140935225401                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 140935225401                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 322991667568                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 322991667568                       # number of WriteReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  38675981880                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::total  38675981880                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6315194753                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   6315194753                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       139001                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       139001                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 463926892969                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 463926892969                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 463926892969                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 463926892969                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    158214490                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    158214490                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    140944299                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    140944299                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1578616                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1578616                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1557892                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total      1557892                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3802331                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      3802331                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      3750320                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      3750320                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    299158789                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    299158789                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    300737405                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    300737405                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060058                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.060058                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081345                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.081345                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758273                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.758273                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.791468                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.791468                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.118203                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.118203                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.070087                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.070087                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.073700                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.073700                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14832.073789                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14832.073789                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28171.545200                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28171.545200                       # average WriteReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31366.822230                       # average WriteInvalidateReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31366.822230                       # average WriteInvalidateReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14051.002014                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14051.002014                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22126.282237                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22126.282237                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20931.310973                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20931.310973                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     21466802                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs           1401851                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.313184                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      7593763                       # number of writebacks
system.cpu.dcache.writebacks::total           7593763                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4321399                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      4321399                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9425025                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      9425025                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data         7055                       # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::total         7055                       # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219414                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total       219414                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data     13746424                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total     13746424                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data     13746424                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total     13746424                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5180659                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5180659                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2040149                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2040149                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1190231                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1190231                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1225967                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1225967                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230034                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       230034                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      7220808                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      7220808                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      8411039                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      8411039                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  70208074682                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  70208074682                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53752252884                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  53752252884                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  18853760746                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  18853760746                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  35977742828                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  35977742828                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2809792248                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2809792248                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       128999                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       128999                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123960327566                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 123960327566                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142814088312                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 142814088312                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729213249                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729213249                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587099983                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587099983                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316313232                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316313232                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032745                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032745                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014475                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014475                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.753971                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.753971                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.786940                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786940                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060498                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060498                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024137                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024137                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027968                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.027968                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13551.958290                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13551.958290                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26347.219190                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26347.219190                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15840.421520                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15840.421520                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29346.420277                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29346.420277                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12214.682386                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12214.682386                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17167.099245                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17167.099245                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16979.363467                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16979.363467                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          15082585                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.954216                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           343840613                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          15083097                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             22.796420                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       14175734000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.954216                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999911                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999911                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           92                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         374724467                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        374724467                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    343840613                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       343840613                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     343840613                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        343840613                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    343840613                       # number of overall hits
system.cpu.icache.overall_hits::total       343840613                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     15800655                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      15800655                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     15800655                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       15800655                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     15800655                       # number of overall misses
system.cpu.icache.overall_misses::total      15800655                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 208208668907                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 208208668907                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 208208668907                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 208208668907                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 208208668907                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 208208668907                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    359641268                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    359641268                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    359641268                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    359641268                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    359641268                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    359641268                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043934                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.043934                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.043934                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.043934                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.043934                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.043934                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13177.217584                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13177.217584                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13177.217584                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13177.217584                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13177.217584                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13177.217584                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        10839                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               972                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    11.151235                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst       717456                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total       717456                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst       717456                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total       717456                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst       717456                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total       717456                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15083199                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     15083199                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     15083199                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     15083199                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     15083199                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     15083199                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171815580989                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 171815580989                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171815580989                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 171815580989                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171815580989                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 171815580989                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1413030250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   1413030250                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041940                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.041940                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.041940                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11391.189693                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11391.189693                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11391.189693                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1167362                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65297.852107                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           29065274                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1230222                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            23.626040                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       2430272000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37323.559826                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   320.853018                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   490.286692                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  7518.567341                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19644.585230                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.569512                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004896                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007481                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.114724                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.299753                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996366                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          285                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        62575                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          285                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          565                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2655                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5044                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54243                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004349                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954819                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        273181992                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       273181992                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       797530                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       297299                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst     14998467                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      6339712                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total       22433008                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      7593763                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      7593763                       # number of Writeback hits
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       728839                       # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total       728839                       # number of WriteInvalidateReq hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         9472                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         9472                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1583067                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1583067                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       797530                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       297299                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     14998467                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7922779                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        24016075                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       797530                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       297299                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     14998467                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7922779                       # number of overall hits
system.cpu.l2cache.overall_hits::total       24016075                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3551                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3223                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        84643                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       257522                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       348939                       # number of ReadReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       497128                       # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total       497128                       # number of WriteInvalidateReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        34502                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        34502                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       416799                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       416799                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         3551                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         3223                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        84643                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       674321                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        765738                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         3551                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         3223                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        84643                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       674321                       # number of overall misses
system.cpu.l2cache.overall_misses::total       765738                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    283709749                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    260562999                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   6536550232                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  21467939178                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  28548762158                       # number of ReadReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data      3612846                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::total      3612846                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    412251300                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    412251300                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        72000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        72000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  34736796105                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  34736796105                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    283709749                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    260562999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   6536550232                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  56204735283                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  63285558263                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    283709749                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    260562999                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   6536550232                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  56204735283                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  63285558263                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       801081                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       300522                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst     15083110                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      6597234                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total     22781947                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      7593763                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      7593763                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1225967                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total      1225967                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43974                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        43974                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1999866                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1999866                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       801081                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       300522                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     15083110                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      8597100                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     24781813                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       801081                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       300522                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     15083110                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      8597100                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     24781813                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004433                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010725                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005612                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.039035                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.015316                       # miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.405499                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.405499                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.784600                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.784600                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.208413                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.208413                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004433                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.010725                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005612                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.078436                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.030899                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004433                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.010725                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005612                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.078436                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.030899                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79895.733315                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80844.864722                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77224.935695                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83363.515265                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81815.910970                       # average ReadReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data     7.267436                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     7.267436                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11948.620370                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11948.620370                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        36000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        36000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83341.841283                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83341.841283                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79895.733315                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80844.864722                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77224.935695                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83350.118539                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82646.490396                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79895.733315                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80844.864722                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77224.935695                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83350.118539                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82646.490396                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       983690                       # number of writebacks
system.cpu.l2cache.writebacks::total           983690                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           21                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3551                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3223                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        84643                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       257501                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       348918                       # number of ReadReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data       497128                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       497128                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34502                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        34502                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       416799                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       416799                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3551                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3223                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        84643                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       674300                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       765717                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3551                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3223                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        84643                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       674300                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       765717                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    220243499                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   5475082762                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  18259324004                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24194010014                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  19601424690                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  19601424690                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    345545498                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    345545498                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70001                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70001                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  29577738885                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  29577738885                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    220243499                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5475082762                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  47837062889                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  53771748899                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    220243499                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5475082762                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  47837062889                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  53771748899                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289733251                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393715501                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176071500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176071500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465804751                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569787001                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.039032                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015316                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.405499                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.405499                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784600                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784600                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.208413                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.208413                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.078433                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.030898                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.078433                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.030898                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70909.720754                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69340.102872                       # average ReadReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39429.331460                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39429.331460                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10015.230943                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.230943                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70964.035146                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70964.035146                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70943.293622                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70224.050007                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70943.293622                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70224.050007                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq       23341232                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      23333163                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33858                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33858                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      7593763                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1332631                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1225967                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        43977                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        43982                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1999866                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1999866                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     30208899                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27463876                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       731462                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1967033                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          60371270                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    965659760                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1114918084                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2404176                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6408648                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2089390668                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      611685                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     34508223                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        9.003348                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.057762                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::9           34392703     99.67%     99.67% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::10            115520      0.33%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value           10                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       34508223                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    26206492236                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1177500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   22671590732                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13674088224                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     431886005                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1166711358                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40382                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40382                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230960                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230960                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354230                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492678                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy          1042360658                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           179004169                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115462                       # number of replacements
system.iocache.tags.tagsinuse               10.424613                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115478                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13092189065000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.544618                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.879995                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221539                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.430000                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651538                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039677                       # Number of tag accesses
system.iocache.tags.data_accesses             1039677                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8816                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8853                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8816                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8856                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8816                       # number of overall misses
system.iocache.overall_misses::total             8856                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5527000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1927411613                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1932938613                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28910124876                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  28910124876                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5866000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1927411613                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1933277613                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5866000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1927411613                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1933277613                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8816                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8853                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8816                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8856                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8816                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8856                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 218626.544124                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 218337.130125                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271039.196692                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 271039.196692                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 218626.544124                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 218301.446816                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 218626.544124                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 218301.446816                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        226675                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27646                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.199197                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8816                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8853                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8816                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8856                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8816                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8856                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3603000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1468863623                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1472466623                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23363269204                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23363269204                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3786000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1468863623                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1472649623                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3786000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1468863623                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1472649623                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166613.387364                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 166324.028352                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219036.124691                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219036.124691                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 166613.387364                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 166288.349481                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 166613.387364                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 166288.349481                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              412825                       # Transaction distribution
system.membus.trans_dist::ReadResp             412825                       # Transaction distribution
system.membus.trans_dist::WriteReq              33858                       # Transaction distribution
system.membus.trans_dist::WriteResp             33858                       # Transaction distribution
system.membus.trans_dist::Writeback           1090321                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       603637                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       603637                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            35296                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           35298                       # Transaction distribution
system.membus.trans_dist::ReadExReq            416163                       # Transaction distribution
system.membus.trans_dist::ReadExResp           416163                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3625442                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3755550                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335069                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       335069                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4090619                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    144046540                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    144217012                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14051136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14051136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               158268148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3264                       # Total snoops (count)
system.membus.snoop_fanout::samples           2503253                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2503253    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2503253                       # Request fanout histogram
system.membus.reqLayer0.occupancy           109702500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               42500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5437999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         16337638979                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7836649146                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          186565831                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16179                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------