path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.320647                       # Number of seconds simulated
sim_ticks                                51320647066500                       # Number of ticks simulated
final_tick                               51320647066500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  81694                       # Simulator instruction rate (inst/s)
host_op_rate                                    95992                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4889396972                       # Simulator tick rate (ticks/s)
host_mem_usage                                 723156                       # Number of bytes of host memory used
host_seconds                                 10496.31                       # Real time elapsed on the host
sim_insts                                   857487967                       # Number of instructions simulated
sim_ops                                    1007562352                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       226752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       205312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           5743904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          43053832                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        407232                       # Number of bytes read from this memory
system.physmem.bytes_read::total             49637032                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      5743904                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5743904                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     69718464                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          69739044                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         3543                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         3208                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             105701                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             672729                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6363                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                791544                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1089351                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1091924                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           4418                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           4001                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               111922                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               838918                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7935                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                  967194                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          111922                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             111922                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1358488                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1358889                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1358488                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          4418                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          4001                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              111922                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              839319                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7935                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2326083                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        791544                       # Number of read requests accepted
system.physmem.writeReqs                      1694292                       # Number of write requests accepted
system.physmem.readBursts                      791544                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1694292                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 50622848                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     35968                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 107999616                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  49637032                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              108290596                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      562                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    6769                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          35256                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               48315                       # Per bank write bursts
system.physmem.perBankRdBursts::1               50150                       # Per bank write bursts
system.physmem.perBankRdBursts::2               46175                       # Per bank write bursts
system.physmem.perBankRdBursts::3               46946                       # Per bank write bursts
system.physmem.perBankRdBursts::4               45323                       # Per bank write bursts
system.physmem.perBankRdBursts::5               52981                       # Per bank write bursts
system.physmem.perBankRdBursts::6               47646                       # Per bank write bursts
system.physmem.perBankRdBursts::7               48748                       # Per bank write bursts
system.physmem.perBankRdBursts::8               44337                       # Per bank write bursts
system.physmem.perBankRdBursts::9               72322                       # Per bank write bursts
system.physmem.perBankRdBursts::10              50834                       # Per bank write bursts
system.physmem.perBankRdBursts::11              50772                       # Per bank write bursts
system.physmem.perBankRdBursts::12              48451                       # Per bank write bursts
system.physmem.perBankRdBursts::13              47387                       # Per bank write bursts
system.physmem.perBankRdBursts::14              44232                       # Per bank write bursts
system.physmem.perBankRdBursts::15              46363                       # Per bank write bursts
system.physmem.perBankWrBursts::0              103979                       # Per bank write bursts
system.physmem.perBankWrBursts::1              105038                       # Per bank write bursts
system.physmem.perBankWrBursts::2              105754                       # Per bank write bursts
system.physmem.perBankWrBursts::3              105161                       # Per bank write bursts
system.physmem.perBankWrBursts::4              103562                       # Per bank write bursts
system.physmem.perBankWrBursts::5              108435                       # Per bank write bursts
system.physmem.perBankWrBursts::6              103867                       # Per bank write bursts
system.physmem.perBankWrBursts::7              105467                       # Per bank write bursts
system.physmem.perBankWrBursts::8              102645                       # Per bank write bursts
system.physmem.perBankWrBursts::9              108407                       # Per bank write bursts
system.physmem.perBankWrBursts::10             108582                       # Per bank write bursts
system.physmem.perBankWrBursts::11             107982                       # Per bank write bursts
system.physmem.perBankWrBursts::12             105330                       # Per bank write bursts
system.physmem.perBankWrBursts::13             105345                       # Per bank write bursts
system.physmem.perBankWrBursts::14             103911                       # Per bank write bursts
system.physmem.perBankWrBursts::15             104029                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
system.physmem.totGap                    51320645833500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  770259                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1691719                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    523893                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    218096                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     34112                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     11428                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       784                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       453                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       412                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       327                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       162                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      157                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      123                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      119                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      110                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       96                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       90                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       49                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35494                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    67146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    82141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    96477                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    97233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   109038                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   106907                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   116227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   110532                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   123491                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   110542                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    98237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    89628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    89775                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    76304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    74747                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    73803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    70600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     4308                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     3795                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     3522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     3348                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     3077                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     3049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     2918                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     2900                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     2759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     2637                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     2554                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     2529                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     2364                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     2307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     2173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     2144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1691                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     1475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1311                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     1090                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      882                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      755                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       89                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       519566                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      305.297267                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     172.561612                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     342.602188                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         210755     40.56%     40.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       125086     24.08%     64.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        44418      8.55%     73.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        23610      4.54%     77.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        15941      3.07%     80.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        10357      1.99%     82.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8070      1.55%     84.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         7704      1.48%     85.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        73625     14.17%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         519566                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         66165                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        11.954266                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       69.214790                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           66159     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            4      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           66165                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         66165                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        25.504330                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       22.270889                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       18.258332                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23           44141     66.71%     66.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31            6693     10.12%     76.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39            8637     13.05%     89.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47            2199      3.32%     93.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55            1176      1.78%     94.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63             430      0.65%     95.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71             581      0.88%     96.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79             510      0.77%     97.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             438      0.66%     97.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95             204      0.31%     98.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103            335      0.51%     98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111           211      0.32%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119           211      0.32%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127            55      0.08%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135           142      0.21%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143            25      0.04%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            36      0.05%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159            19      0.03%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167            38      0.06%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175            22      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183            24      0.04%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             5      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             4      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             5      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             6      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             9      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-279             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           66165                       # Writes before turning the bus around for reads
system.physmem.totQLat                    15484448260                       # Total ticks spent queuing
system.physmem.totMemAccLat               30315360760                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   3954910000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       19576.23                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  38326.23                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.99                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.10                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.97                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.11                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.87                       # Average write queue length when enqueuing
system.physmem.readRowHits                     603455                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1355453                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.29                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.32                       # Row buffer hit rate for writes
system.physmem.avgGap                     20645225.93                       # Average gap between requests
system.physmem.pageHitRate                      79.04                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1965463920                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1072425750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3012968400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               5451384240                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3352015077840                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1226370177675                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29716624044750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34306511542575                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.473889                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49436215199501                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1713709140000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    170722374999                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1962455040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1070784000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3156644400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               5483576880                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3352015077840                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1227684074985                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29715471503250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34306844116395                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.480369                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49434282568001                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1713709140000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    172653903249                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           436                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          400                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          400                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           25                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               226505876                       # Number of BP lookups
system.cpu.branchPred.condPredicted         151515363                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12247822                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            159926869                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               104610641                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             65.411548                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                31076851                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             345252                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.checker.dtb.walker.walks            200647                       # Table walker walks requested
system.cpu.checker.dtb.walker.walksLong        200647                       # Table walker walks initiated with long descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples       200647                       # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0       200647    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total       200647                       # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walksPending::samples   1467106000                       # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0   1467106000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total   1467106000                       # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walkPageSizes::4K       155618     91.17%     91.17% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::2M        15067      8.83%    100.00% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::total       170685                       # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       200647                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       200647                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       170685                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       170685                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total       371332                       # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.dtb.read_hits            161284967                       # DTB read hits
system.cpu.checker.dtb.read_misses             149209                       # DTB read misses
system.cpu.checker.dtb.write_hits           146334371                       # DTB write hits
system.cpu.checker.dtb.write_misses             51438                       # DTB write misses
system.cpu.checker.dtb.flush_tlb                   20                       # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid        80016                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid            2058                       # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries            72843                       # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults           7088                       # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults             19208                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses        161434176                       # DTB read accesses
system.cpu.checker.dtb.write_accesses       146385809                       # DTB write accesses
system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.dtb.hits                 307619338                       # DTB hits
system.cpu.checker.dtb.misses                  200647                       # DTB misses
system.cpu.checker.dtb.accesses             307819985                       # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.checker.itb.walker.walks            120779                       # Table walker walks requested
system.cpu.checker.itb.walker.walksLong        120779                       # Table walker walks initiated with long descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples       120779                       # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0       120779    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total       120779                       # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples   1466561000                       # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0   1466561000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total   1466561000                       # Table walker pending requests distribution
system.cpu.checker.itb.walker.walkPageSizes::4K       108783     98.83%     98.83% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::2M         1287      1.17%    100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total       110070                       # Table walker page sizes translated
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       120779                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       120779                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       110070                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       110070                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total       230849                       # Table walker requests started/completed, data/inst
system.cpu.checker.itb.inst_hits            857899518                       # ITB inst hits
system.cpu.checker.itb.inst_misses             120779                       # ITB inst misses
system.cpu.checker.itb.read_hits                    0                       # DTB read hits
system.cpu.checker.itb.read_misses                  0                       # DTB read misses
system.cpu.checker.itb.write_hits                   0                       # DTB write hits
system.cpu.checker.itb.write_misses                 0                       # DTB write misses
system.cpu.checker.itb.flush_tlb                   20                       # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid        80016                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid            2058                       # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries            52284                       # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
system.cpu.checker.itb.inst_accesses        858020297                       # ITB inst accesses
system.cpu.checker.itb.hits                 857899518                       # DTB hits
system.cpu.checker.itb.misses                  120779                       # DTB misses
system.cpu.checker.itb.accesses             858020297                       # DTB accesses
system.cpu.checker.numCycles               1008137807                       # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    931379                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                931379                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        16662                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       157071                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore       405257                       # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples       526122                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean  1688.949521                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-32767       521687     99.16%     99.16% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-65535         1343      0.26%     99.41% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-98303         1868      0.36%     99.77% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::98304-131071          570      0.11%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-163839          209      0.04%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::163840-196607          174      0.03%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-229375           58      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::229376-262143          108      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-294911            8      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::294912-327679            3      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-360447           36      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::360448-393215           45      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-425983           11      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       526122                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       461527                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       458117     99.26%     99.26% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         2510      0.54%     99.80% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607          628      0.14%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          155      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679           55      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           42      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       461527                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 768881581580                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean     0.740934                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev     0.499994                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1  767107299580     99.77%     99.77% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3     970542000      0.13%     99.90% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5     364225500      0.05%     99.94% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7     157799500      0.02%     99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9     120916000      0.02%     99.98% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11     94826000      0.01%     99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13     21620500      0.00%     99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15     42242000      0.01%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17      2110500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 768881581580                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        157072     90.41%     90.41% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         16662      9.59%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       173734                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       931379                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       931379                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       173734                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       173734                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total      1105113                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    171278986                       # DTB read hits
system.cpu.dtb.read_misses                     671795                       # DTB read misses
system.cpu.dtb.write_hits                   149102166                       # DTB write hits
system.cpu.dtb.write_misses                    259584                       # DTB write misses
system.cpu.dtb.flush_tlb                           20                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               80016                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    2058                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    73098                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                       106                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  10235                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     69082                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                171950781                       # DTB read accesses
system.cpu.dtb.write_accesses               149361750                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         320381152                       # DTB hits
system.cpu.dtb.misses                          931379                       # DTB misses
system.cpu.dtb.accesses                     321312531                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    161841                       # Table walker walks requested
system.cpu.itb.walker.walksLong                161841                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1421                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       122616                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore        17088                       # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples       144753                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean   980.521993                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev  6808.510178                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767       144225     99.64%     99.64% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535          131      0.09%     99.73% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303          321      0.22%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071           37      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::163840-196607           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375            6      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::229376-262143            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::262144-294911            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       144753                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       141125                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 24337.182009                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-32767       134420     95.25%     95.25% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-65535         4577      3.24%     98.49% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-98303         1336      0.95%     99.44% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::98304-131071          512      0.36%     99.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-163839           95      0.07%     99.87% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::163840-196607           88      0.06%     99.93% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-229375           22      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::229376-262143           28      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-294911           15      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::294912-327679           14      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-360447            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::360448-393215            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       141125                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 657209390884                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean     0.938693                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev     0.240123                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0     40327296652      6.14%      6.14% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1    616846868232     93.86%     99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2        34699000      0.01%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3          527000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 657209390884                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        122616     98.85%     98.85% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1421      1.15%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       124037                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161841                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       161841                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       124037                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       124037                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       285878                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    360168043                       # ITB inst hits
system.cpu.itb.inst_misses                     161841                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           20                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               80016                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    2058                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    53745                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    372581                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                360329884                       # ITB inst accesses
system.cpu.itb.hits                         360168043                       # DTB hits
system.cpu.itb.misses                          161841                       # DTB misses
system.cpu.itb.accesses                     360329884                       # DTB accesses
system.cpu.numCycles                       1576983833                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          648826167                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1010661506                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   226505876                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          135687492                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     852638415                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                26165882                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                    3403646                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                27150                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles       9234109                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles      1027275                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          386                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 359779044                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               6134765                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                   47734                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples         1528240089                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.774898                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.161407                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                965897706     63.20%     63.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                215974848     14.13%     77.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 70846962      4.64%     81.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                275520573     18.03%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1528240089                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.143632                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.640883                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                527342057                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             504093722                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 436470729                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              51063982                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                9269599                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             33921165                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred               3872416                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1095869891                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              29092135                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                9269599                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                572608237                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                46122541                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles      363160924                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 442135288                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              94943500                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1076024490                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               6785579                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               4940621                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 314117                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 587788                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               42830435                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents            21754                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          1023810702                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1659713955                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1272840679                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           1685189                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             958043687                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 65767012                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts           27437914                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts       23747073                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 104751050                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            175241778                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           152679763                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           9977994                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          9053000                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1040458161                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded            27741753                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1056586315                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           3302783                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        53612674                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33630584                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         315276                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1528240089                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.691375                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.927907                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           873840021     57.18%     57.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           338263818     22.13%     79.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           236701790     15.49%     94.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            72838134      4.77%     99.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6577115      0.43%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5               19211      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1528240089                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                58408451     35.14%     35.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                 100871      0.06%     35.20% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                   26760      0.02%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc              763      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.21% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               44563063     26.81%     62.02% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              63134312     37.98%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                12      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             727619955     68.87%     68.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2547357      0.24%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                123270      0.01%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   5      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         120690      0.01%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            175181818     16.58%     85.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           150993162     14.29%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1056586315                       # Type of FU issued
system.cpu.iq.rate                           0.670005                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   166234220                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.157331                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         3808470802                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1121012820                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1038530652                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             2478919                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             941723                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       907476                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1221261060                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 1559463                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          4354414                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     13859524                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14300                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       143284                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      6341204                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2565738                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1859911                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                9269599                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 6359819                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               3950891                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1068424262                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             175241778                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            152679763                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts           23316187                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  61516                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               3818793                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         143284                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3692717                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      5135549                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8828266                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1045377154                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             171268732                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10291027                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        224348                       # number of nop insts executed
system.cpu.iew.exec_refs                    320367802                       # number of memory reference insts executed
system.cpu.iew.exec_branches                198404489                       # Number of branches executed
system.cpu.iew.exec_stores                  149099070                       # Number of stores executed
system.cpu.iew.exec_rate                     0.662897                       # Inst execution rate
system.cpu.iew.wb_sent                     1040225395                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1039438128                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 442335874                       # num instructions producing a value
system.cpu.iew.wb_consumers                 715873221                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.659130                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.617897                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        51477037                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls        27426477                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           8434480                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1516228883                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.664519                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.292276                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    998506921     65.85%     65.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    291444279     19.22%     85.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    121999456      8.05%     93.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     36692084      2.42%     95.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     28614798      1.89%     97.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     14261229      0.94%     98.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      8588058      0.57%     98.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      4227240      0.28%     99.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     11894818      0.78%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1516228883                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            857487967                       # Number of instructions committed
system.cpu.commit.committedOps             1007562352                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      307720812                       # Number of memory references committed
system.cpu.commit.loads                     161382253                       # Number of loads committed
system.cpu.commit.membars                     7017472                       # Number of memory barriers committed
system.cpu.commit.branches                  191417503                       # Number of branches committed
system.cpu.commit.fp_insts                     895898                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 925548459                       # Number of committed integer instructions.
system.cpu.commit.function_calls             25509836                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        697466429     69.22%     69.22% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         2165110      0.21%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv            98436      0.01%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       111523      0.01%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       161382253     16.02%     85.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      146338559     14.52%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1007562352                       # Class of committed instruction
system.cpu.commit.bw_lim_events              11894818                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   2555751551                       # The number of ROB reads
system.cpu.rob.rob_writes                  2129995502                       # The number of ROB writes
system.cpu.timesIdled                         8137427                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        48743744                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                 101064310429                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   857487967                       # Number of Instructions Simulated
system.cpu.committedOps                    1007562352                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.839074                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.839074                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.543752                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.543752                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1237547063                       # number of integer regfile reads
system.cpu.int_regfile_writes               738733253                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   1457540                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   782548                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 228190122                       # number of cc regfile reads
system.cpu.cc_regfile_writes                228796042                       # number of cc regfile writes
system.cpu.misc_regfile_reads              5248690758                       # number of misc regfile reads
system.cpu.misc_regfile_writes               27489325                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           9822587                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.985266                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           286182485                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9823099                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.133625                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1485676250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.985266                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999971                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999971                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          380                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           38                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1249763399                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1249763399                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    148780016                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       148780016                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    129548885                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      129548885                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       381333                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        381333                       # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       324563                       # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total       324563                       # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3352422                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3352422                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      3751270                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      3751270                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     278328901                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        278328901                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    278710234                       # number of overall hits
system.cpu.dcache.overall_hits::total       278710234                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      9497038                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       9497038                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data     11468447                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total     11468447                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1197141                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1197141                       # number of SoftPFReq misses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1233328                       # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total      1233328                       # number of WriteInvalidateReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       450623                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       450623                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     20965485                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       20965485                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     22162626                       # number of overall misses
system.cpu.dcache.overall_misses::total      22162626                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 140713387644                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 321962948230                       # number of WriteReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  38655244426                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::total  38655244426                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6327424004                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   6327424004                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       139001                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       139001                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 462676335874                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 462676335874                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 462676335874                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 462676335874                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    158277054                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    158277054                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    141017332                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    141017332                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1578474                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1578474                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1557891                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total      1557891                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3803045                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      3803045                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      3751275                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      3751275                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    299294386                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    299294386                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    300872860                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    300872860                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060003                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.060003                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081327                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.081327                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758417                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.758417                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.791665                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.791665                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.118490                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.118490                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.070050                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.070050                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.073661                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.073661                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305                       # average WriteReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609                       # average WriteInvalidateReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609                       # average WriteInvalidateReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22068.477589                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20876.422129                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     21410972                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs           1402072                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.270950                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      7597183                       # number of writebacks
system.cpu.dcache.writebacks::total           7597183                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4319062                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      4319062                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9426489                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      9426489                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data         7148                       # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.WriteInvalidateReq_mshr_hits::total         7148                       # number of WriteInvalidateReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       220034                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total       220034                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data     13745551                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total     13745551                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data     13745551                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total     13745551                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5177976                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5177976                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2041958                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2041958                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1190352                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1190352                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1226180                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1226180                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230589                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       230589                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      7219934                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      7219934                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      8410286                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      8410286                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  70110899674                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  70110899674                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53589743024                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  53589743024                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  18780468745                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  18780468745                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  35955294132                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  35955294132                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2813771248                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2813771248                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       128999                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       128999                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 123700642698                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 142481111443                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729238749                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729238749                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587095483                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587095483                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316334232                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316334232                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032715                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032715                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014480                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014480                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.754116                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.754116                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.787077                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.787077                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060633                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060633                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024123                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024123                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027953                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.027953                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          15084162                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.954207                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           343955623                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          15084674                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             22.801661                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       14174936000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.954207                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999911                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999911                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         374842526                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        374842526                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    343955623                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       343955623                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     343955623                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        343955623                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    343955623                       # number of overall hits
system.cpu.icache.overall_hits::total       343955623                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     15802123                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      15802123                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     15802123                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       15802123                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     15802123                       # number of overall misses
system.cpu.icache.overall_misses::total      15802123                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 208192919846                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 208192919846                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 208192919846                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 208192919846                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 208192919846                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 208192919846                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    359757746                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    359757746                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    359757746                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    359757746                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    359757746                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    359757746                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043924                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.043924                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.043924                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.043924                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.043924                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.043924                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13174.996793                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13174.996793                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13174.996793                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13174.996793                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13174.996793                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13174.996793                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        11061                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               978                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    11.309816                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst       717343                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total       717343                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst       717343                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total       717343                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst       717343                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total       717343                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15084780                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     15084780                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     15084780                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     15084780                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     15084780                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     15084780                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171798629050                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 171798629050                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171798629050                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 171798629050                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171798629050                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 171798629050                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1412899000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1412899000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1412899000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   1412899000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041930                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041930                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041930                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.041930                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041930                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.041930                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11388.872032                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11388.872032                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11388.872032                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11388.872032                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11388.872032                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11388.872032                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1166252                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65308.801684                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           29080427                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1229042                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            23.661052                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       2430267000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37210.550558                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   324.848912                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   496.111863                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  7620.063188                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19657.227164                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.567788                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004957                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007570                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.116273                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.299945                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996533                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          301                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        62489                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          300                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          518                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2670                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5157                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54081                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004593                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.953506                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        273259305                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       273259305                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       799874                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       299425                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst     15000245                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      6339023                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total       22438567                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      7597183                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      7597183                       # number of Writeback hits
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       730326                       # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total       730326                       # number of WriteInvalidateReq hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         9466                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         9466                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1583904                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1583904                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       799874                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       299425                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     15000245                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7922927                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        24022471                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       799874                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       299425                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     15000245                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7922927                       # number of overall hits
system.cpu.l2cache.overall_hits::total       24022471                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3543                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3208                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        84445                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       256196                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       347392                       # number of ReadReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       495854                       # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total       495854                       # number of WriteInvalidateReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        34479                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        34479                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       417812                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       417812                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         3543                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         3208                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        84445                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       674008                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        765204                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         3543                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         3208                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        84445                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       674008                       # number of overall misses
system.cpu.l2cache.overall_misses::total       765204                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    284358999                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    261200750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   6500329478                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  21309046436                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  28354935663                       # number of ReadReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data      3493350                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::total      3493350                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    414507203                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    414507203                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        72000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        72000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  34565495113                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  34565495113                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    284358999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    261200750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   6500329478                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  55874541549                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  62920430776                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    284358999                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    261200750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   6500329478                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  55874541549                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  62920430776                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       803417                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       302633                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst     15084690                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      6595219                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total     22785959                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      7597183                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      7597183                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1226180                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total      1226180                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43945                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        43945                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2001716                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2001716                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       803417                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       302633                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     15084690                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      8596935                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     24787675                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       803417                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       302633                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     15084690                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      8596935                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     24787675                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004410                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010600                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005598                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.038846                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.015246                       # miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.404389                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.404389                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.784594                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.784594                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.208727                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.208727                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004410                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.010600                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005598                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.078401                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.030870                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004410                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.010600                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005598                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.078401                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.030870                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 80259.384420                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81421.680175                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76977.079496                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83174.781948                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81622.304667                       # average ReadReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data     7.045118                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     7.045118                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12022.019287                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12022.019287                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        36000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        36000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82729.780650                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82729.780650                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 80259.384420                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81421.680175                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76977.079496                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82898.929314                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82227.001918                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 80259.384420                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81421.680175                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76977.079496                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82898.929314                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82227.001918                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       982720                       # number of writebacks
system.cpu.l2cache.writebacks::total           982720                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           21                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3543                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3208                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        84445                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       256175                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       347371                       # number of ReadReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data       495854                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       495854                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34479                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        34479                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       417812                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       417812                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3543                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3208                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        84445                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       673987                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       765183                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3543                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3208                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        84445                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       673987                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       765183                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    240086499                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    221074750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   5441255518                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  18116835264                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24019252031                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  19575424791                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  19575424791                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    345346475                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    345346475                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70001                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70001                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  29394156879                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  29394156879                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    240086499                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    221074750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5441255518                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  47510992143                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  53413408910                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    240086499                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    221074750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5441255518                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  47510992143                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  53413408910                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1103864500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289749251                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393613751                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176073500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176073500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1103864500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465822751                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569687251                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004410                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010600                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005598                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.038843                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015245                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.404389                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.404389                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784594                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784594                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.208727                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.208727                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004410                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010600                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005598                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.078399                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.030869                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004410                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010600                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005598                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.078399                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.030869                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68913.575436                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64435.496690                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.543628                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69145.818249                       # average ReadReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39478.202840                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39478.202840                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10016.139534                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10016.139534                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70352.591307                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70352.591307                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68913.575436                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64435.496690                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70492.445912                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69804.751164                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68913.575436                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64435.496690                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70492.445912                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69804.751164                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq       23340437                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      23332371                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33858                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33858                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      7597183                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1332844                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1226180                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        43948                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        43953                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2001716                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2001716                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     30212060                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27467336                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       733813                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1968769                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          60381978                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    965760880                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1115140164                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2421064                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6427336                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2089749444                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      606880                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     34513008                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        9.003347                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.057757                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::9           34397489     99.67%     99.67% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::10            115519      0.33%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value           10                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       34513008                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    26212619005                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1180500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   22673982421                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13673864954                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     432131982                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1166119344                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40381                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40381                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354228                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334264                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334264                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492670                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy          1042349161                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           179004202                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115461                       # number of replacements
system.iocache.tags.tagsinuse               10.424617                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115477                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13092188806000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.544621                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.879997                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221539                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.430000                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651539                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039668                       # Number of tag accesses
system.iocache.tags.data_accesses             1039668                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8815                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8852                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8815                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8855                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8815                       # number of overall misses
system.iocache.overall_misses::total             8855                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5527000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1934147111                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1939674111                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28899223848                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  28899223848                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5866000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1934147111                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1940013111                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5866000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1934147111                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1940013111                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8815                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8852                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8815                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8855                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8815                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8855                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 219122.696679                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 219415.440839                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 219086.743196                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 219415.440839                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 219086.743196                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        225873                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27588                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.187364                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8815                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8852                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8815                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8855                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8815                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8855                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3603000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1475641121                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1479244121                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23352302242                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23352302242                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3786000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1475641121                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1479427121                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3786000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1475641121                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1479427121                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 167072.515076                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 167072.515076                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              411277                       # Transaction distribution
system.membus.trans_dist::ReadResp             411277                       # Transaction distribution
system.membus.trans_dist::WriteReq              33858                       # Transaction distribution
system.membus.trans_dist::WriteResp             33858                       # Transaction distribution
system.membus.trans_dist::Writeback           1089351                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       602368                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       602368                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            35261                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           35263                       # Transaction distribution
system.membus.trans_dist::ReadExReq            417183                       # Transaction distribution
system.membus.trans_dist::ReadExResp           417183                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3620810                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3750918                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335177                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       335177                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4086095                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    143869516                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    144039988                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14058112                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14058112                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               158098100                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3154                       # Total snoops (count)
system.membus.snoop_fanout::samples           2500418                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2500418    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2500418                       # Request fanout histogram
system.membus.reqLayer0.occupancy           109711500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               42500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5440999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         16316164477                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7830132924                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          186594798                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16179                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------