path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.434893                       # Number of seconds simulated
sim_ticks                                47434893411000                       # Number of ticks simulated
final_tick                               47434893411000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  99639                       # Simulator instruction rate (inst/s)
host_op_rate                                   117176                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5152463712                       # Simulator tick rate (ticks/s)
host_mem_usage                                 784704                       # Number of bytes of host memory used
host_seconds                                  9206.25                       # Real time elapsed on the host
sim_insts                                   917301737                       # Number of instructions simulated
sim_ops                                    1078753903                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       208192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       203648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          4658336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         45847432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     22095168                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        91328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        66368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2323808                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         12264528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     10934912                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        422080                       # Number of bytes read from this memory
system.physmem.bytes_read::total             99115800                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      4658336                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2323808                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6982144                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     83002560                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          83023144                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         3253                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         3182                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             88739                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            716379                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       345237                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1427                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1037                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             36353                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            191646                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       170858                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6595                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1564706                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1296915                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1299489                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          4389                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          4293                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               98205                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              966534                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       465800                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1925                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          1399                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               48989                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              258555                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       230525                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8898                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2089512                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          98205                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          48989                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             147194                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1749821                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1750255                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1749821                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         4389                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         4293                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              98205                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             966968                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       465800                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1925                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         1399                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              48989                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             258555                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       230525                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8898                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3839767                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1564706                       # Number of read requests accepted
system.physmem.writeReqs                      1299489                       # Number of write requests accepted
system.physmem.readBursts                     1564706                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1299489                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                100111296                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     29888                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  83021568                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  99115800                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               83023144                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      467                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         228681                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               96105                       # Per bank write bursts
system.physmem.perBankRdBursts::1              104079                       # Per bank write bursts
system.physmem.perBankRdBursts::2               99076                       # Per bank write bursts
system.physmem.perBankRdBursts::3              102555                       # Per bank write bursts
system.physmem.perBankRdBursts::4               95026                       # Per bank write bursts
system.physmem.perBankRdBursts::5               98411                       # Per bank write bursts
system.physmem.perBankRdBursts::6               98571                       # Per bank write bursts
system.physmem.perBankRdBursts::7               95349                       # Per bank write bursts
system.physmem.perBankRdBursts::8               90083                       # Per bank write bursts
system.physmem.perBankRdBursts::9              124090                       # Per bank write bursts
system.physmem.perBankRdBursts::10              93867                       # Per bank write bursts
system.physmem.perBankRdBursts::11              97434                       # Per bank write bursts
system.physmem.perBankRdBursts::12              91060                       # Per bank write bursts
system.physmem.perBankRdBursts::13              95554                       # Per bank write bursts
system.physmem.perBankRdBursts::14              90000                       # Per bank write bursts
system.physmem.perBankRdBursts::15              92979                       # Per bank write bursts
system.physmem.perBankWrBursts::0               80467                       # Per bank write bursts
system.physmem.perBankWrBursts::1               87240                       # Per bank write bursts
system.physmem.perBankWrBursts::2               82424                       # Per bank write bursts
system.physmem.perBankWrBursts::3               84720                       # Per bank write bursts
system.physmem.perBankWrBursts::4               78521                       # Per bank write bursts
system.physmem.perBankWrBursts::5               82917                       # Per bank write bursts
system.physmem.perBankWrBursts::6               81751                       # Per bank write bursts
system.physmem.perBankWrBursts::7               80612                       # Per bank write bursts
system.physmem.perBankWrBursts::8               77294                       # Per bank write bursts
system.physmem.perBankWrBursts::9               85251                       # Per bank write bursts
system.physmem.perBankWrBursts::10              78271                       # Per bank write bursts
system.physmem.perBankWrBursts::11              81127                       # Per bank write bursts
system.physmem.perBankWrBursts::12              78007                       # Per bank write bursts
system.physmem.perBankWrBursts::13              81137                       # Per bank write bursts
system.physmem.perBankWrBursts::14              77706                       # Per bank write bursts
system.physmem.perBankWrBursts::15              79767                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          33                       # Number of times write queue was full causing retry
system.physmem.totGap                    47434891912500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1543348                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1296915                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    588411                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    392193                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    156445                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    159831                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     99518                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     60251                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     31814                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     29617                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     26249                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      7312                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     4196                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2603                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1676                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1352                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      882                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      666                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      550                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      422                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      135                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       91                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    18951                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    21518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    33036                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    40734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    49908                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    58222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    67476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    73957                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    80711                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    84361                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    87259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    93166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    91933                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    94699                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   106371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    99156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    93223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    82575                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     5494                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     3221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1939                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1368                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      374                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      431                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      340                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      277                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      294                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      389                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      271                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      225                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       69                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       977888                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      187.273406                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     115.248079                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     243.900483                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         583799     59.70%     59.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       193375     19.77%     79.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        62560      6.40%     85.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        34177      3.49%     89.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        24599      2.52%     91.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        13672      1.40%     93.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        13781      1.41%     94.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         7457      0.76%     95.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        44468      4.55%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         977888                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         73621                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.246927                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      254.221432                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          73618    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::65536-69631            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           73621                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         73621                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.620136                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.126079                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.628572                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           68415     92.93%     92.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            2834      3.85%     96.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             416      0.57%     97.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             328      0.45%     97.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              84      0.11%     97.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             303      0.41%     98.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             179      0.24%     98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             107      0.15%     98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              91      0.12%     98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             122      0.17%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              36      0.05%     99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              46      0.06%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             419      0.57%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              29      0.04%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              25      0.03%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             117      0.16%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              10      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             4      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             5      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             3      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            27      0.04%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           73621                       # Writes before turning the bus around for reads
system.physmem.totQLat                    78457411069                       # Total ticks spent queuing
system.physmem.totMemAccLat              107786892319                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   7821195000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       50156.92                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  68906.92                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.11                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.75                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.09                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.75                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.14                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1261076                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    622485                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.62                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  47.99                       # Row buffer hit rate for writes
system.physmem.avgGap                     16561334.66                       # Average gap between requests
system.physmem.pageHitRate                      65.82                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3784611600                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2065016250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                6155541600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4268064960                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3098216175600                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1175166619965                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27430083930000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31719739959975                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.700662                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45632003284876                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1583955100000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    218928032624                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3608221680                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1968771750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                6045468000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4137868800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3098216175600                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1172302278480                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27432596510250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31718875294560                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.682434                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45636187348814                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1583955100000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    214746668686                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           572                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          528                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             39                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           11                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              146144434                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         97047776                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          7141884                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups           102585049                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               68142392                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            66.425266                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               20061645                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            208019                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   627056                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               627056                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13350                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        99805                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       293358                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       333698                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2422.801455                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 15109.123610                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       330908     99.16%     99.16% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         1425      0.43%     99.59% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607         1094      0.33%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          126      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679           36      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           71      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751           25      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       333698                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       325671                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 20358.917435                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 16786.442146                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 23186.053079                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       321319     98.66%     98.66% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          949      0.29%     98.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607         2404      0.74%     99.69% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          140      0.04%     99.74% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          546      0.17%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215          110      0.03%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751          121      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           45      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       325671                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 568195090048                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.606171                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.541778                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 566772056048     99.75%     99.75% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3    811255500      0.14%     99.89% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5    288193500      0.05%     99.94% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7    133409000      0.02%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9    101036500      0.02%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11     47966000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13     17568000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15     22933000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       641000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19        31500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 568195090048                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        99806     88.20%     88.20% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        13350     11.80%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       113156                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       627056                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       627056                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       113156                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       113156                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       740212                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   106442927                       # DTB read hits
system.cpu0.dtb.read_misses                    452572                       # DTB read misses
system.cpu0.dtb.write_hits                   87367482                       # DTB write hits
system.cpu0.dtb.write_misses                   174484                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              44087                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1063                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   43076                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      336                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  7862                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    41749                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               106895499                       # DTB read accesses
system.cpu0.dtb.write_accesses               87541966                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        193810409                       # DTB hits
system.cpu0.dtb.misses                         627056                       # DTB misses
system.cpu0.dtb.accesses                    194437465                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    89572                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                89572                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1024                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        63745                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        10456                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        79116                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1699.586683                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 13044.450560                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        78197     98.84%     98.84% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          434      0.55%     99.39% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303           37      0.05%     99.43% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071           79      0.10%     99.53% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839          275      0.35%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607           59      0.07%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143            6      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911            7      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        79116                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        75225                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26620.711200                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 21926.293248                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 30000.304563                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        72890     96.90%     96.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          127      0.17%     97.06% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607         1867      2.48%     99.55% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143          130      0.17%     99.72% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679          117      0.16%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           47      0.06%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           31      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        75225                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 417841685688                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.859653                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.347613                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    58676119976     14.04%     14.04% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   359136359212     85.95%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       25573000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        3283500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         186000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          60000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6         104000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 417841685688                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        63745     98.42%     98.42% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         1024      1.58%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        64769                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        89572                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        89572                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        64769                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        64769                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       154341                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   230754760                       # ITB inst hits
system.cpu0.itb.inst_misses                     89572                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              44087                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1063                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   31365                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   227814                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               230844332                       # ITB inst accesses
system.cpu0.itb.hits                        230754760                       # DTB hits
system.cpu0.itb.misses                          89572                       # DTB misses
system.cpu0.itb.accesses                    230844332                       # DTB accesses
system.cpu0.numCycles                       860058385                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          93823767                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     647034006                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  146144434                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          88204037                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    713428063                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               15421284                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   2142608                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles              370377                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      6662477                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       811703                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles       935488                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                230526197                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              1802314                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  29828                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         825885125                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.917836                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.204243                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               462725297     56.03%     56.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1               141134334     17.09%     73.12% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                49183945      5.96%     79.07% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3               172841549     20.93%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           825885125                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.169924                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.752314                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               112769742                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            426082666                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                241448796                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             40086734                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5497187                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            21049410                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              2256773                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             670218998                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts             24585217                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5497187                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               150343342                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               70257974                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     265091659                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                243360217                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             91334746                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             651968055                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              6322268                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents             11333163                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                398238                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                892987                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              53687870                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents           12055                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          623161441                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups           1008090615                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       769730678                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           803084                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            561865875                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                61295566                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          16618595                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      14448752                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 81009207                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           106588320                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           90921259                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          9791542                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         8386441                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 628410475                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           16690332                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                633219394                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued          2873840                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       57472988                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     37517559                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        288712                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    825885125                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.766716                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.051496                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          480372364     58.16%     58.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1          144500445     17.50%     75.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2          122618774     14.85%     90.51% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           70098834      8.49%     99.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            8288641      1.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5               6067      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      825885125                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               65372240     45.40%     45.40% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 70238      0.05%     45.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                  24747      0.02%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc              29      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead              37918627     26.33%     71.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite             40615883     28.21%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass               10      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            433018605     68.38%     68.38% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1583156      0.25%     68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                81666      0.01%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         80947      0.01%     68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           109728452     17.33%     85.99% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           88726558     14.01%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             633219394                       # Type of FU issued
system.cpu0.iq.rate                          0.736252                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                  144001764                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.227412                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        2237858803                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        702176142                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    615023589                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1340714                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            546565                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       499647                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             776393889                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 827259                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         2940154                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     13228982                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        17998                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       150420                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      6097724                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2855732                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      4944067                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5497187                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                8555370                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              7804154                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          645228891                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            106588320                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            90921259                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          14154267                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 60797                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              7667643                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        150420                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2190803                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      3056972                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             5247775                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            624930976                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            106438227                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          7669606                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       128084                       # number of nop insts executed
system.cpu0.iew.exec_refs                   193805308                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               117788400                       # Number of branches executed
system.cpu0.iew.exec_stores                  87367081                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.726615                       # Inst execution rate
system.cpu0.iew.wb_sent                     616360773                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    615523236                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                299533919                       # num instructions producing a value
system.cpu0.iew.wb_consumers                491459888                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.715676                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.609478                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       50152735                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       16401620                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4928429                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    816336878                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.719835                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.528210                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    559210939     68.50%     68.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1    132620550     16.25%     84.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     57447612      7.04%     91.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     19359516      2.37%     94.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     13667086      1.67%     95.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      9472900      1.16%     96.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      6300261      0.77%     97.76% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3865026      0.47%     98.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     14392988      1.76%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    816336878                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           500561663                       # Number of instructions committed
system.cpu0.commit.committedOps             587627818                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     178182873                       # Number of memory references committed
system.cpu0.commit.loads                     93359338                       # Number of loads committed
system.cpu0.commit.membars                    3999106                       # Number of memory barriers committed
system.cpu0.commit.branches                 111869987                       # Number of branches committed
system.cpu0.commit.fp_insts                    487433                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                538915028                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            14906557                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       407981366     69.43%     69.43% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1327807      0.23%     69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           64470      0.01%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        71302      0.01%     69.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.68% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       93359338     15.89%     85.57% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      84823535     14.43%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        587627818                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             14392988                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1435053387                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1285071513                       # The number of ROB writes
system.cpu0.timesIdled                        1102508                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       34173260                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 94009700955                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  500561663                       # Number of Instructions Simulated
system.cpu0.committedOps                    587627818                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.718187                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.718187                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.582009                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.582009                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               737541509                       # number of integer regfile reads
system.cpu0.int_regfile_writes              438217894                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   788412                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  466436                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                137084844                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               137795028                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1439828550                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              16463907                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements          6421526                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          508.135251                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          165251545                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6422031                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            25.731976                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       2962355000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   508.135251                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.992452                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.992452                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          505                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          452                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.986328                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        369713036                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       369713036                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     86498014                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       86498014                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     73594824                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      73594824                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       223952                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       223952                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       261481                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       261481                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1906554                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1906554                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1959919                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1959919                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    160092838                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       160092838                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    160316790                       # number of overall hits
system.cpu0.dcache.overall_hits::total      160316790                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      7115044                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7115044                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      7950326                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      7950326                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       760555                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       760555                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       841390                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       841390                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       287295                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       287295                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       195310                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       195310                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     15065370                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      15065370                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     15825925                       # number of overall misses
system.cpu0.dcache.overall_misses::total     15825925                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 123619441500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 123619441500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 174765170319                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 174765170319                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  99329075406                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  99329075406                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4513560000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4513560000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4763112500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4763112500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      4991000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      4991000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 298384611819                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 298384611819                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 298384611819                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 298384611819                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     93613058                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     93613058                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     81545150                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     81545150                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       984507                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       984507                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1102871                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1102871                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2193849                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2193849                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2155229                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2155229                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    175158208                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    175158208                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    176142715                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    176142715                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.076005                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.076005                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.097496                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.097496                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.772524                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.772524                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.762909                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.762909                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.130955                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.130955                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.090621                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.090621                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086010                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.086010                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.089847                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.089847                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17374.374846                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17374.374846                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21982.138886                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 21982.138886                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 118053.548778                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 118053.548778                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15710.541430                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15710.541430                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24387.448159                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24387.448159                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19805.992937                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19805.992937                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18854.165669                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18854.165669                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     31101776                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets     27008277                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           772694                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         787427                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    40.251090                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    34.299404                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      4324525                       # number of writebacks
system.cpu0.dcache.writebacks::total          4324525                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3632070                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      3632070                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6394266                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      6394266                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4384                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         4384                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       147311                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       147311                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data     10026336                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total     10026336                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data     10026336                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total     10026336                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3482974                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3482974                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1556060                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1556060                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       753575                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       753575                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       837006                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       837006                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       139984                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       139984                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       195309                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       195309                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5039034                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5039034                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5792609                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5792609                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31951                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31951                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        31485                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        31485                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        63436                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        63436                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  56753773500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  56753773500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  38838935578                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  38838935578                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  19682576500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  19682576500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  98248508406                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  98248508406                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1973900000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1973900000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4567861500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4567861500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      4933000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      4933000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  95592709078                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  95592709078                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115275285578                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 115275285578                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5771319500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5771319500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5597630000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5597630000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11368949500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11368949500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037206                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037206                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019082                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019082                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.765434                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.765434                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.758934                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.758934                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.063807                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.063807                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.090621                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.090621                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028768                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028768                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032886                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032886                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16294.630250                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16294.630250                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24959.793053                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24959.793053                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26118.935076                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26118.935076                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 117380.889033                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 117380.889033                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14100.897245                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14100.897245                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23387.869991                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23387.869991                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18970.443358                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18970.443358                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19900.408534                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19900.408534                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180630.324559                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180630.324559                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177787.200254                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177787.200254                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179219.205183                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179219.205183                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          6358728                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.935177                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          223756411                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          6359240                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.186030                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      22852216000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.935177                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999873                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999873                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          410                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        467353436                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       467353436                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    223756411                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      223756411                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    223756411                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       223756411                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    223756411                       # number of overall hits
system.cpu0.icache.overall_hits::total      223756411                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6740667                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      6740667                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6740667                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       6740667                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6740667                       # number of overall misses
system.cpu0.icache.overall_misses::total      6740667                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  78361220616                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  78361220616                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  78361220616                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  78361220616                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  78361220616                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  78361220616                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    230497078                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    230497078                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    230497078                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    230497078                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    230497078                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    230497078                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029244                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.029244                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029244                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.029244                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029244                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.029244                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11625.143419                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11625.143419                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11625.143419                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11625.143419                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11625.143419                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11625.143419                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs     12527067                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1547                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           814769                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             13                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.374992                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          119                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       381387                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       381387                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       381387                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       381387                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       381387                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       381387                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6359280                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      6359280                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6359280                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      6359280                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6359280                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      6359280                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  70398317173                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  70398317173                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  70398317173                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  70398317173                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  70398317173                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  70398317173                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2939725498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2939725498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2939725498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2939725498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027589                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027589                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027589                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.027589                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027589                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.027589                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11070.171021                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11070.171021                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11070.171021                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11070.171021                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11070.171021                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11070.171021                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138054.170095                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138054.170095                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      8863203                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      8872058                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         7949                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1112734                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2914685                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16233.717637                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          21584031                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2930348                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            7.365689                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle     21271828500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  7511.186177                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    88.364339                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    96.668630                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4222.815045                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3387.843530                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   926.839916                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.458446                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.005393                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005900                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.257740                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.206778                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.056570                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.990827                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1335                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           99                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14229                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           95                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          255                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          575                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          410                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           74                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          796                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4905                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4871                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3657                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.081482                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006042                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.868469                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       436831326                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      436831326                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       607592                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       191548                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        799140                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      4324517                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      4324517                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       114203                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total       114203                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36958                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        36958                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       970189                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       970189                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5673182                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      5673182                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3273926                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      3273926                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       211331                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       211331                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       607592                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       191548                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      5673182                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      4244115                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       10716437                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       607592                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       191548                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      5673182                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      4244115                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      10716437                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        13844                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10570                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        24414                       # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks            2                       # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total            2                       # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       138430                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       138430                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       158345                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       158345                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            6                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       344034                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       344034                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       686063                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       686063                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1100006                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1100006                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       624163                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       624163                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        13844                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker        10570                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       686063                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1444040                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2154517                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        13844                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker        10570                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       686063                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1444040                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2154517                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    747131500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    657491000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   1404622500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   4320468000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   4320468000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3850233000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3850233000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      4846000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      4846000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  23100204997                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  23100204997                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  27039967498                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  27039967498                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  50121323488                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  50121323488                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  94690450497                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total  94690450497                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    747131500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    657491000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  27039967498                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  73221528485                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 101666118483                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    747131500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    657491000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  27039967498                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  73221528485                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 101666118483                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       621436                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       202118                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       823554                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      4324519                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      4324519                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       252633                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       252633                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       195303                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       195303                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1314223                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1314223                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6359245                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      6359245                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4373932                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      4373932                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       835494                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       835494                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       621436                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       202118                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      6359245                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5688155                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     12870954                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       621436                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       202118                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      6359245                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5688155                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     12870954                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022277                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.052296                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.029645                       # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.547949                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.547949                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.810766                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.810766                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.261777                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.261777                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.107884                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.107884                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.251491                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.251491                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.747059                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.747059                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022277                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.052296                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.107884                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.253868                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.167394                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022277                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.052296                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.107884                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.253868                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.167394                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 53967.892228                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 62203.500473                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 57533.484886                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 31210.489056                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 31210.489056                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 24315.469386                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 24315.469386                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 807666.666667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 807666.666667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67145.122276                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67145.122276                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39413.242658                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39413.242658                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 45564.591000                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 45564.591000                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 151707.887999                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 151707.887999                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53967.892228                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 62203.500473                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39413.242658                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50706.025100                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 47187.429240                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53967.892228                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 62203.500473                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39413.242658                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50706.025100                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 47187.429240                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs         4612                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs              22                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   209.636364                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1594853                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1594853                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            7                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          173                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          180                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        69770                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total        69770                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            3                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         7585                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         7585                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            3                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          173                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            3                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        77355                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        77538                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            7                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          173                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            3                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        77355                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        77538                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13837                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10397                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        24234                       # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks            2                       # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total            2                       # number of Writeback MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       119189                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total       119189                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       853540                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       853540                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       138430                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       138430                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       158345                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       158345                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       274264                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       274264                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       686060                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       686060                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1092421                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1092421                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       624160                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       624160                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13837                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10397                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       686060                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1366685                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      2076979                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        13837                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10397                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       686060                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1366685                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       853540                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2930519                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31951                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        53245                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        31485                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        31485                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        63436                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        84730                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    663983000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    585367500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1249350500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  68949295019                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  68949295019                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4907856994                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4907856994                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3084199996                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3084199996                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      4498000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4498000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  17239432497                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  17239432497                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  22923448498                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  22923448498                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  43011997988                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  43011997988                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  90945024497                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  90945024497                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    663983000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    585367500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  22923448498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  60251430485                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  84424229483                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    663983000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    585367500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  22923448498                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  60251430485                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  68949295019                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 153373524502                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780019500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5515655500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8295675000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5356039467                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5356039467                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   2780019500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10871694967                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  13651714467                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022266                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.051440                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.029426                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.547949                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.547949                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.810766                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.810766                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.208689                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.208689                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.107884                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.107884                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.249757                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249757                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.747055                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.747055                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022266                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.051440                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.107884                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240269                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.161369                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022266                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.051440                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.107884                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240269                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.227685                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 51553.623009                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80780.391099                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 80780.391099                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35453.709413                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35453.709413                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19477.722669                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19477.722669                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 749666.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 749666.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62857.073830                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62857.073830                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33413.183246                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33413.183246                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39373.096991                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39373.096991                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145707.870573                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145707.870573                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33413.183246                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44085.821155                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40647.608610                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33413.183246                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44085.821155                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80780.391099                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52336.642247                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172628.571876                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 155801.953235                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170114.005622                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170114.005622                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171380.524734                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161120.199068                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests     26498119                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     13615382                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2337                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       550917                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       550892                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops           25                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq       1014324                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     11851775                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        31486                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        31485                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      5956604                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict     10410037                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1088232                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            6                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       474368                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       351600                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       519661                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           63                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1396851                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1324661                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6359280                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5366614                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       842272                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       835494                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     19118379                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20677259                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       436050                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1348581                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         41580269                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    407332384                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    648350241                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1616944                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4971488                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1062271057                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    6461178                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     33294085                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.028312                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.165866                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          32351497     97.17%     97.17% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            942563      2.83%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                25      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      33294085                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   17918792438                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    208202715                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   9565441520                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   9227310290                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    234328206                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    727701378                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              122053066                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         81331643                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          6140345                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            85523370                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               55672017                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            65.095677                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               16431061                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            166790                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   513343                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               513343                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10145                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        80504                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       231589                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       281754                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2191.677847                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 13834.020871                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       279857     99.33%     99.33% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1045      0.37%     99.70% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607          593      0.21%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143          154      0.05%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679           32      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           54      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751           12      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       281754                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       256242                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 18411.043076                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 15820.375131                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 14815.596994                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       254819     99.44%     99.44% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          556      0.22%     99.66% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          633      0.25%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           56      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           78      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           63      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           21      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::983040-1.04858e+06            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       256242                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 430767474576                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.581742                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.547950                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 429773436576     99.77%     99.77% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3    519356000      0.12%     99.89% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5    211618500      0.05%     99.94% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7    107822000      0.03%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9     75775500      0.02%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11     45293000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13     13801500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15     19976000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       394000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19         1500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 430767474576                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        80504     88.81%     88.81% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        10145     11.19%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        90649                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       513343                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       513343                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        90649                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        90649                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       603992                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    90392235                       # DTB read hits
system.cpu1.dtb.read_misses                    355030                       # DTB read misses
system.cpu1.dtb.write_hits                   74292452                       # DTB write hits
system.cpu1.dtb.write_misses                   158313                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              44087                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1063                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   34737                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      572                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  5833                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    38175                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                90747265                       # DTB read accesses
system.cpu1.dtb.write_accesses               74450765                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        164684687                       # DTB hits
system.cpu1.dtb.misses                         513343                       # DTB misses
system.cpu1.dtb.accesses                    165198030                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    79836                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                79836                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          812                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        57876                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore         9466                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        70370                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1202.877647                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  9654.881733                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-65535        70178     99.73%     99.73% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-131071           41      0.06%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-196607          131      0.19%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-262143           11      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-327679            7      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        70370                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        68154                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 22918.860228                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 20570.604774                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 17513.278330                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        67528     99.08%     99.08% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071           75      0.11%     99.19% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          455      0.67%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           42      0.06%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           28      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        68154                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 396407660708                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.833666                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.372525                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    65955607768     16.64%     16.64% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   330434317940     83.36%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       16293000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        1234500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         163500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5          44000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 396407660708                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        57876     98.62%     98.62% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          812      1.38%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        58688                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        79836                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        79836                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        58688                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        58688                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       138524                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   192024896                       # ITB inst hits
system.cpu1.itb.inst_misses                     79836                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              44087                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1063                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   24498                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   203556                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               192104732                       # ITB inst accesses
system.cpu1.itb.hits                        192024896                       # DTB hits
system.cpu1.itb.misses                          79836                       # DTB misses
system.cpu1.itb.accesses                    192104732                       # DTB accesses
system.cpu1.numCycles                       663967264                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          80600357                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     540678400                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  122053066                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          72103078                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    547218750                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               13194102                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   1722175                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles              292741                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles      5852987                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       747163                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles       786410                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                191800841                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              1580435                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  27130                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         643817634                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.987423                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.222838                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               339738489     52.77%     52.77% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1               118160249     18.35%     71.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                40196713      6.24%     77.37% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3               145722183     22.63%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           643817634                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.183824                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.814315                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                95925032                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            307565159                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                202328162                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             33349835                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               4649446                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            17381659                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1984856                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             561624259                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts             21210320                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               4649446                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               127605464                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               43917048                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     205458777                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                203595973                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             58590926                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             546425758                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts              5335623                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents              9251054                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                227617                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                291872                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              27374536                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents           10500                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          518347442                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            840457464                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       646223551                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           691924                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            466279930                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                52067506                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          14268129                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      12524757                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 67234415                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            90658674                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           77385188                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          8528695                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         7392702                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 526120257                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           14498185                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                530312729                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued          2450487                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       49492350                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     31830796                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        264307                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    643817634                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.823700                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.068099                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          353942401     54.98%     54.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1          122398683     19.01%     73.99% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2          101611501     15.78%     89.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           58772797      9.13%     98.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            7088607      1.10%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               3645      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      643817634                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu               53425749     43.94%     43.94% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 46790      0.04%     43.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                   9685      0.01%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc              19      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead              32795787     26.97%     70.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite             35319606     29.05%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               84      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            360430820     67.97%     67.97% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1171247      0.22%     68.19% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                68672      0.01%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         45220      0.01%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            93137728     17.56%     85.77% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           75458910     14.23%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             530312729                       # Type of FU issued
system.cpu1.iq.rate                          0.798703                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                  121597636                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.229294                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1827371450                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        589808611                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    515064806                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1119763                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            442884                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       412109                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             651211996                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 698285                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         2417067                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     11379314                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        14413                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       141714                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      5438356                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      2432171                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      3747564                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               4649446                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                5786949                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              2152685                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          540731877                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             90658674                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            77385188                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          12325629                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 58000                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              2039251                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        141714                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       1867697                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2587615                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4455312                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            523333067                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             90385914                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          6476972                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       113435                       # number of nop insts executed
system.cpu1.iew.exec_refs                   164677509                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                98047931                       # Number of branches executed
system.cpu1.iew.exec_stores                  74291595                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.788191                       # Inst execution rate
system.cpu1.iew.wb_sent                     516143321                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    515476915                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                249234254                       # num instructions producing a value
system.cpu1.iew.wb_consumers                407965513                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.776359                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.610920                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       43327267                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       14233878                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4192740                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    635627275                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.772664                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.570415                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    419865335     66.06%     66.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1    112371204     17.68%     83.73% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     47717309      7.51%     91.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     15913228      2.50%     93.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     11392527      1.79%     95.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      7668933      1.21%     96.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5369975      0.84%     97.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3184156      0.50%     98.09% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     12144608      1.91%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    635627275                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           416740074                       # Number of instructions committed
system.cpu1.commit.committedOps             491126085                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     151226191                       # Number of memory references committed
system.cpu1.commit.loads                     79279359                       # Number of loads committed
system.cpu1.commit.membars                    3502305                       # Number of memory barriers committed
system.cpu1.commit.branches                  92953281                       # Number of branches committed
system.cpu1.commit.fp_insts                    403468                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                451237639                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            12195676                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       338863536     69.00%     69.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult         941904      0.19%     69.19% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           54586      0.01%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        39826      0.01%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       79279359     16.14%     85.35% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      71946832     14.65%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        491126085                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             12144608                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1154417922                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1077060232                       # The number of ROB writes
system.cpu1.timesIdled                         910594                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       20149630                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 94205821171                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  416740074                       # Number of Instructions Simulated
system.cpu1.committedOps                    491126085                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.593241                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.593241                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.627652                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.627652                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               618723699                       # number of integer regfile reads
system.cpu1.int_regfile_writes              366638237                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   681038                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  305796                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                111144597                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               111901561                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1146158029                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              14345264                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements          5008277                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          444.234833                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          141116395                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5008789                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            28.173755                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8487531137500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   444.234833                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.867646                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.867646                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          394                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        313835409                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       313835409                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     73808968                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       73808968                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     63012404                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      63012404                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       166300                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       166300                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data        49799                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total        49799                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1689842                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1689842                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1700596                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1700596                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    136821372                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       136821372                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    136987672                       # number of overall hits
system.cpu1.dcache.overall_hits::total      136987672                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      5891473                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      5891473                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      6580040                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      6580040                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       617645                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       617645                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       417038                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       417038                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       243108                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       243108                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       189778                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       189778                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data     12471513                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total      12471513                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data     13089158                       # number of overall misses
system.cpu1.dcache.overall_misses::total     13089158                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  92058874500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  92058874500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 133118807489                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 133118807489                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  16001999882                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  16001999882                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3690480000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   3690480000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4542175000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4542175000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      4462000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      4462000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 225177681989                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 225177681989                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 225177681989                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 225177681989                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     79700441                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     79700441                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     69592444                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     69592444                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       783945                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       783945                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       466837                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       466837                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1932950                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1932950                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1890374                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1890374                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    149292885                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    149292885                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    150076830                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    150076830                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.073920                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.073920                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.094551                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.094551                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.787868                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.787868                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.893327                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.893327                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.125770                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.125770                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100392                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100392                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.083537                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.083537                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.087216                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.087216                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15625.782296                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15625.782296                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20230.698824                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20230.698824                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 38370.603835                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 38370.603835                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15180.413643                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15180.413643                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23934.149375                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23934.149375                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18055.362007                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18055.362007                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17203.374120                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17203.374120                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs      4151520                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets     21118604                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs           339495                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets         658226                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    12.228516                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    32.084123                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3259663                       # number of writebacks
system.cpu1.dcache.writebacks::total          3259663                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      2995366                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total      2995366                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5317058                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      5317058                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3866                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total         3866                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       125871                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total       125871                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      8312424                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      8312424                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      8312424                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      8312424                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2896107                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2896107                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1262982                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1262982                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       617580                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       617580                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       413172                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       413172                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       117237                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       117237                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       189777                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       189777                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4159089                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4159089                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4776669                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4776669                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         6826                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         6826                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7171                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7171                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        13997                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        13997                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  41972381500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  41972381500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  27436414661                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  27436414661                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14179581000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14179581000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  15426665382                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  15426665382                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1682703500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1682703500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4352455000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4352455000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      4405000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      4405000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  69408796161                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  69408796161                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  83588377161                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  83588377161                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    764918000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    764918000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    914224500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    914224500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1679142500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1679142500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036337                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036337                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018148                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018148                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.787785                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.787785                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.885046                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.885046                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060652                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.060652                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100391                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100391                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027859                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027859                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031828                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031828                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14492.690187                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14492.690187                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21723.519940                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21723.519940                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22959.909647                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22959.909647                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 37337.151070                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 37337.151070                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14353.007156                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14353.007156                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22934.575844                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22934.575844                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16688.461382                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16688.461382                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17499.302791                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17499.302791                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112059.478465                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 112059.478465                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 127489.122856                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 127489.122856                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119964.456669                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119964.456669                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          5544230                       # number of replacements
system.cpu1.icache.tags.tagsinuse          501.780204                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          185921865                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5544742                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            33.531202                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8527218243000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.780204                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980039                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.980039                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          348                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        389132386                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       389132386                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    185921865                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      185921865                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    185921865                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       185921865                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    185921865                       # number of overall hits
system.cpu1.icache.overall_hits::total      185921865                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      5871956                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      5871956                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      5871956                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       5871956                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      5871956                       # number of overall misses
system.cpu1.icache.overall_misses::total      5871956                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  64156067699                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  64156067699                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  64156067699                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  64156067699                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  64156067699                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  64156067699                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    191793821                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    191793821                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    191793821                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    191793821                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    191793821                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    191793821                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030616                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.030616                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030616                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.030616                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030616                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.030616                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10925.842717                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10925.842717                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10925.842717                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10925.842717                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10925.842717                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10925.842717                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs      9696468                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          348                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs           701587                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              5                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.820763                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets    69.600000                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       327212                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total       327212                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst       327212                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total       327212                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst       327212                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total       327212                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5544744                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5544744                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5544744                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5544744                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5544744                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5544744                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  57863828928                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  57863828928                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  57863828928                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  57863828928                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  57863828928                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  57863828928                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8907998                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8907998                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8907998                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      8907998                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028910                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028910                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028910                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.028910                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028910                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.028910                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10435.798105                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10435.798105                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10435.798105                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10435.798105                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10435.798105                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10435.798105                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132955.194030                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132955.194030                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      6820164                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      6823757                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit         3326                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       803331                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         1997658                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13422.615868                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          18456162                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2013697                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            9.165312                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9617415490500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  3897.343042                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    66.015363                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    51.895680                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3723.378261                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  4768.192327                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   915.791195                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.237875                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004029                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003167                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.227257                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.291027                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.055895                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.819251                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1310                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           85                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14644                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           29                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          243                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          653                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          377                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           38                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           23                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1361                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5328                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4585                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3240                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.079956                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005188                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.893799                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       360770404                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      360770404                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       497732                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       168884                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        666616                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3259650                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3259650                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        66819                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        66819                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        31621                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        31621                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       793791                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       793791                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4983800                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4983800                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2698278                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2698278                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       190326                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       190326                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       497732                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       168884                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4983800                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3492069                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        9142485                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       497732                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       168884                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4983800                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3492069                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       9142485                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10518                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7585                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        18103                       # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks           13                       # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total           13                       # number of Writeback misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       142287                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       142287                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       158148                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       158148                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            8                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       268312                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       268312                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       560943                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       560943                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       929119                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       929119                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       221533                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       221533                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10518                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7585                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       560943                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1197431                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1776477                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10518                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7585                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       560943                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1197431                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1776477                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    440507000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    317156000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    757663000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   4278657000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   4278657000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3704095999                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3704095999                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      4317497                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      4317497                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  13921759999                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  13921759999                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  19818008500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  19818008500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  34488387987                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  34488387987                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  13205591500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total  13205591500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    440507000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    317156000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  19818008500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  48410147986                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  68985819486                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    440507000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    317156000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  19818008500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  48410147986                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  68985819486                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       508250                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       176469                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       684719                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3259663                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3259663                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       209106                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       209106                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       189769                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       189769                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1062103                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1062103                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5544743                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      5544743                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3627397                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3627397                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       411859                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       411859                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       508250                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       176469                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5544743                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4689500                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10918962                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       508250                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       176469                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5544743                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4689500                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10918962                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020695                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.042982                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.026439                       # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000004                       # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total     0.000004                       # miss rate for Writeback accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.680454                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.680454                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.833371                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.833371                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.252623                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.252623                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.101167                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.101167                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.256139                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.256139                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.537886                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.537886                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020695                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.042982                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.101167                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.255343                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.162697                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020695                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.042982                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.101167                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.255343                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.162697                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41881.251188                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41813.579433                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 41852.897310                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30070.610808                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30070.610808                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23421.706244                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23421.706244                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 539687.125000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 539687.125000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51886.460535                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51886.460535                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35329.808020                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35329.808020                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37119.451854                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37119.451854                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 59610.042296                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 59610.042296                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41881.251188                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41813.579433                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35329.808020                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40428.340327                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 38832.937035                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41881.251188                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41813.579433                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35329.808020                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40428.340327                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 38832.937035                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs         1044                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          348                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks       898326                       # number of writebacks
system.cpu1.l2cache.writebacks::total          898326                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            8                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          163                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          171                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        35372                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total        35372                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         4249                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         4249                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data           14                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total           14                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            8                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          163                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data        39621                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        39792                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            8                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          163                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data        39621                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        39792                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10510                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7422                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        17932                       # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks           13                       # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total           13                       # number of Writeback MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks        94515                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total        94515                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       663376                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       663376                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       142287                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       142287                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       158148                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       158148                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       232940                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       232940                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       560943                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       560943                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       924870                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       924870                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       221519                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       221519                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10510                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7422                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       560943                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1157810                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1736685                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10510                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7422                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       560943                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1157810                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       663376                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2400061                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         6826                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         6893                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         7171                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         7171                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        13997                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        14064                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    377290500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    262748000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    640038500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  36936048403                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  36936048403                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4692578493                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4692578493                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2913063996                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2913063996                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3975497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3975497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  10641963999                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  10641963999                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  16452350500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  16452350500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  28730541987                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  28730541987                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  11875773000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  11875773000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    377290500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    262748000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  16452350500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  39372505986                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  56464894986                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    377290500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    262748000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  16452350500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  39372505986                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  36936048403                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  93400943389                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8404500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    710244000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    718648500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    860387000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    860387000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8404500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1570631000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1579035500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020679                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.042058                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026189                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000004                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000004                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.680454                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.680454                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.833371                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.833371                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.219320                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.219320                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.101167                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.101167                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.254968                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.254968                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.537852                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.537852                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020679                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.042058                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.101167                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.246894                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.159052                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020679                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.042058                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.101167                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.246894                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.219807                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35692.532902                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55678.903673                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32979.671319                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32979.671319                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18419.859853                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18419.859853                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 496937.125000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496937.125000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.429720                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.429720                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29329.808020                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29329.808020                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31064.411200                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31064.411200                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53610.629337                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53610.629337                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29329.808020                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34006.016519                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32513.032004                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29329.808020                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34006.016519                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38916.070629                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104049.809552                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 104257.725228                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119981.453075                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119981.453075                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 112211.973994                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 112274.992890                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests     21930537                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11284587                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1296                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       520648                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       520636                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops           12                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq        828450                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     10092423                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         7171                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         7171                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      4200793                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      9135588                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       838070                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       423377                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       345989                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       462829                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           66                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1138657                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1069017                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5544744                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4688366                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       419379                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       411859                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     16633313                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16198816                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       385145                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1121131                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         34338405                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    354864624                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    515112392                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1411752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4066000                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         875454768                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5438478                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     27571945                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.031057                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.173474                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          26715663     96.89%     96.89% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            856270      3.11%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                12      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      27571945                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   14479823475                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    180399406                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   8321735869                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7455510168                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    208987874                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    613445865                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40368                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40368                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136681                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136681                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47892                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122826                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231192                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231192                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354098                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155933                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496803                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36369000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           565777885                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92876000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147888000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115577                       # number of replacements
system.iocache.tags.tagsinuse               11.305567                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115593                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9126912991000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.834509                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.471058                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.239657                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.466941                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706598                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040721                       # Number of tag accesses
system.iocache.tags.data_accesses             1040721                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8868                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8905                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8868                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8908                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8868                       # number of overall misses
system.iocache.overall_misses::total             8908                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1707562057                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1712757057                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13922427828                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13922427828                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1707562057                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1713126057                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1707562057                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1713126057                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8868                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8905                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8868                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8908                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8868                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8908                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 192553.231507                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 192336.558899                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130447.753429                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130447.753429                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 192553.231507                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 192313.208015                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 192553.231507                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 192313.208015                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         35527                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3511                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.118770                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8868                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8905                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8868                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8908                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8868                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8908                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1264162057                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1267507057                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8586027828                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8586027828                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1264162057                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1267726057                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1264162057                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1267726057                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142553.231507                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 142336.558899                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80447.753429                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80447.753429                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 142553.231507                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 142313.208015                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 142553.231507                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 142313.208015                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1523284                       # number of replacements
system.l2c.tags.tagsinuse                63784.617798                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5785768                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1584080                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.652447                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   17262.204967                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   288.051541                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   383.464514                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4972.263689                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    12806.585942                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17387.012671                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    85.287470                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker    93.857044                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2455.379438                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     4782.512624                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  3267.997898                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.263400                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.004395                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.005851                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.075871                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.195413                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.265305                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001301                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.001432                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.037466                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.072975                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.049866                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.973276                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10918                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          244                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        49634                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2         1058                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          384                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9467                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          241                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2538                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5035                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        41740                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.166595                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003723                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.757355                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 71725289                       # Number of tag accesses
system.l2c.tags.data_accesses                71725289                       # Number of data accesses
system.l2c.Writeback_hits::writebacks         2493194                       # number of Writeback hits
system.l2c.Writeback_hits::total              2493194                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           29135                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           32441                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               61576                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          6380                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          5628                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             12008                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           165668                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           160581                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               326249                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6589                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4357                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       618480                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       631164                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       297252                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5967                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4162                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       524459                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       533369                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       294077                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2919876                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6589                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4357                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              618480                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              796832                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       297252                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5967                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4162                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              524459                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              693950                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       294077                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3246125                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6589                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4357                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             618480                       # number of overall hits
system.l2c.overall_hits::cpu0.data             796832                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       297252                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5967                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4162                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             524459                       # number of overall hits
system.l2c.overall_hits::cpu1.data             693950                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       294077                       # number of overall hits
system.l2c.overall_hits::total                3246125                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         49689                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         45204                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             94893                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        10659                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         8662                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           19321                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         547046                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         101994                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             649040                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3253                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3182                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        67580                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       173763                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       345323                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1427                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1037                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        36484                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        93466                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       171017                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         896532                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker         3253                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         3182                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             67580                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            720809                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       345323                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1427                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1037                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             36484                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            195460                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       171017                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1545572                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         3253                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         3182                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            67580                       # number of overall misses
system.l2c.overall_misses::cpu0.data           720809                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       345323                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1427                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1037                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            36484                       # number of overall misses
system.l2c.overall_misses::cpu1.data           195460                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       171017                       # number of overall misses
system.l2c.overall_misses::total              1545572                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    823665000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    712158000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1535823000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data    169857000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data    128692500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    298549500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  97772317996                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  15251359498                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 113023677494                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    459886500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    447245500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   9268037502                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  25632017498                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  63422033653                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    210125000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    151697000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5011265500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  13524553500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  31614845146                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 149741706799                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    459886500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    447245500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   9268037502                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 123404335494                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  63422033653                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    210125000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    151697000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   5011265500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  28775912998                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  31614845146                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    262765384293                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    459886500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    447245500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   9268037502                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 123404335494                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  63422033653                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    210125000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    151697000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   5011265500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  28775912998                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  31614845146                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   262765384293                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks      2493194                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2493194                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        78824                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        77645                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          156469                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        17039                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        14290                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         31329                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       712714                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       262575                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           975289                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         9842                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7539                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       686060                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       804927                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       642575                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         7394                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5199                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       560943                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       626835                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       465094                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3816408                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         9842                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7539                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          686060                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1517641                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       642575                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         7394                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5199                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          560943                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          889410                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       465094                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4791697                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         9842                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7539                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         686060                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1517641                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       642575                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         7394                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5199                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         560943                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         889410                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       465094                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4791697                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.630379                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.582188                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.606465                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.625565                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.606158                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.616713                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.767553                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.388438                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.665485                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.330522                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.422072                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.098505                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.215874                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.537405                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.192994                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.199461                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.065040                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.149108                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.367704                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.234915                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.330522                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.422072                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.098505                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.474954                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.537405                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.192994                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.199461                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.065040                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.219764                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.367704                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.322552                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.330522                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.422072                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.098505                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.474954                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.537405                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.192994                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.199461                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.065040                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.219764                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.367704                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.322552                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16576.405241                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15754.313778                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 16184.787076                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15935.547425                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14857.134611                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 15452.072874                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 178727.781569                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149531.928329                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 174139.771808                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141373.040271                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140554.839723                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137141.720953                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 147511.366045                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 183660.033224                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 147249.474422                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 146284.474446                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137355.155685                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144700.249289                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 184863.757088                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 167023.270557                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141373.040271                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140554.839723                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 137141.720953                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 171202.545326                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 183660.033224                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 147249.474422                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 146284.474446                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 137355.155685                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 147221.492878                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 184863.757088                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 170011.739533                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141373.040271                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140554.839723                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 137141.720953                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 171202.545326                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 183660.033224                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 147249.474422                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 146284.474446                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 137355.155685                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 147221.492878                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 184863.757088                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 170011.739533                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             10627                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       95                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs    111.863158                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1190221                       # number of writebacks
system.l2c.writebacks::total                  1190221                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           97                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           21                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          189                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           20                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          327                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             97                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             21                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            189                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             20                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                327                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            97                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            21                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           189                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            20                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               327                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        49518                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        49518                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        49689                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        45204                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        94893                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10659                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8662                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        19321                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       547046                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       101994                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        649040                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3253                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3182                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        67483                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       173742                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       345323                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1427                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1037                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        36295                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        93446                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       171017                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       896205                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         3253                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         3182                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        67483                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       720788                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       345323                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1427                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1037                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        36295                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       195440                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       171017                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1545245                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         3253                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         3182                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        67483                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       720788                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       345323                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1427                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1037                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        36295                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       195440                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       171017                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1545245                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31951                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         6824                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        60136                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        31485                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         7171                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38656                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        63436                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        13995                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        98792                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   3656557006                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   3330209007                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   6986766013                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    815429503                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    662042995                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total   1477472498                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  92301857996                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  14231419498                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 106533277494                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    427356500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    415425500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   8580768502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  23891460998                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  59968803653                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    195855000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    141327000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   4625471500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  12587638500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  29904675146                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 140738782299                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    427356500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    415425500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   8580768502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 116193318994                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  59968803653                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    195855000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    141327000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   4625471500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  26819057998                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  29904675146                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 247272059793                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    427356500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    415425500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   8580768502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 116193318994                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  59968803653                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    195855000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    141327000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   4625471500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  26819057998                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  29904675146                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 247272059793                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2396727000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4940514000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7197500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    587373500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7931812000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4820729533                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    738465000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5559194533                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2396727000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9761243533                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7197500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1325838500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13491006533                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.630379                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.582188                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.606465                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.625565                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.606158                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.616713                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.767553                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.388438                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.665485                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.330522                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.422072                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.098363                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.215848                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.537405                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.192994                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.199461                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.064704                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.149076                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.367704                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.234829                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.330522                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.422072                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.098363                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.474940                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.537405                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.192994                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.199461                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.064704                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.219741                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.367704                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.322484                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.330522                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.422072                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.098363                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.474940                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.537405                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.192994                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.199461                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.064704                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.219741                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.367704                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.322484                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73588.862847                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73670.670892                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73627.833592                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76501.501360                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76430.731355                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76469.773718                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 168727.781569                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139531.928329                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 164139.771808                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127154.520427                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137511.142948                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127441.011159                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134704.947242                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 157038.604224                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127154.520427                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 161203.181787                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127441.011159                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137223.997124                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 160021.265102                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127154.520427                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 161203.181787                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127441.011159                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137223.997124                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 160021.265102                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154627.836374                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 86074.662954                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131897.898098                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153111.943243                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102979.361316                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 143811.944666                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153875.457674                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 94736.584494                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 136559.706586                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               60136                       # Transaction distribution
system.membus.trans_dist::ReadResp             965246                       # Transaction distribution
system.membus.trans_dist::WriteReq              38656                       # Transaction distribution
system.membus.trans_dist::WriteResp             38656                       # Transaction distribution
system.membus.trans_dist::Writeback           1296915                       # Transaction distribution
system.membus.trans_dist::CleanEvict           243951                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           452760                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         304384                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          121976                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            662340                       # Transaction distribution
system.membus.trans_dist::ReadExResp           641281                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        905110                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122826                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26816                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5450054                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5599774                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342030                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342030                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5941804                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155933                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        53632                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    174888448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    175098585                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7250496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7250496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               182349081                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           659296                       # Total snoops (count)
system.membus.snoop_fanout::samples           4073524                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4073524    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4073524                       # Request fanout histogram
system.membus.reqLayer0.occupancy            98143499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            22747469                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9016528809                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         8432717951                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          230475062                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     11519638                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      5862055                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      2048796                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         167370                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       156134                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        11236                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              60138                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4755206                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38656                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38656                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          3790142                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1500041                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          506577                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        316392                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         822969                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          115                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1127077                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1127077                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4702306                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9146865                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6326733                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              15473598                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    285949105                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    180962856                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              466911961                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3420267                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         13372960                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.331842                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.472656                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                8946480     66.90%     66.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                4415244     33.02%     99.92% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  11236      0.08%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           13372960                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8776402150                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2601544                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        5338662327                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3896618177                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   14407                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    7094                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------