path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.389857                       # Number of seconds simulated
sim_ticks                                47389857088000                       # Number of ticks simulated
final_tick                               47389857088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 145229                       # Simulator instruction rate (inst/s)
host_op_rate                                   170794                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7499087776                       # Simulator tick rate (ticks/s)
host_mem_usage                                 767912                       # Number of bytes of host memory used
host_seconds                                  6319.42                       # Real time elapsed on the host
sim_insts                                   917760909                       # Number of instructions simulated
sim_ops                                    1079317478                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       104896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        67648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3518240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         12875080                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     14592448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       209856                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       206272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3409696                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         12665040                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     18241216                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        447104                       # Number of bytes read from this memory
system.physmem.bytes_read::total             66337496                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3518240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3409696                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6927936                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     83736832                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          83757416                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1639                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1057                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             70925                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            201186                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       228007                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         3279                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         3223                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             53320                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            197904                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       285019                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6986                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1052545                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1308388                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1310962                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2213                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1427                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               74240                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              271684                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       307923                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          4428                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          4353                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               71950                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              267252                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       384918                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9435                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1399825                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          74240                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          71950                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             146190                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1766978                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1767412                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1766978                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2213                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1427                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              74240                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             272119                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       307923                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         4428                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         4353                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              71950                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             267252                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       384918                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9435                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3167237                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1052545                       # Number of read requests accepted
system.physmem.writeReqs                      1310962                       # Number of write requests accepted
system.physmem.readBursts                     1052545                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1310962                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 67342528                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     20352                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  83756608                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  66337496                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               83757416                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      318                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               66733                       # Per bank write bursts
system.physmem.perBankRdBursts::1               71928                       # Per bank write bursts
system.physmem.perBankRdBursts::2               60670                       # Per bank write bursts
system.physmem.perBankRdBursts::3               68962                       # Per bank write bursts
system.physmem.perBankRdBursts::4               64861                       # Per bank write bursts
system.physmem.perBankRdBursts::5               72347                       # Per bank write bursts
system.physmem.perBankRdBursts::6               66642                       # Per bank write bursts
system.physmem.perBankRdBursts::7               70254                       # Per bank write bursts
system.physmem.perBankRdBursts::8               57646                       # Per bank write bursts
system.physmem.perBankRdBursts::9               82139                       # Per bank write bursts
system.physmem.perBankRdBursts::10              57944                       # Per bank write bursts
system.physmem.perBankRdBursts::11              62634                       # Per bank write bursts
system.physmem.perBankRdBursts::12              58488                       # Per bank write bursts
system.physmem.perBankRdBursts::13              63067                       # Per bank write bursts
system.physmem.perBankRdBursts::14              63784                       # Per bank write bursts
system.physmem.perBankRdBursts::15              64128                       # Per bank write bursts
system.physmem.perBankWrBursts::0               82746                       # Per bank write bursts
system.physmem.perBankWrBursts::1               86394                       # Per bank write bursts
system.physmem.perBankWrBursts::2               79376                       # Per bank write bursts
system.physmem.perBankWrBursts::3               84859                       # Per bank write bursts
system.physmem.perBankWrBursts::4               81483                       # Per bank write bursts
system.physmem.perBankWrBursts::5               87954                       # Per bank write bursts
system.physmem.perBankWrBursts::6               81083                       # Per bank write bursts
system.physmem.perBankWrBursts::7               85604                       # Per bank write bursts
system.physmem.perBankWrBursts::8               78166                       # Per bank write bursts
system.physmem.perBankWrBursts::9               81607                       # Per bank write bursts
system.physmem.perBankWrBursts::10              78637                       # Per bank write bursts
system.physmem.perBankWrBursts::11              81487                       # Per bank write bursts
system.physmem.perBankWrBursts::12              76226                       # Per bank write bursts
system.physmem.perBankWrBursts::13              79682                       # Per bank write bursts
system.physmem.perBankWrBursts::14              80516                       # Per bank write bursts
system.physmem.perBankWrBursts::15              82877                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          67                       # Number of times write queue was full causing retry
system.physmem.totGap                    47389855480500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1031187                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1308388                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    475081                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    269839                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     74446                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     52901                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     38377                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     34235                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     31560                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     30053                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     26736                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      7334                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     3987                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2417                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1591                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1204                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      701                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      610                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      497                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      402                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      147                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    25192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    30313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    42202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    46715                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    53462                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    56984                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    62681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    68834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    74158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    77826                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    82266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    87664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    86481                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    90056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   101873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    89446                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    81226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    76109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                    12688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     9562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     8108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     6575                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     5525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     4656                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     3860                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     3225                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     2811                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     2313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     2109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1888                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1382                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      898                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      369                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      151                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1063862                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      142.028406                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      96.908483                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     188.947681                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         721844     67.85%     67.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       204911     19.26%     87.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        49859      4.69%     91.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        22222      2.09%     93.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        18303      1.72%     95.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        10788      1.01%     96.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         6944      0.65%     97.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         4476      0.42%     97.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        24515      2.30%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1063862                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         61379                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        17.142980                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       72.283129                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           61375     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           61379                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         61379                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        21.321576                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.114024                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       78.581580                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-127           61139     99.61%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-255           150      0.24%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-383            15      0.02%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-511            13      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-639            10      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-767             5      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::768-895             6      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::896-1023            2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1024-1151            3      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1152-1279            3      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1280-1407            1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1408-1535            3      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1536-1663            1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1664-1791            2      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1792-1919            3      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1920-2047            1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2048-2175            1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2176-2303            2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2432-2559            1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2560-2687            2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2688-2815            1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2944-3071            1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3072-3199            1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3200-3327            1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3584-3711            1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3840-3967            2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3968-4095            3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4224-4351            3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4736-4863            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5760-5887            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6528-6655            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           61379                       # Writes before turning the bus around for reads
system.physmem.totQLat                    45835808351                       # Total ticks spent queuing
system.physmem.totMemAccLat               65565064601                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5261135000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       43560.76                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  62310.76                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.42                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.77                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.40                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.77                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.24                       # Average write queue length when enqueuing
system.physmem.readRowHits                     793650                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    503408                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.43                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  38.47                       # Row buffer hit rate for writes
system.physmem.avgGap                     20050651.63                       # Average gap between requests
system.physmem.pageHitRate                      54.94                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 4147801560                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2263185375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4230649800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4338353520                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3095274664560                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1171144383615                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27406590797250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31687989835680                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.666167                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45593219352262                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1582451260000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    214185512238                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3894995160                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2125245375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3976658400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4142003040                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3095274664560                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1168941164895                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27408523445250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31686878176680                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.642709                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45596430811261                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1582451260000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    210971448239                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           556                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          368                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           23                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           11                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              134064980                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         88919550                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          6498041                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            94483455                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               58137091                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            61.531504                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               17960348                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            169436                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4224209                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           2670261                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses         1553948                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted       396228                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   535513                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               535513                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        11169                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        82857                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       246420                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       289093                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2351.355792                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 14312.568858                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       286889     99.24%     99.24% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         1266      0.44%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          685      0.24%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          138      0.05%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679           30      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           61      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751           19      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       289093                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       272039                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 19613.296255                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 17220.717357                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 14703.962270                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       270425     99.41%     99.41% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          632      0.23%     99.64% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          733      0.27%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           61      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          123      0.05%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           32      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           15      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::720896-786431            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       272039                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 510275836160                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.563308                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.548439                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 509171724160     99.78%     99.78% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3    565791000      0.11%     99.89% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5    239447000      0.05%     99.94% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7    119430500      0.02%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9     85504500      0.02%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11     55232500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13     15487000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15     22822000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       392500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19         5000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 510275836160                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        82857     88.12%     88.12% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        11169     11.88%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        94026                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       535513                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       535513                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        94026                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        94026                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       629539                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    97385635                       # DTB read hits
system.cpu0.dtb.read_misses                    369085                       # DTB read misses
system.cpu0.dtb.write_hits                   80705124                       # DTB write hits
system.cpu0.dtb.write_misses                   166428                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   34685                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      254                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  6533                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    38231                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                97754720                       # DTB read accesses
system.cpu0.dtb.write_accesses               80871552                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        178090759                       # DTB hits
system.cpu0.dtb.misses                         535513                       # DTB misses
system.cpu0.dtb.accesses                    178626272                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    79425                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                79425                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          951                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        57153                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore         9771                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        69654                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1061.827031                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  8997.758844                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        69210     99.36%     99.36% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          270      0.39%     99.75% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303            5      0.01%     99.76% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071           37      0.05%     99.81% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839           88      0.13%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607           29      0.04%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        69654                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        67875                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 24239.233886                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 22083.564087                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 17866.594665                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        67243     99.07%     99.07% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071           67      0.10%     99.17% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          462      0.68%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           35      0.05%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           34      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           16      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           11      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        67875                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 394215499668                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.849337                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.357871                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    59413822884     15.07%     15.07% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   334782784784     84.92%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       17900000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3         873000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         119000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 394215499668                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        57153     98.36%     98.36% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          951      1.64%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        58104                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        79425                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        79425                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        58104                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        58104                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       137529                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   209912640                       # ITB inst hits
system.cpu0.itb.inst_misses                     79425                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   24340                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   193348                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               209992065                       # ITB inst accesses
system.cpu0.itb.hits                        209912640                       # DTB hits
system.cpu0.itb.misses                          79425                       # DTB misses
system.cpu0.itb.accesses                    209992065                       # DTB accesses
system.cpu0.numCycles                       756853118                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          86258252                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     591637469                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  134064980                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          78767700                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    626674135                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               13960220                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   1708629                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles              309159                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      5578419                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       726023                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles       793198                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                209720229                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              1626111                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  25986                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         729027925                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.950211                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.213293                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               397179270     54.48%     54.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1               129433697     17.75%     72.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                43948284      6.03%     78.26% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3               158466674     21.74%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           729027925                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.177135                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.781707                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               101905293                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            364135087                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                222287988                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             35712800                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               4986757                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            19110947                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              2030964                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             613952929                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts             22693715                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               4986757                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               135896080                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               55064795                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     234892830                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                223531264                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             74656199                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             597354053                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              5967968                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents             10658303                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                242676                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                277310                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              41417072                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents           10715                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          569274330                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            919727485                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       705445437                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           845170                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            513762865                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                55511456                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          14761622                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      12913765                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 71848393                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            97600013                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           83873039                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          8761707                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         7520310                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 575959343                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           14902678                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                580046321                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued          2619697                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       52147933                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     33732364                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        256005                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    729027925                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.795643                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.062696                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          413752637     56.75%     56.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1          130387752     17.89%     74.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2          112730807     15.46%     90.10% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           64434367      8.84%     98.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            7717956      1.06%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5               4406      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      729027925                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               60438369     45.47%     45.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 47042      0.04%     45.50% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                  17968      0.01%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc              10      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead              34488153     25.95%     71.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite             37935532     28.54%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass               10      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            396224561     68.31%     68.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1355740      0.23%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                69556      0.01%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  5      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt             26      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         78264      0.01%     68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           100394563     17.31%     85.88% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           81923573     14.12%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             580046321                       # Type of FU issued
system.cpu0.iq.rate                          0.766392                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                  132927074                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.229166                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        2023285471                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        642599747                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    563357563                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1381865                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            550084                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       513487                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             712117129                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 856256                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         2617003                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     11923389                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        15941                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       140828                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      5327299                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2590097                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      4396592                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               4986757                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                6158595                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              2729815                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          590987234                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             97600013                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            83873039                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          12685897                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 60837                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              2608142                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        140828                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       1838258                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      2998999                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             4837257                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            572331002                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             97377740                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          7191247                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       125213                       # number of nop insts executed
system.cpu0.iew.exec_refs                   178083928                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               107921948                       # Number of branches executed
system.cpu0.iew.exec_stores                  80706188                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.756198                       # Inst execution rate
system.cpu0.iew.wb_sent                     564585754                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    563871050                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                273627354                       # num instructions producing a value
system.cpu0.iew.wb_consumers                449179775                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.745020                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.609171                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       45416795                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       14646672                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4504688                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    720395645                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.747803                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.555225                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    485771326     67.43%     67.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1    120512789     16.73%     84.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     52399936      7.27%     91.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     17702861      2.46%     93.89% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     12776683      1.77%     95.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      8497825      1.18%     96.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      5820958      0.81%     97.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3534904      0.49%     98.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     13378363      1.86%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    720395645                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           458462253                       # Number of instructions committed
system.cpu0.commit.committedOps             538714081                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     164222361                       # Number of memory references committed
system.cpu0.commit.loads                     85676622                       # Number of loads committed
system.cpu0.commit.membars                    3641024                       # Number of memory barriers committed
system.cpu0.commit.branches                 102649552                       # Number of branches committed
system.cpu0.commit.fp_insts                    504968                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                494164906                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            13432281                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       373237846     69.28%     69.28% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1127454      0.21%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           54738      0.01%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        71640      0.01%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       85676622     15.90%     85.42% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      78545739     14.58%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        538714081                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             13378363                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1287287379                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1176858570                       # The number of ROB writes
system.cpu0.timesIdled                         934729                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       27825193                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 94022861092                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  458462253                       # Number of Instructions Simulated
system.cpu0.committedOps                    538714081                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.650852                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.650852                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.605748                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.605748                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               675960762                       # number of integer regfile reads
system.cpu0.int_regfile_writes              401183302                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   830771                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  428332                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                124727892                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               125481667                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1276105833                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              14867290                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements          5765600                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          490.322435                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          152640999                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5766111                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            26.472088                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       2962390000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   490.322435                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.957661                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.957661                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        340447274                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       340447274                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     79408561                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       79408561                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     68334031                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      68334031                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       200433                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       200433                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       174121                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       174121                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1831958                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1831958                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1849907                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1849907                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    147742592                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       147742592                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    147943025                       # number of overall hits
system.cpu0.dcache.overall_hits::total      147943025                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      6387707                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      6387707                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      7192656                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      7192656                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       686822                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       686822                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       795953                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       795953                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       241297                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       241297                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       189319                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       189319                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     13580363                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      13580363                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     14267185                       # number of overall misses
system.cpu0.dcache.overall_misses::total     14267185                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 102145338500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 102145338500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 163649518808                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 163649518808                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  49996037023                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  49996037023                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3671046500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   3671046500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5304166500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   5304166500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5694500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5694500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 265794857308                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 265794857308                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 265794857308                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 265794857308                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     85796268                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     85796268                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     75526687                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     75526687                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       887255                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       887255                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       970074                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       970074                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2073255                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2073255                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2039226                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2039226                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    161322955                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    161322955                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    162210210                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    162210210                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074452                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.074452                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.095233                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.095233                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.774098                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.774098                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.820508                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.820508                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.116386                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.116386                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.092839                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.092839                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084181                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.084181                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.087955                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.087955                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15990.924208                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15990.924208                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 22752.307188                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 22752.307188                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 62812.800533                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 62812.800533                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.809123                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.809123                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28017.084920                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28017.084920                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19571.999460                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19571.999460                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18629.803799                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18629.803799                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     15450587                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets     24201430                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           734789                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         699058                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.027243                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    34.620060                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      5765616                       # number of writebacks
system.cpu0.dcache.writebacks::total          5765616                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3289806                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      3289806                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5763001                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      5763001                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4255                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         4255                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       124637                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       124637                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      9052807                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      9052807                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      9052807                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      9052807                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3097901                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3097901                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1429655                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1429655                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       679876                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       679876                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       791698                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       791698                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       116660                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       116660                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       189313                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       189313                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4527556                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4527556                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5207432                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5207432                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        19295                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        19295                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        20724                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        20724                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        40019                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40019                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  47331591500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  47331591500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  38044472455                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  38044472455                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16657786000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16657786000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  48937488023                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  48937488023                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1685431500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1685431500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5114922500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5114922500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5625500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5625500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  85376063955                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  85376063955                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 102033849955                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 102033849955                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3789852000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3789852000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3941977500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3941977500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7731829500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7731829500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036108                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036108                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018929                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018929                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.766269                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.766269                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.816121                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.816121                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056269                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056269                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.092836                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.092836                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028065                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028065                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032103                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032103                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15278.600414                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15278.600414                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26610.946316                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26610.946316                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24501.211986                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24501.211986                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61813.327838                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61813.327838                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14447.381279                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14447.381279                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27018.337357                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27018.337357                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18856.986850                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18856.986850                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19593.890032                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19593.890032                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196416.273646                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196416.273646                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 190213.158657                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190213.158657                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 193203.965616                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193203.965616                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          5849403                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.943926                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          203506939                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5849915                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            34.788016                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      18014203000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.943926                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999890                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999890                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          457                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        425234482                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       425234482                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    203506939                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      203506939                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    203506939                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       203506939                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    203506939                       # number of overall hits
system.cpu0.icache.overall_hits::total      203506939                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6185325                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      6185325                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6185325                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       6185325                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6185325                       # number of overall misses
system.cpu0.icache.overall_misses::total      6185325                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  68820233655                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  68820233655                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  68820233655                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  68820233655                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  68820233655                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  68820233655                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    209692264                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    209692264                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    209692264                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    209692264                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    209692264                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    209692264                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029497                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.029497                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029497                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.029497                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029497                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.029497                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11126.373094                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11126.373094                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11126.373094                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11126.373094                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11126.373094                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11126.373094                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs     10317197                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1776                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           708038                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             15                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.571530                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets   118.400000                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      5849403                       # number of writebacks
system.cpu0.icache.writebacks::total          5849403                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       335371                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       335371                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       335371                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       335371                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       335371                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       335371                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5849954                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      5849954                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      5849954                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      5849954                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      5849954                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      5849954                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  62003791719                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  62003791719                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  62003791719                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  62003791719                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  62003791719                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  62003791719                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2939780498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2939780498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2939780498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2939780498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027898                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027898                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027898                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.027898                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027898                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.027898                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10599.022098                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10599.022098                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10599.022098                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10599.022098                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10599.022098                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10599.022098                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.236651                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.236651                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7728604                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7739029                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         9391                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1009379                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2564693                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16115.455050                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          16793989                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2580455                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.508150                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      3423391000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15189.817195                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    51.994619                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    35.520086                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data     0.176107                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   837.947042                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.927113                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003173                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.002168                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.000011                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.051144                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.983609                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1242                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           79                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14441                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           78                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          110                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          653                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          401                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           26                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1001                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5348                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4520                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3402                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.075806                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004822                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.881409                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       398023302                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      398023302                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       546484                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       178619                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        725103                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3848803                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3848803                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      7764047                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      7764047                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          499                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total          499                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            5                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total            5                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       861581                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       861581                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5300527                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      5300527                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2904826                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2904826                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       194350                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       194350                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       546484                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       178619                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      5300527                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3766407                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        9792037                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       546484                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       178619                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      5300527                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3766407                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       9792037                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11083                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7410                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        18493                       # number of ReadReq misses
system.cpu0.l2cache.WritebackDirty_misses::writebacks            1                       # number of WritebackDirty misses
system.cpu0.l2cache.WritebackDirty_misses::total            1                       # number of WritebackDirty misses
system.cpu0.l2cache.WritebackClean_misses::writebacks            2                       # number of WritebackClean misses
system.cpu0.l2cache.WritebackClean_misses::total            2                       # number of WritebackClean misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       259441                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       259441                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       189304                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       189304                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       319873                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       319873                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       549397                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       549397                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       986020                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       986020                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       595026                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       595026                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        11083                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7410                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       549397                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1305893                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1873783                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11083                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7410                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       549397                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1305893                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1873783                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    482796500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    312182000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    794978500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3412861500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   3412861500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1849978000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1849978000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      5522000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      5522000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  20457541498                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  20457541498                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  21120469998                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  21120469998                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  40452425974                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  40452425974                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    524579500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    524579500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    482796500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    312182000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  21120469998                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  60909967472                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  82825415970                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    482796500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    312182000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  21120469998                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  60909967472                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  82825415970                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       557567                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       186029                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       743596                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3848804                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3848804                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      7764049                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      7764049                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       259940                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       259940                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       189309                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       189309                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1181454                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1181454                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5849924                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      5849924                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3890846                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3890846                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       789376                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       789376                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       557567                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       186029                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5849924                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5072300                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     11665820                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       557567                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       186029                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5849924                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5072300                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     11665820                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.019877                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.039832                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.024870                       # miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000000                       # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000000                       # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998080                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998080                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999974                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999974                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.270745                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.270745                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.093915                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.093915                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.253420                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.253420                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.753793                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.753793                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.019877                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.039832                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.093915                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.257456                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.160622                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.019877                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.039832                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.093915                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.257456                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.160622                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 43561.896598                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42129.824561                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 42988.076570                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13154.672931                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13154.672931                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9772.524616                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9772.524616                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data      1380500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1380500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63955.199401                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63955.199401                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38443.002051                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38443.002051                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41025.969021                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41025.969021                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   881.607694                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   881.607694                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 43561.896598                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42129.824561                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38443.002051                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46642.387601                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 44202.245388                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 43561.896598                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42129.824561                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38443.002051                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46642.387601                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 44202.245388                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          731                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               8                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    91.375000                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.unused_prefetches           42139                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks      1615717                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1615717                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            6                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker           11                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        41013                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total        41013                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            5                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5478                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5478                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           13                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total           13                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            6                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker           11                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            5                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        46491                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        46513                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            6                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker           11                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            5                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        46491                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        46513                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        11077                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7399                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        18476                       # number of ReadReq MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            2                       # number of WritebackClean MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::total            2                       # number of WritebackClean MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       765922                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       765922                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       259441                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       259441                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       189304                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       189304                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       278860                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       278860                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       549392                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       549392                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       980542                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       980542                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       595013                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       595013                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        11077                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7399                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       549392                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1259402                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1827270                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        11077                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7399                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       549392                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1259402                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       765922                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2593192                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        19295                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40588                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        20724                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        20724                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        40019                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        61312                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    416228500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    267583000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    683811500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  48317121571                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  48317121571                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7648488996                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7648488996                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3692133999                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3692133999                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      5108000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5108000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  16036130498                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  16036130498                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17824036498                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17824036498                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  34158749978                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  34158749978                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  42060830499                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  42060830499                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    416228500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    267583000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17824036498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  50194880476                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  68702728474                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    416228500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    267583000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17824036498                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  50194880476                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  48317121571                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 117019850045                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780082000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3635082000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6415164000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3780809967                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3780809967                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   2780082000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7415891967                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10195973967                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.019867                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.039773                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.024847                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998080                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998080                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999974                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999974                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.236031                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.236031                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.093914                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.093914                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.252013                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.252013                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.753776                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.753776                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.019867                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.039773                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.093914                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248290                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.156635                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.019867                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.039773                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.093914                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248290                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.222290                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37010.797792                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63083.605865                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63083.605865                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29480.648764                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29480.648764                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19503.729446                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19503.729446                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data      1277000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1277000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57506.026314                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57506.026314                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32443.203574                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32443.203574                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 34836.600552                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34836.600552                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70688.926963                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70688.926963                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32443.203574                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39856.122569                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37598.564237                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32443.203574                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39856.122569                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63083.605865                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45125.794791                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188395.024618                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158055.681482                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182436.304140                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182436.304140                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185309.277268                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 166296.548261                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests     24114479                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12402894                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2291                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops      1959388                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1958967                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          421                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        868302                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     10703945                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        20725                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        20724                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5471023                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      7766214                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2549883                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       981532                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       467602                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       343874                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       514595                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           72                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          137                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1212904                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1189199                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5849954                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4880551                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       848509                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       789376                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     17591867                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18635587                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       390565                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1180743                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         37798762                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    749097616                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    700307787                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1488232                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4460536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1455354171                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    6848442                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     19646181                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.117106                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.321630                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          17346012     88.29%     88.29% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           2299647     11.71%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               522      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      19646181                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   23957915414                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    186819649                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   8802550782                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8265265885                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    204815934                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    623887061                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              135174598                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         89157012                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          6771553                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            95119508                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               59219614                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            62.258116                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               18509493                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            199065                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        4260619                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           2645570                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses         1615049                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted       400784                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   620331                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               620331                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        13694                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        99863                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       301286                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       319045                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2609.283957                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 15339.812797                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       316072     99.07%     99.07% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1597      0.50%     99.57% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607         1113      0.35%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143          132      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679           45      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           65      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751           13      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       319045                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       336255                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 21304.924834                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17913.652779                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 23319.449537                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       331614     98.62%     98.62% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1015      0.30%     98.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607         2524      0.75%     99.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143          218      0.06%     99.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679          559      0.17%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215          132      0.04%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751          112      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           49      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823           16      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       336255                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 493108416476                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.613633                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.555238                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 491595088976     99.69%     99.69% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3    828838000      0.17%     99.86% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5    323227000      0.07%     99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7    140968000      0.03%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9    113706500      0.02%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11     58901000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13     19970500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15     26949000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       748000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19        19500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 493108416476                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        99864     87.94%     87.94% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        13694     12.06%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       113558                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       620331                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       620331                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       113558                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       113558                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       733889                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    99541236                       # DTB read hits
system.cpu1.dtb.read_misses                    446261                       # DTB read misses
system.cpu1.dtb.write_hits                   80566614                       # DTB write hits
system.cpu1.dtb.write_misses                   174070                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   43247                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      634                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  6731                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    41159                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                99987497                       # DTB read accesses
system.cpu1.dtb.write_accesses               80740684                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        180107850                       # DTB hits
system.cpu1.dtb.misses                         620331                       # DTB misses
system.cpu1.dtb.accesses                    180728181                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    88034                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                88034                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1080                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        62024                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore        10531                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        77503                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1737.752087                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 13376.771603                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767        76531     98.75%     98.75% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535          407      0.53%     99.27% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303           54      0.07%     99.34% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071          157      0.20%     99.54% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839          274      0.35%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607           44      0.06%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        77503                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        73635                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28077.836627                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23325.571005                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 31326.629409                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        71135     96.60%     96.60% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          154      0.21%     96.81% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607         1986      2.70%     99.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143          113      0.15%     99.66% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679          137      0.19%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           53      0.07%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           44      0.06%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        73635                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 428680982536                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.877576                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.328123                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    52527553308     12.25%     12.25% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   376108944728     87.74%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       42347500      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        2103500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4          33500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 428680982536                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        62024     98.29%     98.29% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         1080      1.71%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        63104                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        88034                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        88034                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        63104                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        63104                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       151138                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   212987962                       # ITB inst hits
system.cpu1.itb.inst_misses                     88034                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   31450                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   212403                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               213075996                       # ITB inst accesses
system.cpu1.itb.hits                        212987962                       # DTB hits
system.cpu1.itb.misses                          88034                       # DTB misses
system.cpu1.itb.accesses                    213075996                       # DTB accesses
system.cpu1.numCycles                       763303942                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          89198965                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     599138491                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  135174598                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          80374677                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    631697152                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               14629606                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   2135822                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles              325301                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles      6190061                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       869593                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles       862105                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                212754259                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              1709590                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  28554                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         738593802                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.951348                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.213932                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               402298959     54.47%     54.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1               130678569     17.69%     72.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                44867308      6.07%     78.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3               160748966     21.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           738593802                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.177091                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.784928                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles               106478117                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            366845169                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                222515957                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             37512815                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               5241744                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            19111386                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              2112679                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             619567000                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts             23338360                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               5241744                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               141946273                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               54617946                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     243861784                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                224134357                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             68791698                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             602126263                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts              6118576                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents             11056239                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                380631                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                940722                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              33286587                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents           12083                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          573060902                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            928019832                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       710062229                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           649328                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            514926448                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                58134448                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          16118585                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      14068970                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 75560239                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            99853363                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           83838519                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          9473424                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         8115334                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 579120615                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           16293769                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                584059770                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued          2714782                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       54810980                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     35376701                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        290425                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    738593802                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.790773                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.055961                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          417929764     56.58%     56.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1          136913052     18.54%     75.12% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2          111746112     15.13%     90.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           64370034      8.72%     98.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            7629808      1.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               5032      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      738593802                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu               58567749     44.20%     44.20% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 70680      0.05%     44.25% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                  16113      0.01%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc              26      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead              36085591     27.23%     71.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite             37772354     28.50%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               36      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            397950619     68.14%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1394287      0.24%     68.37% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                80723      0.01%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  4      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         45828      0.01%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead           102773744     17.60%     85.99% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           81814529     14.01%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             584059770                       # Type of FU issued
system.cpu1.iq.rate                          0.765173                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                  132512513                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.226882                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        2040871763                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        649951389                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    566663887                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1068872                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            423239                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       394625                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             715907019                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 665228                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         2663748                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     12784321                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        18121                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       150654                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      5561892                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      2706765                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      4288761                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               5241744                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                8152179                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              2696224                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          595550479                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             99853363                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            83838519                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          13801566                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 59598                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              2567849                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        150654                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       1960671                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      3092522                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             5053193                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            576018607                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             99536730                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          7427921                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       136095                       # number of nop insts executed
system.cpu1.iew.exec_refs                   180100552                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               107831822                       # Number of branches executed
system.cpu1.iew.exec_stores                  80563822                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.754639                       # Inst execution rate
system.cpu1.iew.wb_sent                     567845555                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    567058512                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                275064587                       # num instructions producing a value
system.cpu1.iew.wb_consumers                450436874                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.742900                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.610662                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       47911948                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       16003344                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4698494                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    729478017                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.741083                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.544204                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    491334549     67.35%     67.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1    124605119     17.08%     84.44% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     52434637      7.19%     91.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     17448264      2.39%     94.02% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     12346698      1.69%     95.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      8646744      1.19%     96.89% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5821113      0.80%     97.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3490122      0.48%     98.17% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     13350771      1.83%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    729478017                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           459298656                       # Number of instructions committed
system.cpu1.commit.committedOps             540603397                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     165345668                       # Number of memory references committed
system.cpu1.commit.loads                     87069041                       # Number of loads committed
system.cpu1.commit.membars                    3858315                       # Number of memory barriers committed
system.cpu1.commit.branches                 102318506                       # Number of branches committed
system.cpu1.commit.fp_insts                    386565                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                496515316                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            13693042                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       374009133     69.18%     69.18% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult        1144857      0.21%     69.40% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           64258      0.01%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        39481      0.01%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       87069041     16.11%     85.52% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      78276627     14.48%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        540603397                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             13350771                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1300306905                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1186107059                       # The number of ROB writes
system.cpu1.timesIdled                        1002683                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       24710140                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 94016410262                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  459298656                       # Number of Instructions Simulated
system.cpu1.committedOps                    540603397                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.661890                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.661890                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.601724                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.601724                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               679475596                       # number of integer regfile reads
system.cpu1.int_regfile_writes              404035591                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   636627                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  333028                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                123323505                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               123972693                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1293234240                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              15956756                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements          5664060                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          461.921265                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          153938367                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5664570                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            27.175649                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8482615799500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   461.921265                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.902190                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.902190                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          393                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        343399100                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       343399100                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     81011302                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       81011302                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     68259476                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      68259476                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       190553                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       190553                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       137870                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       137870                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1767079                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1767079                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1811409                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1811409                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    149270778                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       149270778                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    149461331                       # number of overall hits
system.cpu1.dcache.overall_hits::total      149461331                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      6609494                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      6609494                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      7403019                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      7403019                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       691160                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       691160                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       462153                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       462153                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       284407                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       284407                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       195281                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       195281                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data     14012513                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total      14012513                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data     14703673                       # number of overall misses
system.cpu1.dcache.overall_misses::total     14703673                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 113682780000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 113682780000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 163432974267                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 163432974267                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  19652724076                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  19652724076                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4573915000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   4573915000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5496232500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   5496232500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5776500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5776500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 277115754267                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 277115754267                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 277115754267                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 277115754267                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     87620796                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     87620796                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     75662495                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     75662495                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       881713                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       881713                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       600023                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       600023                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2051486                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      2051486                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2006690                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      2006690                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    163283291                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    163283291                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    164165004                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    164165004                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.075433                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.075433                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.097843                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.097843                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.783883                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.783883                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.770225                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.770225                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.138635                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.138635                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097315                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097315                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.085817                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.085817                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.089566                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.089566                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17199.921809                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 17199.921809                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22076.530435                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22076.530435                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42524.281084                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42524.281084                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16082.287004                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16082.287004                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28145.249666                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28145.249666                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19776.306667                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19776.306667                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18846.702743                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18846.702743                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs      5374733                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets     26726963                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs           381404                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets         750366                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    14.091968                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    35.618569                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      5664164                       # number of writebacks
system.cpu1.dcache.writebacks::total          5664164                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3334691                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total      3334691                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5984035                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      5984035                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3399                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total         3399                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       145205                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total       145205                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      9318726                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      9318726                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      9318726                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      9318726                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3274803                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      3274803                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1418984                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1418984                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       691046                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       691046                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       458754                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       458754                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       139202                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       139202                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       195277                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       195277                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4693787                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4693787                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5384833                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5384833                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        19232                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        19232                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        17726                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        17726                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        36958                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        36958                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  51262951500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  51262951500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  34883587324                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  34883587324                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16764876500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16764876500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  19026160076                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  19026160076                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   2027619500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   2027619500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5301023500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5301023500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      5708500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      5708500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  86146538824                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  86146538824                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 102911415324                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 102911415324                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3119149500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3119149500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2971127000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2971127000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   6090276500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   6090276500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037375                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037375                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018754                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018754                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.783754                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.783754                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.764561                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.764561                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067854                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067854                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097313                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097313                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028746                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.028746                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032801                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.032801                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15653.751233                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15653.751233                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24583.495884                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24583.495884                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24260.145490                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24260.145490                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41473.556800                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41473.556800                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14566.022758                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14566.022758                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27146.174409                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27146.174409                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18353.312331                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18353.312331                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19111.347617                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19111.347617                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162185.394135                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162185.394135                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167614.069728                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167614.069728                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164789.125494                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 164789.125494                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          6084021                       # number of replacements
system.cpu1.icache.tags.tagsinuse          501.481326                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          206310871                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          6084533                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            33.907429                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8522353869000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.481326                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979456                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.979456                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          345                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        431579068                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       431579068                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    206310871                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      206310871                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    206310871                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       206310871                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    206310871                       # number of overall hits
system.cpu1.icache.overall_hits::total      206310871                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      6436378                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      6436378                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      6436378                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       6436378                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      6436378                       # number of overall misses
system.cpu1.icache.overall_misses::total      6436378                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  72269477183                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  72269477183                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  72269477183                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  72269477183                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  72269477183                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  72269477183                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    212747249                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    212747249                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    212747249                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    212747249                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    212747249                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    212747249                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030254                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.030254                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030254                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.030254                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030254                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.030254                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11228.283544                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 11228.283544                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11228.283544                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 11228.283544                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11228.283544                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 11228.283544                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs     11099833                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          317                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs           762485                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              4                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.557444                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets    79.250000                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks      6084021                       # number of writebacks
system.cpu1.icache.writebacks::total          6084021                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       351808                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total       351808                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst       351808                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total       351808                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst       351808                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total       351808                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      6084570                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      6084570                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      6084570                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      6084570                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      6084570                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      6084570                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  65151824817                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  65151824817                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  65151824817                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  65151824817                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  65151824817                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  65151824817                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9154498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9154498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9154498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      9154498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028600                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028600                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028600                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.028600                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028600                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.028600                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10707.712265                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10707.712265                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10707.712265                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10707.712265                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10707.712265                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10707.712265                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136634.298507                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136634.298507                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136634.298507                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136634.298507                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7756566                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7763412                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit         6220                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       969756                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2332043                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13399.306231                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          17632836                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2347889                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            7.510081                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9842790935000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12578.549266                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    73.835699                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    75.403592                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   671.517674                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.767734                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004507                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004602                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.040986                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.817829                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1168                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           87                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14591                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          213                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          557                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          388                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           63                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1235                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4922                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4629                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3692                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.071289                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005310                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.890564                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       403369890                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      403369890                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       629324                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       196368                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        825692                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3534370                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3534370                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      8212493                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      8212493                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          814                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total          814                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       892249                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       892249                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5494357                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      5494357                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3102678                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      3102678                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       175982                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       175982                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       629324                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       196368                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      5494357                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3994927                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total       10314976                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       629324                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       196368                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      5494357                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3994927                       # number of overall hits
system.cpu1.l2cache.overall_hits::total      10314976                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        13918                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10528                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        24446                       # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks            2                       # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total            2                       # number of WritebackDirty misses
system.cpu1.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
system.cpu1.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       231959                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       231959                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       195268                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       195268                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            9                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            9                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       301055                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       301055                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       590167                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       590167                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       999846                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       999846                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       280900                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       280900                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        13918                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker        10528                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       590167                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1300901                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1915514                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        13918                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker        10528                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       590167                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1300901                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1915514                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    754019500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    658882500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1412902000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3524402500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   3524402500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1953633500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1953633500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      5605499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      5605499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  17593545499                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  17593545499                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  22728280000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  22728280000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  43184825986                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  43184825986                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    414465000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    414465000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    754019500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    658882500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  22728280000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  60778371485                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  84919553485                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    754019500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    658882500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  22728280000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  60778371485                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  84919553485                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       643242                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       206896                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       850138                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3534372                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3534372                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      8212494                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      8212494                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       232773                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       232773                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       195268                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       195268                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            9                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            9                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1193304                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1193304                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      6084524                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      6084524                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4102524                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      4102524                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       456882                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       456882                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       643242                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       206896                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      6084524                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      5295828                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     12230490                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       643242                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       206896                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      6084524                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      5295828                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     12230490                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021637                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.050885                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.028755                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.996503                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.996503                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.252287                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.252287                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.096995                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.096995                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.243715                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.243715                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.614820                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.614820                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021637                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050885                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.096995                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.245646                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.156618                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021637                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050885                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.096995                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.245646                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.156618                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 54175.851415                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62583.824088                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 57796.858382                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15194.075246                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15194.075246                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10004.883033                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10004.883033                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 622833.222222                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 622833.222222                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58439.638933                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58439.638933                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38511.607731                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38511.607731                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43191.477474                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43191.477474                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1475.489498                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1475.489498                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 54175.851415                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62583.824088                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38511.607731                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 46720.212749                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 44332.515181                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 54175.851415                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62583.824088                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38511.607731                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 46720.212749                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 44332.515181                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs         1668                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs              18                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    92.666667                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.unused_prefetches           46928                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks      1248737                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1248737                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            4                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            8                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        53310                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total        53310                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         6042                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         6042                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            6                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            6                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            8                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            2                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data        59352                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        59366                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            4                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            8                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            2                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data        59352                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        59366                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        13914                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10520                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        24434                       # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            2                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::total            2                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       810022                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       810022                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       231959                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       231959                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       195268                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       195268                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            9                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            9                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       247745                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       247745                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       590165                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       590165                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       993804                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       993804                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       280894                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       280894                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        13914                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10520                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       590165                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1241549                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1856148                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        13914                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        10520                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       590165                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1241549                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       810022                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2666170                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        19232                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        19299                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        17726                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        17726                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        36958                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        37025                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    670350500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    595616000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1265966500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  58037263327                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  58037263327                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   7346311996                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   7346311996                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3833341496                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3833341496                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      5197499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5197499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  12807729999                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  12807729999                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  19187264000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  19187264000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  36825734486                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  36825734486                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  14981372997                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  14981372997                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    670350500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    595616000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  19187264000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  49633464485                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  70086694985                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    670350500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    595616000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  19187264000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  49633464485                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  58037263327                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 128123958312                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8651000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2965138000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2973789000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2838108000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2838108000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8651000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5803246000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5811897000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021631                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050847                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.028741                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.996503                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.996503                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.207613                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.207613                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.096994                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.096994                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.242242                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.242242                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.614806                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.614806                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021631                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050847                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.096994                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234439                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.151764                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021631                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050847                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.096994                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234439                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.217994                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 51811.676353                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 71648.996357                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 71648.996357                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31670.734897                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31670.734897                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19631.181228                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19631.181228                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 577499.888889                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 577499.888889                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 51697.229002                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 51697.229002                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32511.694187                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32511.694187                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37055.329306                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37055.329306                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53334.613758                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53334.613758                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32511.694187                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 39977.048417                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 37759.216929                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32511.694187                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 39977.048417                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 71648.996357                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 48055.434692                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129119.402985                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154177.308652                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154090.315560                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160109.895069                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 160109.895069                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129119.402985                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 157022.728503                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 156972.234976                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests     24388069                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     12550954                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1330                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops      2014096                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2013701                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          395                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq        959951                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     11237676                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        17726                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        17726                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4787619                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      8213812                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      2728404                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq      1028067                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       448479                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       348012                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       489399                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           78                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          137                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1222080                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1199432                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      6084570                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5051662                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       514998                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       456882                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     18253249                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18257850                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       433982                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1356808                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         38301889                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    778787952                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    707763692                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1655168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      5145936                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1493352748                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    6663078                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     19657279                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.121604                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.326890                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          17267267     87.84%     87.84% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           2389617     12.16%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               395      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      19657279                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   24252664474                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    176228657                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   9133388497                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   8423069488                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    227423320                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    714183249                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40322                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40322                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136632                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136632                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47654                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122588                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231240                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231240                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353908                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47674                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155695                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338976                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338976                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496757                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36957001                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               329000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               13500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            24079502                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36400000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           567357875                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92687000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147936000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115615                       # number of replacements
system.iocache.tags.tagsinuse               11.303922                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115631                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9121269324000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.412531                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.891391                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.463283                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.243212                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706495                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040937                       # Number of tag accesses
system.iocache.tags.data_accesses             1040937                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8892                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8929                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8892                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8932                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8892                       # number of overall misses
system.iocache.overall_misses::total             8932                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5198500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1708541513                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1713740013                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13535070862                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13535070862                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5567500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1708541513                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1714109013                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5567500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1708541513                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1714109013                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8892                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8929                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8892                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8932                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8892                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8932                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet       140500                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 192143.669928                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 191929.668832                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126818.368769                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126818.368769                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 192143.669928                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 191906.517353                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 192143.669928                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 191906.517353                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         34688                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3476                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.979287                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106693                       # number of writebacks
system.iocache.writebacks::total               106693                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8892                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8929                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8892                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8932                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8892                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8932                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1263941513                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1267290013                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8192379111                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8192379111                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3567500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1263941513                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1267509013                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3567500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1263941513                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1267509013                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        90500                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142143.669928                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 141929.668832                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76759.417501                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76759.417501                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 142143.669928                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 141906.517353                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 142143.669928                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 141906.517353                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1503046                       # number of replacements
system.l2c.tags.tagsinuse                63375.622092                       # Cycle average of tags in use
system.l2c.tags.total_refs                    6171586                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1562708                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.949289                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               4906135000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   21677.292557                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    83.067014                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker    94.369601                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3446.989039                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6115.798225                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  4388.751690                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   261.257745                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   419.349614                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3918.629584                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     8309.441217                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14660.675806                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.330769                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001268                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.001440                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.052597                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.093320                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.066967                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003986                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.006399                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.059794                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.126792                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.223704                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.967035                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022         9545                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          198                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        49919                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          721                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          554                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         8260                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          193                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          332                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2886                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5698                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        40984                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.145645                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003021                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.761703                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 78456956                       # Number of tag accesses
system.l2c.tags.data_accesses                78456956                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks      2864457                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2864457                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total               1                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data          177336                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          132362                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              309698                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         38451                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         42622                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             81073                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            52385                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            53709                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106094                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6384                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4273                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       499570                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       608768                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       311188                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6757                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4531                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       536739                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       583922                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       292843                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2854975                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       132875                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       127159                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           260034                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6384                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4273                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              499570                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              661153                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       311188                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6757                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4531                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              536739                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              637631                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       292843                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2961069                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6384                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4273                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             499570                       # number of overall hits
system.l2c.overall_hits::cpu0.data             661153                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       311188                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6757                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4531                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             536739                       # number of overall hits
system.l2c.overall_hits::cpu1.data             637631                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       292843                       # number of overall hits
system.l2c.overall_hits::total                2961069                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         62895                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         64271                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            127166                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        12027                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        12595                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           24622                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          80267                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          60030                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140297                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1639                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1057                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        49818                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       124211                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       228039                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         3279                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         3223                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        53421                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       140654                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       285232                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         890573                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       448396                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       141685                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         590081                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1639                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1057                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             49818                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            204478                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       228039                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         3279                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         3223                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             53421                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            200684                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       285232                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1030870                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1639                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1057                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            49818                       # number of overall misses
system.l2c.overall_misses::cpu0.data           204478                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       228039                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         3279                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         3223                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            53421                       # number of overall misses
system.l2c.overall_misses::cpu1.data           200684                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       285232                       # number of overall misses
system.l2c.overall_misses::total              1030870                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data   1112376000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data   1041657500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   2154033500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data    166517500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data    204256500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    370774000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  11267452492                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   8441524499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  19708976991                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    239750000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    155989500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6853821500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  17860631492                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  42675512933                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    464430000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    455098500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   7368110000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  20598242999                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  52661073904                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 149332660828                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data    199010000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data    130631000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total    329641000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    239750000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    155989500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6853821500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  29128083984                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  42675512933                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    464430000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    455098500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   7368110000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  29039767498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  52661073904                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    169041637819                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    239750000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    155989500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6853821500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  29128083984                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  42675512933                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    464430000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    455098500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   7368110000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  29039767498                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  52661073904                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   169041637819                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2864457                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2864457                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       240231                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       196633                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          436864                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        50478                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        55217                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        105695                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       132652                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       113739                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246391                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         8023                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         5330                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       549388                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       732979                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       539227                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        10036                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7754                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       590160                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       724576                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       578075                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3745548                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       581271                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       268844                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       850115                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8023                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         5330                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          549388                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          865631                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       539227                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        10036                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7754                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          590160                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          838315                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       578075                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             3991939                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8023                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         5330                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         549388                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         865631                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       539227                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        10036                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7754                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         590160                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         838315                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       578075                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            3991939                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.261811                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.326858                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.291088                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.238262                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.228100                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.232953                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.605095                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.527787                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.569408                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.204288                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.198311                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.090679                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.169461                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.326724                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.415656                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.090520                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.194119                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.237768                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.771406                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.527016                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.694119                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.204288                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.198311                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.090679                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.236218                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.326724                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.415656                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.090520                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.239390                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.258238                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.204288                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.198311                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.090679                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.236218                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.326724                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.415656                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.090520                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.239390                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.258238                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17686.238970                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16207.270775                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 16938.753283                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13845.306394                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 16217.268757                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 15058.646739                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 140374.655736                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 140621.764101                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 140480.387970                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 146278.218426                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 147577.578051                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137577.211048                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 143792.671277                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141637.694419                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141203.381942                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137925.347710                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146446.194200                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 167681.549775                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   443.826439                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   921.981861                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   558.636865                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 146278.218426                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 147577.578051                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 137577.211048                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 142450.943300                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141637.694419                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141203.381942                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 137925.347710                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 144703.949981                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 163979.587939                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 146278.218426                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 147577.578051                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 137577.211048                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 142450.943300                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141637.694419                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141203.381942                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 137925.347710                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 144703.949981                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 163979.587939                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             14431                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                      146                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     98.842466                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1201695                       # number of writebacks
system.l2c.writebacks::total                  1201695                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          163                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           25                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          145                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data            9                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          342                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            163                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             25                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            145                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                342                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           163                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            25                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           145                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               342                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        53917                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        53917                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        62895                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        64271                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total       127166                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        12027                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        12595                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        24622                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        80267                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        60030                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140297                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1639                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1057                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        49655                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       124186                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       228039                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         3279                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         3223                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        53276                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       140645                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       285232                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       890231                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       448396                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       141685                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       590081                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1639                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1057                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        49655                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       204453                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       228039                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         3279                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         3223                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        53276                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       200675                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       285232                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1030528                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1639                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1057                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        49655                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       204453                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       228039                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         3279                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         3223                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        53276                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       200675                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       285232                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1030528                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        19295                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        19230                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        59885                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        20724                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        17726                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38450                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        40019                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        36956                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        98335                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   4446225996                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   4534639994                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   8980865990                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    886749499                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    926414497                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total   1813163996                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  10464275798                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   7840878904                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  18305154702                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    223351517                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    145414512                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   6337103575                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  16614995089                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  40393654484                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    431629523                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    422863011                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   6817728943                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  19190174661                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  49807612610                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 140384527925                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  31537249501                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   9872026491                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  41409275992                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    223351517                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    145414512                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   6337103575                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  27079270887                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  40393654484                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    431629523                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    422863011                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   6817728943                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  27031053565                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  49807612610                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 158689682627                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    223351517                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    145414512                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   6337103575                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  27079270887                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  40393654484                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    431629523                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    422863011                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   6817728943                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  27031053565                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  49807612610                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 158689682627                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2396807500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3287554526                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7444500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2618864514                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8310671040                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3427997062                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2536356535                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5964353597                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2396807500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6715551588                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7444500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5155221049                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  14275024637                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.261811                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.326858                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.291088                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.238262                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.228100                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.232953                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.605095                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.527787                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.569408                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.204288                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.198311                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.090382                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.169426                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.326724                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.415656                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.090274                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.194107                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.237677                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.771406                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.527016                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.694119                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.204288                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.198311                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.090382                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.236190                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.326724                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.415656                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.090274                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.239379                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.258152                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.204288                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.198311                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.090382                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.236190                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.326724                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.415656                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.090274                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.239379                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.258152                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70692.837205                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70554.993605                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70623.169637                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73729.899310                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73554.148233                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73639.996588                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 130368.343130                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 130616.007063                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 130474.313079                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127622.667909                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 133791.209065                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127969.985416                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136444.058879                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 157694.494940                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70333.476438                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69675.876000                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70175.579271                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127622.667909                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132447.412789                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127969.985416                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 134700.653121                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 153988.715131                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127622.667909                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132447.412789                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127969.985416                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 134700.653121                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 153988.715131                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170383.753615                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111111.940299                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136186.402184                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138777.173583                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165411.940842                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143086.795385                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155119.729441                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167809.080387                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111111.940299                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 139496.185978                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 145167.281609                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               59885                       # Transaction distribution
system.membus.trans_dist::ReadResp             959045                       # Transaction distribution
system.membus.trans_dist::WriteReq              38450                       # Transaction distribution
system.membus.trans_dist::WriteResp             38450                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1308388                       # Transaction distribution
system.membus.trans_dist::CleanEvict           245549                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           443766                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         303375                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              24                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq            149775                       # Transaction distribution
system.membus.trans_dist::ReadExResp           134703                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        899160                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        692677                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122588                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26142                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4883481                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5032287                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238261                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       238261                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5270548                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155695                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52284                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    142819456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    143027991                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7275456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7275456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               150303447                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           603397                       # Total snoops (count)
system.membus.snoop_fanout::samples           4141095                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4141095    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4141095                       # Request fanout histogram
system.membus.reqLayer0.occupancy            97863497                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               52000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            22133983                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9091243819                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5543319054                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45567476                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     12058125                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      6550145                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1934123                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         145409                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       132628                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        12781                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              59887                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4587364                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38450                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38450                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      4172911                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2698369                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          743738                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        384448                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1128186                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          137                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          137                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           300120                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          300120                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4534724                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       956843                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       850115                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9259077                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8380798                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17639875                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    229804683                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    209683148                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              439487831                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3155812                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          8637402                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.346247                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.478873                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5659510     65.52%     65.52% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                2965111     34.33%     99.85% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  12781      0.15%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            8637402                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         9396796139                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2598429                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4205091357                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4119595686                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    5119                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   13991                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------