path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.468752                       # Number of seconds simulated
sim_ticks                                47468751978000                       # Number of ticks simulated
final_tick                               47468751978000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 133266                       # Simulator instruction rate (inst/s)
host_op_rate                                   156717                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6699893970                       # Simulator tick rate (ticks/s)
host_mem_usage                                 769956                       # Number of bytes of host memory used
host_seconds                                  7085.00                       # Real time elapsed on the host
sim_insts                                   944191442                       # Number of instructions simulated
sim_ops                                    1110340105                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       171136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       120960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3861216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         14070216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     17654336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       218240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       209216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3621984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         13693456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     20748864                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        405504                       # Number of bytes read from this memory
system.physmem.bytes_read::total             74775128                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3861216                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3621984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7483200                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     90808384                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          90828968                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2674                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1890                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             76284                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            219860                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       275849                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         3410                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         3269                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             56637                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            213973                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       324201                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6336                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1184383                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1418881                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1421455                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3605                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2548                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               81342                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              296410                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       371915                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          4598                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          4407                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               76302                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              288473                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       437106                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8543                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1575250                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          81342                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          76302                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             157645                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1913014                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1913448                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1913014                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3605                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2548                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              81342                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             296844                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       371915                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         4598                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         4407                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              76302                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             288473                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       437106                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8543                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3488697                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1184383                       # Number of read requests accepted
system.physmem.writeReqs                      1421455                       # Number of write requests accepted
system.physmem.readBursts                     1184383                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1421455                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 75776512                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     24000                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  90827456                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  74775128                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               90828968                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      375                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               72103                       # Per bank write bursts
system.physmem.perBankRdBursts::1               78803                       # Per bank write bursts
system.physmem.perBankRdBursts::2               72464                       # Per bank write bursts
system.physmem.perBankRdBursts::3               70552                       # Per bank write bursts
system.physmem.perBankRdBursts::4               69846                       # Per bank write bursts
system.physmem.perBankRdBursts::5               79143                       # Per bank write bursts
system.physmem.perBankRdBursts::6               69266                       # Per bank write bursts
system.physmem.perBankRdBursts::7               70722                       # Per bank write bursts
system.physmem.perBankRdBursts::8               68903                       # Per bank write bursts
system.physmem.perBankRdBursts::9               99020                       # Per bank write bursts
system.physmem.perBankRdBursts::10              71711                       # Per bank write bursts
system.physmem.perBankRdBursts::11              73604                       # Per bank write bursts
system.physmem.perBankRdBursts::12              71852                       # Per bank write bursts
system.physmem.perBankRdBursts::13              74765                       # Per bank write bursts
system.physmem.perBankRdBursts::14              70123                       # Per bank write bursts
system.physmem.perBankRdBursts::15              71131                       # Per bank write bursts
system.physmem.perBankWrBursts::0               89065                       # Per bank write bursts
system.physmem.perBankWrBursts::1               93300                       # Per bank write bursts
system.physmem.perBankWrBursts::2               85781                       # Per bank write bursts
system.physmem.perBankWrBursts::3               86502                       # Per bank write bursts
system.physmem.perBankWrBursts::4               86907                       # Per bank write bursts
system.physmem.perBankWrBursts::5               92159                       # Per bank write bursts
system.physmem.perBankWrBursts::6               86239                       # Per bank write bursts
system.physmem.perBankWrBursts::7               88123                       # Per bank write bursts
system.physmem.perBankWrBursts::8               85047                       # Per bank write bursts
system.physmem.perBankWrBursts::9               93098                       # Per bank write bursts
system.physmem.perBankWrBursts::10              87729                       # Per bank write bursts
system.physmem.perBankWrBursts::11              90867                       # Per bank write bursts
system.physmem.perBankWrBursts::12              86341                       # Per bank write bursts
system.physmem.perBankWrBursts::13              90891                       # Per bank write bursts
system.physmem.perBankWrBursts::14              88902                       # Per bank write bursts
system.physmem.perBankWrBursts::15              88228                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          43                       # Number of times write queue was full causing retry
system.physmem.totGap                    47468750370500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1163025                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1418881                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    512770                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    308725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     87137                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     63943                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     45149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     40149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     37001                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     34987                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     30693                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      8585                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     4718                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2994                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     2073                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1609                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1005                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      881                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      765                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      567                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      148                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       96                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    26847                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    31854                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    44695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    49676                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    56919                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    61698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    67754                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    74407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    81101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    85167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    89920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    95633                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    94983                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    99480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   111361                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    98562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    89368                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    83432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                    13050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     9803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     8425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     6741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     5561                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     4626                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     3942                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     3261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     2837                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     2381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     2058                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1391                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1040                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      919                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      666                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      524                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      368                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      105                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1159540                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      143.680535                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      97.586865                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     190.741453                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         783407     67.56%     67.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       222260     19.17%     86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        55727      4.81%     91.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        24890      2.15%     93.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        21192      1.83%     95.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11987      1.03%     96.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8178      0.71%     97.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         4967      0.43%     97.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        26932      2.32%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1159540                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         67946                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        17.425117                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       68.584486                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           67943    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           67946                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         67946                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.886866                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.982744                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       74.693624                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-127           67692     99.63%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-255           167      0.25%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-383            12      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-511            13      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-639            10      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-767             5      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::768-895             6      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::896-1023            2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1024-1151            3      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1152-1279            3      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1280-1407            1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1408-1535            3      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1536-1663            1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1664-1791            2      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1792-1919            3      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1920-2047            1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2048-2175            1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2176-2303            2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2432-2559            1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2560-2687            2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2688-2815            1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2944-3071            1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3072-3199            1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3200-3327            1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3584-3711            1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3840-3967            2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3968-4095            3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4224-4351            3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4736-4863            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5760-5887            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6528-6655            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           67946                       # Writes before turning the bus around for reads
system.physmem.totQLat                    53444908202                       # Total ticks spent queuing
system.physmem.totMemAccLat               75645058202                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5920040000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       45138.98                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  63888.98                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.60                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.91                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.58                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.91                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.06                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.70                       # Average write queue length when enqueuing
system.physmem.readRowHits                     894156                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    549489                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.52                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  38.72                       # Row buffer hit rate for writes
system.physmem.avgGap                     18216309.06                       # Average gap between requests
system.physmem.pageHitRate                      55.46                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 4374828360                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2387059125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4546612200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4588332480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3100427903040                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1181604436515                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27444754155000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31742683326720                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.706973                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45656629611476                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1585085840000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    227033353524                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 4391294040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2396043375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4688572200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4607947440                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3100427903040                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1183305976290                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27443261584500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31743079320885                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.715315                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45654123959514                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1585085840000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    229539287986                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           556                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          368                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           23                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           11                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              132444225                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         87787955                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          6400754                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            93524644                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               57612051                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            61.600931                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               17778768                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            168825                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4144770                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           2586947                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses         1557823                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted       392899                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   539802                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               539802                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        11294                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        84152                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       248635                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       291167                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2569.659336                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 15605.583986                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       288567     99.11%     99.11% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         1409      0.48%     99.59% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          865      0.30%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          174      0.06%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679           52      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           75      0.03%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751           18      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       291167                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       273980                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 20501.036572                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 17496.757374                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 20192.590719                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       271123     98.96%     98.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          705      0.26%     99.21% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1540      0.56%     99.78% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          149      0.05%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          269      0.10%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           86      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           62      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           25      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            6      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       273980                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 529053057016                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.549473                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.550536                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 527876290016     99.78%     99.78% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3    603631000      0.11%     99.89% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5    259797000      0.05%     99.94% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7    123836500      0.02%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9     92525500      0.02%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11     56948500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13     16655000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15     23145000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       228500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 529053057016                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        84152     88.17%     88.17% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        11294     11.83%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        95446                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       539802                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       539802                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        95446                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        95446                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       635248                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    96092667                       # DTB read hits
system.cpu0.dtb.read_misses                    371231                       # DTB read misses
system.cpu0.dtb.write_hits                   80108557                       # DTB write hits
system.cpu0.dtb.write_misses                   168571                       # DTB write misses
system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              46091                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1084                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   35125                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      346                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  6813                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    38936                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                96463898                       # DTB read accesses
system.cpu0.dtb.write_accesses               80277128                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        176201224                       # DTB hits
system.cpu0.dtb.misses                         539802                       # DTB misses
system.cpu0.dtb.accesses                    176741026                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    79903                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                79903                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          950                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        57315                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore         9653                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        70250                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1248.284698                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 10855.060811                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-65535        69985     99.62%     99.62% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-131071           65      0.09%     99.72% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-196607          177      0.25%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-262143           11      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-327679            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-393215            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        70250                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        67918                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26250.242940                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 22828.736245                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 25780.781063                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        66522     97.94%     97.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          103      0.15%     98.10% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607         1066      1.57%     99.67% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           71      0.10%     99.77% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           86      0.13%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           28      0.04%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           25      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::917504-983039            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        67918                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 408740768228                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.873449                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.332683                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    51752271292     12.66%     12.66% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   356965086936     87.33%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       21879500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        1303500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4          81500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          52500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6          29500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::7           1000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::8          62500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 408740768228                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        57315     98.37%     98.37% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          950      1.63%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        58265                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        79903                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        79903                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        58265                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        58265                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       138168                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   207793696                       # ITB inst hits
system.cpu0.itb.inst_misses                     79903                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              46091                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1084                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   24840                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   191050                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               207873599                       # ITB inst accesses
system.cpu0.itb.hits                        207793696                       # DTB hits
system.cpu0.itb.misses                          79903                       # DTB misses
system.cpu0.itb.accesses                    207873599                       # DTB accesses
system.cpu0.numCycles                       761315266                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          84074114                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     585063894                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  132444225                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          77977766                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    631770796                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               13765762                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   1785587                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles              318737                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      5559321                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       752999                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles       796339                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                207603742                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              1586738                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  26136                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         731940774                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.936268                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.209570                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               403543312     55.13%     55.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1               128205713     17.52%     72.65% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                43488128      5.94%     78.59% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3               156703621     21.41%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           731940774                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.173968                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.768491                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               100319911                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            372509653                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                217857253                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             36338079                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               4915878                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            18873695                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              2004301                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             606758178                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts             22350639                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               4915878                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               134368949                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               57393762                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     239367965                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                219640614                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             76253606                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             590337881                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              5891778                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents             10879657                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                272900                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                275104                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              42478331                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents           10735                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          562575259                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            912365987                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       697390419                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           694396                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            507972674                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                54602579                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          15164295                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      13334098                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 72899123                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            96066209                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           83257958                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          8637114                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         7533431                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 568637659                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           15304177                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                573527019                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued          2573483                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       51469570                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     33194366                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        252301                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    731940774                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.783570                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.057506                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          419086912     57.26%     57.26% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1          131041268     17.90%     75.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2          110621862     15.11%     90.27% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           63525040      8.68%     98.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            7661553      1.05%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5               4139      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      731940774                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               59257381     45.13%     45.13% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 46667      0.04%     45.16% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                  17941      0.01%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc              17      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead              34285997     26.11%     71.29% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite             37701656     28.71%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass               17      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            391712029     68.30%     68.30% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1330798      0.23%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                69152      0.01%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  6      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         42956      0.01%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            99049842     17.27%     85.82% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           81322170     14.18%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             573527019                       # Type of FU issued
system.cpu0.iq.rate                          0.753337                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                  131309659                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.228951                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        2011763518                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        635110276                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    556950573                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1114436                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            438215                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       411063                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             704141671                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 694990                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         2575949                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     11750995                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        17228                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       138196                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      5318019                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2553185                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      4584143                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               4915878                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                6708218                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              2698388                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          584066483                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             96066209                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            83257958                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          13102761                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 64235                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              2566402                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        138196                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       1807441                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      2958148                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             4765589                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            565930325                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             96085763                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          7069222                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       124647                       # number of nop insts executed
system.cpu0.iew.exec_refs                   176196325                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               106580080                       # Number of branches executed
system.cpu0.iew.exec_stores                  80110562                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.743359                       # Inst execution rate
system.cpu0.iew.wb_sent                     558072531                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    557361636                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                269759058                       # num instructions producing a value
system.cpu0.iew.wb_consumers                442874225                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.732104                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.609110                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       44855365                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       15051876                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4433751                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    723417587                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.736051                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.544488                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    490442876     67.80%     67.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1    120876307     16.71%     84.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     51465837      7.11%     91.62% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     17138323      2.37%     93.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     12635808      1.75%     95.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      8409902      1.16%     96.90% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      5731195      0.79%     97.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3469312      0.48%     98.17% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     13248027      1.83%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    723417587                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           452974919                       # Number of instructions committed
system.cpu0.commit.committedOps             532472262                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     162255152                       # Number of memory references committed
system.cpu0.commit.loads                     84315213                       # Number of loads committed
system.cpu0.commit.membars                    3606698                       # Number of memory barriers committed
system.cpu0.commit.branches                 101352780                       # Number of branches committed
system.cpu0.commit.fp_insts                    403239                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                488332622                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            13274605                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       369012489     69.30%     69.30% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1112277      0.21%     69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           54460      0.01%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        37842      0.01%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       84315213     15.83%     85.36% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      77939939     14.64%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        532472262                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             13248027                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1283601950                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1163144719                       # The number of ROB writes
system.cpu0.timesIdled                         940575                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       29374492                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 94176188727                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  452974919                       # Number of Instructions Simulated
system.cpu0.committedOps                    532472262                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.680701                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.680701                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.594990                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.594990                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               668586496                       # number of integer regfile reads
system.cpu0.int_regfile_writes              395947855                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   683579                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  295852                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                123538962                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               124272565                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1278649841                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              15273032                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements          5802522                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          485.093904                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          150368529                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5803033                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            25.912058                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       2962390000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.093904                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.947449                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.947449                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          391                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        336490622                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       336490622                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     77978502                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       77978502                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     67507915                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      67507915                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       199394                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       199394                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       171803                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       171803                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1821693                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1821693                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1835435                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1835435                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    145658220                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       145658220                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    145857614                       # number of overall hits
system.cpu0.dcache.overall_hits::total      145857614                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      6410027                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      6410027                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      7429665                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      7429665                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       719434                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       719434                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       793389                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       793389                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       238145                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       238145                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       190782                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       190782                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     14633081                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      14633081                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     15352515                       # number of overall misses
system.cpu0.dcache.overall_misses::total     15352515                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 109062490500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 109062490500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 171373805000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 171373805000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  50210173040                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  50210173040                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3622154000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   3622154000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5311494500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   5311494500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5825000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5825000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 330646468540                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 330646468540                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 330646468540                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 330646468540                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     84388529                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     84388529                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     74937580                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     74937580                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       918828                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       918828                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       965192                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       965192                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2059838                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2059838                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2026217                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2026217                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    160291301                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    160291301                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    161210129                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    161210129                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.075959                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.075959                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.099145                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.099145                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.782991                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.782991                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.822001                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.822001                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.115613                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.115613                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.094157                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.094157                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.091291                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.091291                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.095233                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.095233                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17014.357428                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17014.357428                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23066.155069                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23066.155069                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 63285.693449                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 63285.693449                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15209.867938                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15209.867938                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27840.647965                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27840.647965                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22595.820288                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 22595.820288                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21536.957856                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 21536.957856                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     15517119                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets     25638833                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           732854                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         730129                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.173548                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    35.115484                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      5802538                       # number of writebacks
system.cpu0.dcache.writebacks::total          5802538                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3327729                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      3327729                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5970882                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      5970882                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4398                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         4398                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       123286                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       123286                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      9303009                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      9303009                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      9303009                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      9303009                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3082298                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3082298                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1458783                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1458783                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       712505                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       712505                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       788991                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       788991                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       114859                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       114859                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       190777                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       190777                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5330072                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5330072                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      6042577                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      6042577                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        19706                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        19706                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        21266                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        21266                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        40972                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40972                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48302897000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  48302897000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39166129612                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  39166129612                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  19342072500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  19342072500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  49145395540                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  49145395540                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1672767500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1672767500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5120787500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5120787500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5755000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5755000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 136614422152                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 136614422152                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 155956494652                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 155956494652                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3863694500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3863694500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3863694500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3863694500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036525                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036525                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019467                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019467                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.775450                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.775450                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.817445                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.817445                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.055761                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.055761                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.094154                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.094154                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.033252                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.033252                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.037483                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.037483                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15671.066522                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15671.066522                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26848.496049                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26848.496049                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27146.577919                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27146.577919                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 62288.917795                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 62288.917795                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14563.660662                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14563.660662                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26841.744550                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26841.744550                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25630.877435                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25630.877435                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25809.599886                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25809.599886                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196066.908556                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196066.908556                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94300.851801                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94300.851801                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements          5681079                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.944679                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          201561746                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5681591                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.476286                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      18014203000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.944679                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999892                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999892                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          483                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        420833426                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       420833426                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    201561746                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      201561746                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    201561746                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       201561746                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    201561746                       # number of overall hits
system.cpu0.icache.overall_hits::total      201561746                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6014149                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      6014149                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6014149                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       6014149                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6014149                       # number of overall misses
system.cpu0.icache.overall_misses::total      6014149                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  68585469625                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  68585469625                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  68585469625                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  68585469625                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  68585469625                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  68585469625                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    207575895                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    207575895                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    207575895                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    207575895                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    207575895                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    207575895                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028973                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.028973                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028973                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.028973                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028973                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.028973                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11404.019027                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11404.019027                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11404.019027                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11404.019027                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11404.019027                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11404.019027                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs     10444384                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1542                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           695799                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             13                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.010634                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets   118.615385                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      5681079                       # number of writebacks
system.cpu0.icache.writebacks::total          5681079                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       332513                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       332513                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       332513                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       332513                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       332513                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       332513                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5681636                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      5681636                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      5681636                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      5681636                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      5681636                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      5681636                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  61685306454                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  61685306454                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  61685306454                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  61685306454                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  61685306454                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  61685306454                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2939780498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2939780498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2939780498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2939780498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027371                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027371                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027371                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.027371                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027371                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.027371                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10856.962054                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10856.962054                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10856.962054                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10856.962054                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10856.962054                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10856.962054                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.236651                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.236651                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7915167                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7926437                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit        10130                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1009963                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2664029                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16072.729216                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          16415073                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2680041                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.124934                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      3423391000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14987.796585                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    47.087094                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    49.541309                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   988.304228                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.914783                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002874                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003024                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.060321                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.981002                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1464                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           68                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14480                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           48                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          590                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          290                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          526                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           35                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1208                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5747                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         2985                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4461                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.089355                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004150                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.883789                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       394147733                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      394147733                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       551770                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       179424                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        731194                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3854487                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3854487                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      7627202                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      7627202                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          654                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total          654                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            5                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total            5                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       878534                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       878534                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5121208                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      5121208                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2880934                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2880934                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       188453                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       188453                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       551770                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       179424                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      5121208                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3759468                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        9611870                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       551770                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       179424                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      5121208                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3759468                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       9611870                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12055                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8680                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        20735                       # number of ReadReq misses
system.cpu0.l2cache.WritebackDirty_misses::writebacks            3                       # number of WritebackDirty misses
system.cpu0.l2cache.WritebackDirty_misses::total            3                       # number of WritebackDirty misses
system.cpu0.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
system.cpu0.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       264383                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       264383                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       190766                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       190766                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            6                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       327479                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       327479                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       560388                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       560388                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1024494                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1024494                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       598286                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       598286                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12055                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8680                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       560388                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1351973                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1933096                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12055                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8680                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       560388                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1351973                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1933096                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    639534000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    449293500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   1088827500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3359987500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   3359987500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1839849500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1839849500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      5649000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      5649000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  21332705499                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  21332705499                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22152073000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22152073000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  44214750984                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  44214750984                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    435322500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    435322500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    639534000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    449293500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22152073000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  65547456483                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  88788356983                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    639534000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    449293500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22152073000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  65547456483                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  88788356983                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       563825                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       188104                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       751929                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3854490                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3854490                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      7627203                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      7627203                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       265037                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       265037                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       190771                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       190771                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1206013                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1206013                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5681596                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      5681596                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3905428                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3905428                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       786739                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       786739                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       563825                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       188104                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5681596                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5111441                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     11544966                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       563825                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       188104                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5681596                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5111441                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     11544966                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021381                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.046145                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.027576                       # miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.997532                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.997532                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999974                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999974                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.271539                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.271539                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.098632                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.098632                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.262326                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.262326                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.760463                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.760463                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021381                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.046145                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.098632                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.264499                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.167441                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021381                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.046145                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.098632                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.264499                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.167441                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 53051.347988                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 51761.923963                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 52511.574632                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 12708.788008                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 12708.788008                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9644.535714                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9644.535714                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       941500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       941500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65142.209116                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65142.209116                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39529.884651                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39529.884651                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 43157.647565                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 43157.647565                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   727.616057                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   727.616057                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53051.347988                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 51761.923963                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39529.884651                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 48482.814733                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 45930.650616                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53051.347988                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 51761.923963                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39529.884651                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 48482.814733                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 45930.650616                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          710                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   118.333333                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           45316                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks      1671374                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1671374                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            3                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker           14                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        47908                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total        47908                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            7                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            7                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5947                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5947                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           12                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total           12                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker           14                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            7                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        53855                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        53879                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            3                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker           14                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            7                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        53855                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        53879                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12052                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8666                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        20718                       # number of ReadReq MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            3                       # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::total            3                       # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       803197                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       803197                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       264383                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       264383                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       190766                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       190766                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       279571                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       279571                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       560381                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       560381                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1018547                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1018547                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       598274                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       598274                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12052                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8666                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       560381                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1298118                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1879217                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12052                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8666                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       560381                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1298118                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       803197                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2682414                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        19706                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40999                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        21266                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        21266                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        40972                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        62265                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    567159000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    396729500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    963888500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  57196003159                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  57196003159                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7687713495                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7687713495                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3687086997                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3687086997                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      5229000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5229000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  16511973000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  16511973000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  18789663000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  18789663000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  37621826984                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  37621826984                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  42300516999                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  42300516999                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    567159000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    396729500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  18789663000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  54133799984                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  73887351484                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    567159000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    396729500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  18789663000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  54133799984                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  57196003159                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 131083354643                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780082000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3705524000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6485606000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   2780082000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   3705524000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6485606000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021375                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.046070                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027553                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.997532                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.997532                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999974                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999974                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.231814                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.231814                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.098631                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.098631                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.260803                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.260803                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.760448                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.760448                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021375                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.046070                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.098631                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.253963                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.162774                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021375                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.046070                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.098631                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.253963                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.232345                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46524.206004                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 71210.429271                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 71210.429271                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29077.941831                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29077.941831                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19327.799487                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19327.799487                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       871500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       871500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.823294                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 59061.823294                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33530.157161                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33530.157161                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36936.760880                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36936.760880                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70704.254236                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70704.254236                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33530.157161                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41701.755914                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39318.158299                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33530.157161                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41701.755914                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 71210.429271                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48867.682111                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188040.393789                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158189.370472                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90440.398321                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104161.342648                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests     23859843                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12280153                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1945                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops      2008292                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2007802                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          490                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        875651                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     10557046                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        21267                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        21266                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5532941                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      7629125                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2654810                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1033772                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       476440                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       348822                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       520615                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           53                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1237465                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1213308                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5681636                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4942147                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       844889                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       786739                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     17086897                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18759020                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       394013                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1192566                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         37432496                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    727551888                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    705113777                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1504832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4510600                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1438681097                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    7112172                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     19795414                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.118782                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.323609                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          17444556     88.12%     88.12% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           2350368     11.87%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               490      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      19795414                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   23702360441                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    185100538                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   8549815301                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8326796053                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    206206896                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    629446573                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              144214101                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         95658264                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          7037471                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups           101536339                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               63283833                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            62.326290                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               19487906                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            205159                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        4571638                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           2870819                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses         1700819                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted       415354                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   655828                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               655828                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        14723                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3       107099                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       315531                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       340297                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2456.990511                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 14831.918999                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       337419     99.15%     99.15% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1530      0.45%     99.60% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607         1096      0.32%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143          124      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679           45      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           65      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751           10      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::786432-851967            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       340297                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       353965                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 21023.430283                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17819.927272                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 22140.509228                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       349562     98.76%     98.76% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1039      0.29%     99.05% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607         2363      0.67%     99.72% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143          142      0.04%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679          520      0.15%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215          154      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751          109      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           57      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       353965                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 524755655220                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.627277                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.547876                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 523184603720     99.70%     99.70% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3    876126000      0.17%     99.87% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5    338256000      0.06%     99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7    142712500      0.03%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9    110713000      0.02%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11     57399000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13     19068500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15     26227000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       540000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19         6500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21         1500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23         1500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 524755655220                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K       107100     87.91%     87.91% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        14723     12.09%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       121823                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       655828                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       655828                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       121823                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       121823                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       777651                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                   106468062                       # DTB read hits
system.cpu1.dtb.read_misses                    473211                       # DTB read misses
system.cpu1.dtb.write_hits                   85858726                       # DTB write hits
system.cpu1.dtb.write_misses                   182617                       # DTB write misses
system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              46091                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1084                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   44338                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      492                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  7273                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    40937                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses               106941273                       # DTB read accesses
system.cpu1.dtb.write_accesses               86041343                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        192326788                       # DTB hits
system.cpu1.dtb.misses                         655828                       # DTB misses
system.cpu1.dtb.accesses                    192982616                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    90500                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                90500                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1174                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        63013                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore        10919                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        79581                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1858.653447                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 14270.720139                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-65535        78947     99.20%     99.20% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-131071          217      0.27%     99.48% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-196607          367      0.46%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-262143           26      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-327679           15      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-393215            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        79581                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        75106                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 27703.186164                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23129.879308                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 30256.665627                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        72610     96.68%     96.68% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          191      0.25%     96.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607         1968      2.62%     99.55% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143          115      0.15%     99.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679          133      0.18%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           46      0.06%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           21      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        75106                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 438856254800                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.887236                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.316700                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    49536953716     11.29%     11.29% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   389273644084     88.70%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       42101500      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        2811500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         744000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 438856254800                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        63013     98.17%     98.17% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         1174      1.83%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        64187                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        90500                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        90500                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        64187                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        64187                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       154687                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   226870355                       # ITB inst hits
system.cpu1.itb.inst_misses                     90500                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              46091                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1084                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   32400                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   223247                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               226960855                       # ITB inst accesses
system.cpu1.itb.hits                        226870355                       # DTB hits
system.cpu1.itb.misses                          90500                       # DTB misses
system.cpu1.itb.accesses                    226960855                       # DTB accesses
system.cpu1.numCycles                       812532558                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          91759705                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     638580491                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  144214101                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          85642558                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    676433492                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               15215298                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   2168545                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles              336979                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles      6484962                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       887415                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles       890942                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                226625049                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              1736948                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  29701                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         786569689                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.951781                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.213726                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               428022323     54.42%     54.42% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1               139668800     17.76%     72.17% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                47662444      6.06%     78.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3               171216122     21.77%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           786569689                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.177487                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.785914                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles               110960591                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            393393476                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                236254465                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             40475350                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               5485807                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            20188292                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              2163849                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             661116472                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts             24295467                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               5485807                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               148680347                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               59294510                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     260447701                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                238523513                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             74137811                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             642734014                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts              6463851                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents             12050420                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                431614                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents               1024133                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              35807802                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents           12087                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          613144176                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            993338486                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       758389620                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           787806                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            551826661                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                61317509                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          17340731                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      15198476                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 81471302                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads           106673767                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           89326102                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads         10094322                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         8631476                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 618122262                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           17529509                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                623787865                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued          2873824                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       57783921                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     37389903                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        307135                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    786569689                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.793048                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.056857                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          444068370     56.46%     56.46% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1          146437024     18.62%     75.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2          119059525     15.14%     90.21% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           68792645      8.75%     98.96% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            8206769      1.04%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               5356      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      786569689                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu               62505184     44.18%     44.18% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 68578      0.05%     44.23% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                  15954      0.01%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc              29      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead              38525280     27.23%     71.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite             40370294     28.53%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               56      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            425111535     68.15%     68.15% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1458161      0.23%     68.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                82493      0.01%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  4      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                1      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   1      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         80022      0.01%     68.41% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.41% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.41% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.41% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead           109884961     17.62%     86.03% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           87170631     13.97%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             623787865                       # Type of FU issued
system.cpu1.iq.rate                          0.767708                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                  141485319                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.226816                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        2177185436                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        693073885                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    605244442                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1319124                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            525529                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       491804                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             764456486                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 816642                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         2875534                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     13536096                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        19732                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       165171                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      5907805                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      2920913                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      4601873                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               5485807                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                8833718                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              2787810                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          635796262                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts            106673767                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            89326102                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          14923932                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 69191                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              2639688                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        165171                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       2071854                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      3210854                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             5282708                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            615332242                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts            106464546                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          7808914                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       144491                       # number of nop insts executed
system.cpu1.iew.exec_refs                   192321367                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               115394599                       # Number of branches executed
system.cpu1.iew.exec_stores                  85856821                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.757302                       # Inst execution rate
system.cpu1.iew.wb_sent                     606557665                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    605736246                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                294174085                       # num instructions producing a value
system.cpu1.iew.wb_consumers                482464820                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.745492                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.609732                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       50535620                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       17222374                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4915629                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    776983088                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.743733                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.546908                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    522401316     67.23%     67.23% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1    133381083     17.17%     84.40% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     55837578      7.19%     91.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     18787317      2.42%     94.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     13118953      1.69%     95.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      9117290      1.17%     96.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      6295998      0.81%     97.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3737021      0.48%     98.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     14306532      1.84%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    776983088                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           491216523                       # Number of instructions committed
system.cpu1.commit.committedOps             577867843                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     176555967                       # Number of memory references committed
system.cpu1.commit.loads                     93137670                       # Number of loads committed
system.cpu1.commit.membars                    4128399                       # Number of memory barriers committed
system.cpu1.commit.branches                 109594417                       # Number of branches committed
system.cpu1.commit.fp_insts                    483207                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                530271703                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            14440728                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       399975864     69.22%     69.22% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult        1198206      0.21%     69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           65313      0.01%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        72493      0.01%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       93137670     16.12%     85.56% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      83418297     14.44%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        577867843                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             14306532                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1386603636                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1266352729                       # The number of ROB writes
system.cpu1.timesIdled                        1031751                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       25962869                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 94124971438                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  491216523                       # Number of Instructions Simulated
system.cpu1.committedOps                    577867843                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.654123                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.654123                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.604550                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.604550                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               726234004                       # number of integer regfile reads
system.cpu1.int_regfile_writes              431188126                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   774766                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  462404                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                133303662                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               133988748                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1377831690                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              17262707                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements          6040824                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          459.378668                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          164299100                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          6041336                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            27.195822                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8482617709500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   459.378668                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.897224                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.897224                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          401                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        366496301                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       366496301                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     86507946                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       86507946                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     72726229                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      72726229                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       199332                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       199332                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       142639                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       142639                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1934214                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1934214                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1984655                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1984655                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    159376814                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       159376814                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    159576146                       # number of overall hits
system.cpu1.dcache.overall_hits::total      159576146                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      7084890                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      7084890                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      7887926                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      7887926                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       742812                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       742812                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       468512                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       468512                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       301623                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       301623                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       202162                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       202162                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data     15441328                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total      15441328                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data     16184140                       # number of overall misses
system.cpu1.dcache.overall_misses::total     16184140                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 122386342500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 122386342500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 173974758337                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 173974758337                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20327422974                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  20327422974                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   5004935500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   5004935500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5709587500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   5709587500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3496000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3496000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 316688523811                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 316688523811                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 316688523811                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 316688523811                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     93592836                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     93592836                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     80614155                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     80614155                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       942144                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       942144                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       611151                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       611151                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2235837                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      2235837                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2186817                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      2186817                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    174818142                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    174818142                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    175760286                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    175760286                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.075699                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.075699                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.097848                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.097848                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.788427                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.788427                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.766606                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.766606                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.134904                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.134904                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.092446                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.092446                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.088328                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.088328                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.092081                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.092081                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17274.275606                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 17274.275606                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22055.830435                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22055.830435                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 43387.198138                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 43387.198138                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16593.348319                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16593.348319                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28242.634620                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28242.634620                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20509.150755                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20509.150755                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19567.831458                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 19567.831458                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs      5568492                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets     28779495                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs           387755                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets         802381                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    14.360852                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    35.867618                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      6040976                       # number of writebacks
system.cpu1.dcache.writebacks::total          6040976                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3573916                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total      3573916                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      6375716                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      6375716                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3475                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total         3475                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       153685                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total       153685                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      9953107                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      9953107                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      9953107                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      9953107                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3510974                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      3510974                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1512210                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1512210                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       742708                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       742708                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       465037                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       465037                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       147938                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       147938                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       202156                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       202156                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      5488221                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      5488221                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      6230929                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      6230929                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        18701                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        18701                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        17029                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        17029                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        35730                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        35730                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  55262810500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  55262810500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  37074565990                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  37074565990                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  18477747500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  18477747500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  19695654974                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  19695654974                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   2170800500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   2170800500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5507478500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5507478500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3449000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3449000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 112033031464                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 112033031464                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 130510778964                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 130510778964                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3038329000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3038329000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3038329000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3038329000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037513                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037513                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018759                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018759                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.788317                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.788317                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.760920                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.760920                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.066167                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066167                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.092443                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.092443                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031394                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031394                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035451                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035451                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15740.022712                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15740.022712                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24516.810489                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24516.810489                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24878.885780                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24878.885780                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 42352.877242                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 42352.877242                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14673.718044                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14673.718044                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27243.705356                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27243.705356                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20413.360079                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20413.360079                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20945.637314                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20945.637314                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162468.798460                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162468.798460                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 85035.796250                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 85035.796250                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.replacements          6229961                       # number of replacements
system.cpu1.icache.tags.tagsinuse          501.669710                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          220025292                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          6230473                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            35.314380                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8522353535000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.669710                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979824                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.979824                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        459465626                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       459465626                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    220025292                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      220025292                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    220025292                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       220025292                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    220025292                       # number of overall hits
system.cpu1.icache.overall_hits::total      220025292                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      6592262                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      6592262                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      6592262                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       6592262                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      6592262                       # number of overall misses
system.cpu1.icache.overall_misses::total      6592262                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  74756974451                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  74756974451                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  74756974451                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  74756974451                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  74756974451                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  74756974451                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    226617554                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    226617554                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    226617554                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    226617554                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    226617554                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    226617554                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029090                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.029090                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029090                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.029090                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029090                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.029090                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11340.109730                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 11340.109730                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11340.109730                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 11340.109730                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11340.109730                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 11340.109730                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs     11528745                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          835                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs           773545                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              6                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.903781                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets   139.166667                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      6229961                       # number of writebacks
system.cpu1.icache.writebacks::total          6229961                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       361744                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total       361744                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst       361744                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total       361744                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst       361744                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total       361744                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      6230518                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      6230518                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      6230518                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      6230518                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      6230518                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      6230518                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  67349232950                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  67349232950                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  67349232950                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  67349232950                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  67349232950                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  67349232950                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8957498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8957498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8957498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      8957498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027494                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027494                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027494                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.027494                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027494                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.027494                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10809.572005                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10809.572005                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10809.572005                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10809.572005                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10809.572005                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10809.572005                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst       133694                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total       133694                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst       133694                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total       133694                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.num_hwpf_issued      8304723                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      8311187                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit         5839                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage      1024317                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2528309                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13413.609149                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          18251408                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2544361                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            7.173278                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9891515003500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12660.361458                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    61.649049                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    73.939309                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data     0.000012                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   617.659322                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.772727                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003763                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004513                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.000000                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.037699                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.818702                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1288                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           59                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14705                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          259                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          581                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          431                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           38                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1409                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5268                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4214                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3711                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.078613                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003601                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.897522                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       421641447                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      421641447                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       670573                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       201040                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        871613                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3790012                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3790012                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      8479233                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      8479233                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          992                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total          992                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            7                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total            7                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       953658                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       953658                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5605859                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      5605859                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3317239                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      3317239                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       173754                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       173754                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       670573                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       201040                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      5605859                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      4270897                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total       10748369                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       670573                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       201040                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      5605859                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      4270897                       # number of overall hits
system.cpu1.l2cache.overall_hits::total      10748369                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        13735                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10344                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        24079                       # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks            1                       # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total            1                       # number of WritebackDirty misses
system.cpu1.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
system.cpu1.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       250358                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       250358                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       202146                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       202146                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       315483                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       315483                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       624615                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       624615                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1080990                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total      1080990                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       289367                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       289367                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        13735                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker        10344                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       624615                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1396473                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      2045167                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        13735                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker        10344                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       624615                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1396473                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      2045167                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    769352500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    652492500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1421845000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3726618500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   3726618500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   2054743500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   2054743500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3377498                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3377498                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  18580326500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  18580326500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  24049432000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  24049432000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  47157033477                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  47157033477                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    475628500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    475628500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    769352500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    652492500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  24049432000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  65737359977                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  91208636977                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    769352500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    652492500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  24049432000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  65737359977                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  91208636977                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       684308                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       211384                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       895692                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3790013                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3790013                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      8479234                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      8479234                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       251350                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       251350                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       202153                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       202153                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1269141                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1269141                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      6230474                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      6230474                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4398229                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      4398229                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       463121                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       463121                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       684308                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       211384                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      6230474                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      5667370                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     12793536                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       684308                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       211384                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      6230474                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      5667370                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     12793536                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020071                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.048935                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.026883                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000000                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000000                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.996053                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.996053                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999965                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999965                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.248580                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.248580                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.100252                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.100252                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.245778                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.245778                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.624819                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.624819                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020071                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.048935                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.100252                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.246406                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.159859                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020071                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.048935                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.100252                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.246406                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.159859                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 56014.015289                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 63079.321346                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 59049.171477                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14885.158453                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14885.158453                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10164.650797                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10164.650797                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1125832.666667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1125832.666667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58894.858043                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58894.858043                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38502.808930                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38502.808930                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43623.931282                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43623.931282                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1643.686046                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1643.686046                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 56014.015289                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 63079.321346                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38502.808930                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 47073.849603                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 44597.158558                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 56014.015289                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 63079.321346                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38502.808930                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 47073.849603                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 44597.158558                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs         1476                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs              14                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs   105.428571                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches           50570                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks      1373649                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1373649                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            2                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            9                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total           11                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        59817                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total        59817                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         6475                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         6475                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            7                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            7                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            2                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            9                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data        66292                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        66303                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            2                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            9                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data        66292                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        66303                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        13733                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10335                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        24068                       # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       868323                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       868323                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       250358                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       250358                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       202146                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       202146                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       255666                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       255666                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       624615                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       624615                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data      1074515                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total      1074515                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       289360                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       289360                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        13733                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10335                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       624615                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1330181                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1978864                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        13733                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        10335                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       624615                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1330181                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       868323                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2847187                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        18701                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        18768                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        17029                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        17029                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        35730                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        35797                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    686821000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    590353500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1277174500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  65644901114                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  65644901114                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   7861561998                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   7861561998                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3988088997                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3988088997                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3095498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3095498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  13308484000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  13308484000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  20301742000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  20301742000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  40328599477                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  40328599477                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  15597274497                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  15597274497                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    686821000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    590353500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  20301742000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  53637083477                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  75215999977                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    686821000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    590353500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  20301742000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  53637083477                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  65644901114                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 140860901091                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8454000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2888554500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2897008500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8454000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2888554500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2897008500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020068                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.048892                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026871                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.996053                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.996053                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999965                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999965                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.201448                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.201448                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.100252                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.100252                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.244306                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.244306                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.624804                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.624804                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020068                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.048892                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.100252                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234709                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.154677                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020068                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.048892                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.100252                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234709                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.222549                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 53065.252618                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 75599.634138                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 75599.634138                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31401.281357                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31401.281357                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19728.755439                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19728.755439                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1031832.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031832.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52054.180063                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52054.180063                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32502.808930                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32502.808930                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37531.909259                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37531.909259                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53902.662763                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53902.662763                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32502.808930                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40323.146607                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38009.686354                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32502.808930                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40323.146607                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 75599.634138                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 49473.708995                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126179.104478                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154459.895193                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154358.935422                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126179.104478                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 80843.954660                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 80928.806883                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests     25472686                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     13111869                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1712                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops      2149417                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2149008                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          409                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq       1009964                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     11730214                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        17029                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        17029                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      5169290                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      8480923                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      2927219                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq      1103039                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       459055                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       356155                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       515583                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           73                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1297103                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1275135                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      6230518                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5372910                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       516382                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       463121                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     18691087                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     19440124                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       443982                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1442906                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         40018099                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    797468912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    755702222                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1691072                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      5474464                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1560336670                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    7082459                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     20668727                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.122834                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.328306                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          18130322     87.72%     87.72% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           2537996     12.28%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               409      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      20668727                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   25335696459                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    177629109                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   9352273561                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   8995491238                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    232944299                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    759270636                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40305                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40305                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136595                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136595                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47570                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122504                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231216                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231216                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353800                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47590                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155611                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338880                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338880                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496577                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36858001                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               326000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               13500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            24204504                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36391000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           567248472                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92640000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147912000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115604                       # number of replacements
system.iocache.tags.tagsinuse               11.311799                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115620                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9121271629000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.400215                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.911583                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.462513                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.244474                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706987                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040829                       # Number of tag accesses
system.iocache.tags.data_accesses             1040829                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8880                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8917                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115608                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115648                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115608                       # number of overall misses
system.iocache.overall_misses::total           115648                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5214500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1674617085                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1679831585                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13548349887                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13548349887                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5583500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15222966972                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15228550472                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5583500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15222966972                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15228550472                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8880                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8917                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115608                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115648                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115608                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115648                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140932.432432                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 188583.005068                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 188385.284849                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126942.788087                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126942.788087                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139587.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 131677.452875                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 131680.188780                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139587.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 131677.452875                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 131680.188780                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         33801                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3396                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.953180                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8880                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8917                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115608                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115648                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115608                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115648                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3364500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1230617085                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1233981585                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8205400767                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8205400767                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3583500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9436017852                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9439601352                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3583500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9436017852                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9439601352                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90932.432432                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138583.005068                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 138385.284849                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76881.425371                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76881.425371                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89587.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 81620.803508                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 81623.559007                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89587.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 81620.803508                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 81623.559007                       # average overall mshr miss latency
system.l2c.tags.replacements                  1658646                       # number of replacements
system.l2c.tags.tagsinuse                63614.355421                       # Cycle average of tags in use
system.l2c.tags.total_refs                    6503693                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1717473                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.786780                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               4906135000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   21778.868920                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    77.174149                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   104.892582                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3369.245029                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4690.877672                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  5127.772728                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   275.118534                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   421.752346                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3923.044466                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    10215.764671                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13629.844323                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.332319                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001178                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.001601                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.051411                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.071577                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.078244                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004198                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.006435                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.059861                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.155880                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.207975                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.970678                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022         9349                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          246                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        49232                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0           12                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1           39                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          275                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          523                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         8500                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          244                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2922                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4073                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        41884                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.142654                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003754                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.751221                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 83070472                       # Number of tag accesses
system.l2c.tags.data_accesses                83070472                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks      3045027                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         3045027                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks            2                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total               2                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data          177681                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          151575                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              329256                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         38520                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         46161                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             84681                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            58316                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            56868                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               115184                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6506                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4755                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       505198                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       629843                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       303617                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6637                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4374                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       567907                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       649267                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       304398                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2982502                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       134777                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       127780                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           262557                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6506                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4755                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              505198                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              688159                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       303617                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6637                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4374                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              567907                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              706135                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       304398                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3097686                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6506                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4755                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             505198                       # number of overall hits
system.l2c.overall_hits::cpu0.data             688159                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       303617                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6637                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4374                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             567907                       # number of overall hits
system.l2c.overall_hits::cpu1.data             706135                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       304398                       # number of overall hits
system.l2c.overall_hits::total                3097686                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         62380                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         67853                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            130233                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        11700                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        13195                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           24895                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          82725                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          61895                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             144620                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2677                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1890                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        55177                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       140078                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       275934                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         3410                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         3269                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        56707                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       154817                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       324363                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total        1018322                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       452102                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       148246                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         600348                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2677                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1890                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             55177                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            222803                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       275934                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         3410                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         3269                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             56707                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            216712                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       324363                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1162942                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2677                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1890                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            55177                       # number of overall misses
system.l2c.overall_misses::cpu0.data           222803                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       275934                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         3410                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         3269                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            56707                       # number of overall misses
system.l2c.overall_misses::cpu1.data           216712                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       324363                       # number of overall misses
system.l2c.overall_misses::total              1162942                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data   1034957000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data   1157063000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   2192020000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data    174365000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data    228989500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    403354500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  11711225489                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   8776678992                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  20487904481                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    384848000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    271512500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   7616921000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  20740892494                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  51616446987                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    485048000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    453166500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   7794605500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  22700743998                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  60057715420                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 172121900399                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data    148772000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data    161516500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total    310288500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    384848000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    271512500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   7616921000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  32452117983                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  51616446987                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    485048000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    453166500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   7794605500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  31477422990                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  60057715420                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    192609804880                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    384848000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    271512500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   7616921000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  32452117983                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  51616446987                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    485048000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    453166500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   7794605500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  31477422990                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  60057715420                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   192609804880                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      3045027                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      3045027                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks            2                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total            2                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       240061                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       219428                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          459489                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        50220                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        59356                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        109576                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       141041                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       118763                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           259804                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         9183                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6645                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       560375                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       769921                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       579551                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        10047                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7643                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       624614                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       804084                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       628761                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      4000824                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       586879                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       276026                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       862905                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         9183                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6645                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          560375                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          910962                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       579551                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        10047                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7643                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          624614                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          922847                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       628761                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4260628                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         9183                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6645                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         560375                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         910962                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       579551                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        10047                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7643                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         624614                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         922847                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       628761                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4260628                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.259851                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.309227                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.283430                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.232975                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.222303                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.227194                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.586532                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.521164                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.556650                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.291517                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.284424                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.098464                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.181938                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.339405                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.427712                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.090787                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.192538                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.254528                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.770350                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.537073                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.695729                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.291517                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.284424                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.098464                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.244580                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.339405                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.427712                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.090787                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.234830                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.272951                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.291517                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.284424                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.098464                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.244580                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.339405                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.427712                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.090787                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.234830                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.272951                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16591.167041                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17052.495837                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 16831.525036                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14902.991453                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17354.262978                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 16202.229363                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 141568.153388                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 141799.482866                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 141667.158630                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143760.926410                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 143657.407407                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 138045.218116                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 148066.737775                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 142242.815249                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 138625.420618                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137454.026840                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146629.530336                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 169025.023911                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   329.067334                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data  1089.516749                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   516.847728                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143760.926410                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 143657.407407                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 138045.218116                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 145653.864549                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 142242.815249                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138625.420618                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 137454.026840                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 145250.023026                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 165622.881347                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143760.926410                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 143657.407407                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 138045.218116                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 145653.864549                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 142242.815249                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138625.420618                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 137454.026840                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 145250.023026                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 165622.881347                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             15923                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                      177                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     89.960452                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1312187                       # number of writebacks
system.l2c.writebacks::total                  1312187                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker            3                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          163                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           34                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          114                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           21                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          335                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            163                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             34                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            114                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             21                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                335                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker            3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           163                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            34                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           114                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            21                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               335                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        62188                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        62188                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        62380                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        67853                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total       130233                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        11700                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        13195                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        24895                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        82725                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        61895                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        144620                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         2674                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1890                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        55014                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       140044                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       275934                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         3410                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         3269                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        56593                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       154796                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       324363                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total      1017987                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       452102                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       148246                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       600348                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2674                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1890                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        55014                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       222769                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       275934                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         3410                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         3269                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        56593                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       216691                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       324363                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1162607                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2674                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1890                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        55014                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       222769                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       275934                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         3410                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         3269                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        56593                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       216691                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       324363                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1162607                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        19706                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        18699                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        59765                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        21266                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        17029                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38295                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        40972                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        35728                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        98060                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   4409168995                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   4786348998                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   9195517993                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    862109992                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    970555497                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total   1832665489                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  10883415957                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   8157375512                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  19040791469                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    357690038                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    252601028                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   7044725224                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  19335135004                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  48855278506                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    450944507                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    420472009                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   7214941938                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  21149813267                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  56812837096                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 161894438617                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  31769945999                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  10316729000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  42086674999                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    357690038                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    252601028                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   7044725224                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  30218550961                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  48855278506                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    450944507                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    420472009                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   7214941938                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  29307188779                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  56812837096                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 180935230086                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    357690038                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    252601028                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   7044725224                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  30218550961                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  48855278506                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    450944507                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    420472009                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   7214941938                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  29307188779                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  56812837096                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 180935230086                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2396807500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3350562534                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7247500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2551834016                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8306451550                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2396807500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3350562534                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7247500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2551834016                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   8306451550                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.259851                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.309227                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.283430                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.232975                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.222303                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.227194                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.586532                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.521164                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.556650                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.291190                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.284424                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.098174                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.181894                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.339405                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.427712                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.090605                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.192512                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.254444                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.770350                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.537073                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.695729                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.291190                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.284424                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.098174                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.244543                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.339405                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.427712                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.090605                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.234807                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.272872                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.291190                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.284424                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.098174                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.244543                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.339405                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.427712                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.090605                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.234807                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.272872                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70682.414155                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70539.976095                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70608.202168                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73684.614701                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73554.793255                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73615.805945                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 131561.389628                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 131793.771904                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 131660.845450                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 128053.317774                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 138064.715404                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127488.239500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136630.231188                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 159033.895931                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70271.633390                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69591.955264                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70103.798129                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 128053.317774                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135649.713205                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127488.239500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135248.758735                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 155628.884125                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 128053.317774                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135649.713205                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127488.239500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135248.758735                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 155628.884125                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170027.531412                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108171.641791                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136469.009894                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138985.217937                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81776.885043                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108171.641791                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 71423.925661                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 84707.847746                       # average overall mshr uncacheable latency
system.membus.trans_dist::ReadReq               59765                       # Transaction distribution
system.membus.trans_dist::ReadResp            1086669                       # Transaction distribution
system.membus.trans_dist::WriteReq              38295                       # Transaction distribution
system.membus.trans_dist::WriteResp             38295                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1418881                       # Transaction distribution
system.membus.trans_dist::CleanEvict           277094                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           441724                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         308123                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            153866                       # Transaction distribution
system.membus.trans_dist::ReadExResp           139435                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       1026904                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        703178                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122504                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25676                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5303073                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5451329                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237588                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237588                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5688917                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155611                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51352                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    158370176                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    158577695                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7233920                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7233920                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               165811615                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           603403                       # Total snoops (count)
system.membus.snoop_fanout::samples           4427877                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4427877    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4427877                       # Request fanout histogram
system.membus.reqLayer0.occupancy            97877995                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               52000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21789496                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9855054431                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6236968511                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45519188                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     12681630                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      6883923                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      2005926                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         170885                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       155146                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        15739                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              59767                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4843433                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38295                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38295                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      4463947                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean            2                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2878269                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          761897                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        392804                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1154700                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          117                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           312867                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          312867                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4790902                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       969633                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       862905                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9568329                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      9002574                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              18570903                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    239712817                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    228526446                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              468239263                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3311598                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          9100879                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.338787                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.476937                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                6033358     66.29%     66.29% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                3051782     33.53%     99.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  15739      0.17%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            9100879                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         9916846796                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2612852                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4354241663                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4394264623                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    4933                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   14218                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------