path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.384940                       # Number of seconds simulated
sim_ticks                                47384940455000                       # Number of ticks simulated
final_tick                               47384940455000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 206357                       # Simulator instruction rate (inst/s)
host_op_rate                                   242664                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            10614318936                       # Simulator tick rate (ticks/s)
host_mem_usage                                 793572                       # Number of bytes of host memory used
host_seconds                                  4464.25                       # Real time elapsed on the host
sim_insts                                   921230293                       # Number of instructions simulated
sim_ops                                    1083311023                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       222656                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       215552                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          4481312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         16941064                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     21659840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       116096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        80000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2978912                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         10395024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     12881984                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        421760                       # Number of bytes read from this memory
system.physmem.bytes_read::total             70394200                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      4481312                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2978912                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7460224                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     86479488                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          86500072                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         3479                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         3368                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             85973                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            264717                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       338435                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1814                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1250                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             46589                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            162435                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       201281                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6590                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1115931                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1351242                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1353816                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          4699                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          4549                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               94572                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              357520                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       457104                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2450                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          1688                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               62866                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              219374                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       271858                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8901                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1485582                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          94572                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          62866                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             157439                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1825042                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1825476                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1825042                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         4699                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         4549                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              94572                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             357954                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       457104                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2450                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         1688                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              62866                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             219374                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       271858                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8901                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3311058                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1115931                       # Number of read requests accepted
system.physmem.writeReqs                      1353816                       # Number of write requests accepted
system.physmem.readBursts                     1115931                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1353816                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 71392384                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     27200                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  86499392                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  70394200                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               86500072                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      425                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               66640                       # Per bank write bursts
system.physmem.perBankRdBursts::1               69755                       # Per bank write bursts
system.physmem.perBankRdBursts::2               65507                       # Per bank write bursts
system.physmem.perBankRdBursts::3               67407                       # Per bank write bursts
system.physmem.perBankRdBursts::4               65920                       # Per bank write bursts
system.physmem.perBankRdBursts::5               70505                       # Per bank write bursts
system.physmem.perBankRdBursts::6               65125                       # Per bank write bursts
system.physmem.perBankRdBursts::7               71371                       # Per bank write bursts
system.physmem.perBankRdBursts::8               68061                       # Per bank write bursts
system.physmem.perBankRdBursts::9               95897                       # Per bank write bursts
system.physmem.perBankRdBursts::10              65782                       # Per bank write bursts
system.physmem.perBankRdBursts::11              68970                       # Per bank write bursts
system.physmem.perBankRdBursts::12              60174                       # Per bank write bursts
system.physmem.perBankRdBursts::13              71971                       # Per bank write bursts
system.physmem.perBankRdBursts::14              71235                       # Per bank write bursts
system.physmem.perBankRdBursts::15              71186                       # Per bank write bursts
system.physmem.perBankWrBursts::0               81261                       # Per bank write bursts
system.physmem.perBankWrBursts::1               86034                       # Per bank write bursts
system.physmem.perBankWrBursts::2               81926                       # Per bank write bursts
system.physmem.perBankWrBursts::3               83311                       # Per bank write bursts
system.physmem.perBankWrBursts::4               82546                       # Per bank write bursts
system.physmem.perBankWrBursts::5               86081                       # Per bank write bursts
system.physmem.perBankWrBursts::6               81799                       # Per bank write bursts
system.physmem.perBankWrBursts::7               86537                       # Per bank write bursts
system.physmem.perBankWrBursts::8               86254                       # Per bank write bursts
system.physmem.perBankWrBursts::9               89944                       # Per bank write bursts
system.physmem.perBankWrBursts::10              82817                       # Per bank write bursts
system.physmem.perBankWrBursts::11              84554                       # Per bank write bursts
system.physmem.perBankWrBursts::12              78968                       # Per bank write bursts
system.physmem.perBankWrBursts::13              86566                       # Per bank write bursts
system.physmem.perBankWrBursts::14              86628                       # Per bank write bursts
system.physmem.perBankWrBursts::15              86327                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                       51513                       # Number of times write queue was full causing retry
system.physmem.totGap                    47384938876500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1094573                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1351242                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    480312                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    254385                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    111988                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     68856                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     44885                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     37588                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     34371                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     31850                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     28995                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      8446                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     4926                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2904                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1783                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1395                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      820                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      687                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      582                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      476                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    22318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    26304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    36819                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    42386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    47455                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    51611                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    56891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    62379                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    68066                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    69883                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    74729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    78908                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    77080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    78119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    84175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    91218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    81081                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    75935                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     8194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     4666                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     3474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2709                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1885                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1809                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1719                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1477                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1621                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1614                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1876                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1830                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1798                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1943                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1999                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     2219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     2498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     2690                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                     2884                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                     3113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                     3416                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                     3559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                     3969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                     4586                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                     5969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                    24986                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                   120772                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1035166                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      152.526679                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     102.371009                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     198.170623                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         664281     64.17%     64.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       215041     20.77%     84.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        59106      5.71%     90.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        25397      2.45%     93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        20542      1.98%     95.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11502      1.11%     96.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7604      0.73%     96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         6193      0.60%     97.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        25500      2.46%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1035166                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         63814                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        17.480459                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       70.581857                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           63808     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            3      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           63814                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         63814                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        21.179569                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.530322                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev      597.849869                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-4095          63812    100.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40960-45055            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::143360-147455            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           63814                       # Writes before turning the bus around for reads
system.physmem.totQLat                    67332860089                       # Total ticks spent queuing
system.physmem.totMemAccLat               88248597589                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5577530000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       60360.82                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  79110.82                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.51                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.83                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.49                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.83                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.79                       # Average write queue length when enqueuing
system.physmem.readRowHits                     837889                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    593994                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.11                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  43.95                       # Row buffer hit rate for writes
system.physmem.avgGap                     19186151.00                       # Average gap between requests
system.physmem.pageHitRate                      58.04                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3662384460                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1946584530                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3871522200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3494763900                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           31929318720.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            40834926540                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             1598586240                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       62046559410                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy       43455299520                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       11294770338285                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             11487626755995                       # Total energy per rank (pJ)
system.physmem_0.averagePower              242.432018                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           47291190900816                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE     2771331378                       # Time in different power states
system.physmem_0.memoryStateTime::REF     13558872000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   47041958774500                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 113164787559                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     77419210306                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 136067479257                       # Time in different power states
system.physmem_1.actEnergy                 3728772180                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1981870440                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4093190640                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3560342760                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           33599910240.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            42188393820                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             1621939680                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       66725147910                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy       45519792000                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       11290481164380                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             11493516343440                       # Total energy per rank (pJ)
system.physmem_1.averagePower              242.556311                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           47288162727367                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE     2732090205                       # Time in different power states
system.physmem_1.memoryStateTime::REF     14267508000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   47023294872500                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 118540781222                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     79778077178                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 146327125895                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           556                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          368                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           23                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           11                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              139151101                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         91634411                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          6732234                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            97916993                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               61670085                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            62.982005                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               19220371                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            194045                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4187621                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           2676103                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses         1511518                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted       384250                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   608743                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               608743                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13705                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        96942                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       292908                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       315835                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2627.591939                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 15089.582893                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       312900     99.07%     99.07% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         2131      0.67%     99.75% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          548      0.17%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          139      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679           36      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           50      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751            5      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359           23      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       315835                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       324732                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22165.202382                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18853.631715                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 18861.810606                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       320100     98.57%     98.57% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         3009      0.93%     99.50% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          694      0.21%     99.71% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          681      0.21%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          132      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           68      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           19      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           13      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       324732                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 522550016344                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.577122                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.559179                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 521035310844     99.71%     99.71% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3    819753000      0.16%     99.87% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5    323762500      0.06%     99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7    144297000      0.03%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9    115791000      0.02%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11     61783500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13     19805000      0.00%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15     28515500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       990500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19         7500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 522550016344                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        96943     87.61%     87.61% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        13705     12.39%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       110648                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       608743                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       608743                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       110648                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       110648                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       719391                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   101564011                       # DTB read hits
system.cpu0.dtb.read_misses                    439385                       # DTB read misses
system.cpu0.dtb.write_hits                   82403711                       # DTB write hits
system.cpu0.dtb.write_misses                   169358                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              44658                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   43119                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      431                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  7683                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    39881                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               102003396                       # DTB read accesses
system.cpu0.dtb.write_accesses               82573069                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        183967722                       # DTB hits
system.cpu0.dtb.misses                         608743                       # DTB misses
system.cpu0.dtb.accesses                    184576465                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    85247                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                85247                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1031                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        58619                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        10594                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        74653                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1640.215397                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 15358.310447                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-65535        74120     99.29%     99.29% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-131071          439      0.59%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-196607           37      0.05%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-262143           19      0.03%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-327679           10      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-393215            2      0.00%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::458752-524287            1      0.00%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::524288-589823            6      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::589824-655359           19      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        74653                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        70244                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 27495.914242                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23588.322709                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 27529.617952                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        67750     96.45%     96.45% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071         1764      2.51%     98.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          417      0.59%     99.55% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143          170      0.24%     99.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           48      0.07%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           42      0.06%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           15      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            5      0.01%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            3      0.00%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359           26      0.04%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        70244                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 419443065740                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.871284                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.335229                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    54034549916     12.88%     12.88% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   365365302324     87.11%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       40992500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        2004000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         217000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 419443065740                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        58619     98.27%     98.27% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         1031      1.73%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        59650                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        85247                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        85247                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        59650                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        59650                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       144897                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   219469803                       # ITB inst hits
system.cpu0.itb.inst_misses                     85247                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              44658                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   31398                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   204530                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               219555050                       # ITB inst accesses
system.cpu0.itb.hits                        219469803                       # DTB hits
system.cpu0.itb.misses                          85247                       # DTB misses
system.cpu0.itb.accesses                    219555050                       # DTB accesses
system.cpu0.numPwrStateTransitions              27212                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples        13606                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    3453780783.684036                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   93985708249.621262                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3589     26.38%     26.38% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         9986     73.39%     99.77% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11           12      0.09%     99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            3      0.02%     99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           13      0.10%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 6914083139000                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total          13606                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   392799112195                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46992141342805                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       785608211                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          89154333                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     616347679                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  139151101                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          83566559                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    651741352                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               14592652                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   2033431                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles              298378                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      6056906                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       755254                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles       834704                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                219265865                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              1675112                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  28029                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         758170684                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.951385                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.212910                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               412487393     54.41%     54.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1               134584185     17.75%     72.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                46569297      6.14%     78.30% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3               164529809     21.70%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           758170684                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.177125                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.784548                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               107249627                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            379334150                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                227390625                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             38947644                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5248638                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            19981467                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              2087891                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             636989334                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts             23191131                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5248638                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               143394034                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               56142021                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     253850770                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                229681319                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             69853902                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             619319594                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              6178554                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents             10862186                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                388792                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                930621                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              33162716                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents           11693                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          591176589                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            957415604                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       731049781                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           649204                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            532948721                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                58227868                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          16256269                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      14199870                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 78279720                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           101593087                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           85666218                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          9630459                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         8075180                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 596126359                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           16460453                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                601474893                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued          2699291                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       54684336                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     35421563                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        283328                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    758170684                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.793324                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.057959                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          428799597     56.56%     56.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1          139371286     18.38%     74.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2          115828942     15.28%     90.22% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           66243104      8.74%     98.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            7922364      1.04%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5               5391      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      758170684                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               61955212     45.30%     45.30% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 62513      0.05%     45.34% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                  16729      0.01%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMultAcc                0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMisc                  21      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead              36421436     26.63%     71.99% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite             37996782     27.78%     99.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemRead            31053      0.02%     99.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemWrite          287360      0.21%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass               30      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            411361741     68.39%     68.39% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1567778      0.26%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                78948      0.01%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                 15      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMultAcc              0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMisc             39915      0.01%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           104723474     17.41%     86.08% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           83352955     13.86%     99.94% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemRead          49350      0.01%     99.95% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemWrite        300687      0.05%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             601474893                       # Type of FU issued
system.cpu0.iq.rate                          0.765617                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                  136771106                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.227393                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        2099488112                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        667007258                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    583889559                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1102755                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            413748                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       385073                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             737537568                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 708401                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         2768605                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     12684669                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        17846                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       151274                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      5522197                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2796342                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      4797484                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5248638                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                8055865                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1895421                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          612718172                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            101593087                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            85666218                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          13907446                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 58112                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1764578                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        151274                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       1949210                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      3085558                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             5034768                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            593488019                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            101560351                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          7385409                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       131360                       # number of nop insts executed
system.cpu0.iew.exec_refs                   183963466                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               111638269                       # Number of branches executed
system.cpu0.iew.exec_stores                  82403115                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.755450                       # Inst execution rate
system.cpu0.iew.wb_sent                     585082868                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    584274632                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                284506732                       # num instructions producing a value
system.cpu0.iew.wb_consumers                466304278                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.743723                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.610131                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       47796807                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       16177125                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4684546                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    749065087                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.744798                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.551758                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    504468440     67.35%     67.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1    127495809     17.02%     84.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     53846196      7.19%     91.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     17894232      2.39%     93.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     12874355      1.72%     95.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      8922431      1.19%     96.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      5996417      0.80%     97.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3594154      0.48%     98.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     13973053      1.87%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    749065087                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           475226157                       # Number of instructions committed
system.cpu0.commit.committedOps             557902476                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     169052439                       # Number of memory references committed
system.cpu0.commit.loads                     88908418                       # Number of loads committed
system.cpu0.commit.membars                    3969625                       # Number of memory barriers committed
system.cpu0.commit.branches                 106090436                       # Number of branches committed
system.cpu0.commit.fp_insts                    377224                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                511981133                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            14308761                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       387443640     69.45%     69.45% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1310567      0.23%     69.68% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           61901      0.01%     69.69% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.69% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.69% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.69% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.69% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMultAcc            0      0.00%     69.69% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.69% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMisc        33929      0.01%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.70% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       88862033     15.93%     85.63% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      79847111     14.31%     99.94% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemRead        46385      0.01%     99.95% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemWrite       296910      0.05%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        557902476                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             13973053                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1336174255                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1220466867                       # The number of ROB writes
system.cpu0.timesIdled                        1005352                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       27437527                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 93984272695                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  475226157                       # Number of Instructions Simulated
system.cpu0.committedOps                    557902476                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.653125                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.653125                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.604915                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.604915                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               700618930                       # number of integer regfile reads
system.cpu0.int_regfile_writes              416450651                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   634669                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  293776                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                128889270                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               129563151                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1347671553                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              16172806                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          6286438                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          484.582319                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          156315528                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6286950                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            24.863492                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       2049282000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   484.582319                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.946450                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.946450                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          324                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        351060755                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       351060755                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     82089512                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       82089512                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     69232216                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      69232216                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       209823                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       209823                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       173405                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       173405                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1868090                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1868090                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1930069                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1930069                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    151495133                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       151495133                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    151704956                       # number of overall hits
system.cpu0.dcache.overall_hits::total      151704956                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      7010414                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7010414                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      7797174                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      7797174                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       751824                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       751824                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       805427                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       805427                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       284725                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       284725                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       186829                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       186829                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     15613015                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      15613015                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     16364839                       # number of overall misses
system.cpu0.dcache.overall_misses::total     16364839                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112159926000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 112159926000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 158052575270                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 158052575270                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  29573159898                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  29573159898                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4301491500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4301491500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4484661500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4484661500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2134500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2134500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 299785661168                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 299785661168                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 299785661168                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 299785661168                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     89099926                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     89099926                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     77029390                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     77029390                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       961647                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       961647                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       978832                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       978832                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2152815                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2152815                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2116898                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2116898                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    167108148                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    167108148                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    168069795                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    168069795                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.078680                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.078680                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.101223                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.101223                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.781809                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.781809                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.822845                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.822845                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.132257                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.132257                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.088256                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.088256                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.093431                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.093431                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097369                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.097369                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15999.044564                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15999.044564                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20270.494832                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20270.494832                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36717.368424                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36717.368424                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15107.530073                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15107.530073                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24004.097330                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24004.097330                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19201.010258                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19201.010258                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18318.888513                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18318.888513                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      8999058                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets     24447381                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           751224                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         774000                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    11.979194                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    31.585764                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      6286527                       # number of writebacks
system.cpu0.dcache.writebacks::total          6286527                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3589298                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      3589298                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6265824                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      6265824                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4129                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         4129                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       147493                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       147493                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      9859251                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      9859251                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      9859251                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      9859251                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3421116                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3421116                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1531350                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1531350                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       745052                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       745052                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       801298                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       801298                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       137232                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       137232                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       186825                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       186825                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5753764                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5753764                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      6498816                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      6498816                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29615                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29615                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        29691                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        29691                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        59306                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        59306                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  51678055000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  51678055000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  34197879948                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  34197879948                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17704904500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17704904500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  28602356899                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  28602356899                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1885182000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1885182000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4297888500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4297888500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2082500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2082500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 114478291847                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 114478291847                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132183196347                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 132183196347                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5594868000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5594868000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5594868000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5594868000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.038396                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.038396                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019880                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019880                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.774767                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.774767                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.818627                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.818627                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.063745                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.063745                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.088254                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.088254                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.034431                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.034431                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.038667                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.038667                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15105.613198                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15105.613198                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22331.850947                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22331.850947                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23763.313836                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23763.313836                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35695.030936                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35695.030936                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13737.189577                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13737.189577                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23004.889603                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23004.889603                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19896.243893                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19896.243893                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20339.581294                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20339.581294                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188920.074287                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188920.074287                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94338.987624                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94338.987624                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          5974428                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.960293                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          212911456                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5974940                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.634074                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      13477910000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.960293                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999922                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999922                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          293                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          116                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        444450377                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       444450377                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    212911456                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      212911456                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    212911456                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       212911456                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    212911456                       # number of overall hits
system.cpu0.icache.overall_hits::total      212911456                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6326229                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      6326229                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6326229                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       6326229                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6326229                       # number of overall misses
system.cpu0.icache.overall_misses::total      6326229                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  70930890398                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  70930890398                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  70930890398                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  70930890398                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  70930890398                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  70930890398                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    219237685                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    219237685                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    219237685                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    219237685                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    219237685                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    219237685                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028856                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.028856                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028856                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.028856                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028856                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.028856                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11212.191402                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11212.191402                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11212.191402                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11212.191402                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11212.191402                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11212.191402                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs     10513720                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1665                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           740505                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             13                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.198041                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets   128.076923                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      5974428                       # number of writebacks
system.cpu0.icache.writebacks::total          5974428                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       351221                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       351221                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       351221                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       351221                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       351221                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       351221                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5975008                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      5975008                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      5975008                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      5975008                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      5975008                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      5975008                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  63931230447                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  63931230447                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  63931230447                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  63931230447                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  63931230447                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  63931230447                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2027158498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2027158498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2027158498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2027158498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027254                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027254                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027254                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.027254                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027254                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.027254                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10699.773196                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10699.773196                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10699.773196                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10699.773196                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10699.773196                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10699.773196                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      8714333                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      8724211                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         8793                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1114037                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements         2711723                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15840.616895                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          10811538                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2727125                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            3.964445                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      2357982000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.308256                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    33.621063                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    19.237059                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data     0.000001                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   268.450517                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.947223                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002052                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001174                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.000000                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.016385                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.966835                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          381                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14929                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           75                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          118                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3           93                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           95                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           69                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          499                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1082                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5719                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5657                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1972                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.023254                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005615                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.911194                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       427199165                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      427199165                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       602660                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       185799                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        788459                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      4096903                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      4096903                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      8161916                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      8161916                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data           32                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total           32                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            5                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total            5                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       986017                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       986017                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5386829                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      5386829                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3255809                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      3255809                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       183461                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       183461                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       602660                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       185799                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      5386829                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      4241826                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       10417114                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       602660                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       185799                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      5386829                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      4241826                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      10417114                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        25200                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        12620                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        37820                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       257381                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       257381                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       186815                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       186815                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       295278                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       295278                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       588130                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       588130                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1045192                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1045192                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       617837                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       617837                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        25200                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker        12620                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       588130                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1340470                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1966420                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        25200                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker        12620                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       588130                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1340470                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1966420                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    896455000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    597646500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   1494101500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    982091000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    982091000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    295025000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    295025000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2003000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2003000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  18413910498                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  18413910498                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22335302000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22335302000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  43094995483                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  43094995483                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data       882000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total       882000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    896455000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    597646500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22335302000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  61508905981                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  85338309481                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    896455000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    597646500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22335302000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  61508905981                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  85338309481                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       627860                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       198419                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       826279                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4096903                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      4096903                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      8161916                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      8161916                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       257413                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       257413                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       186820                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       186820                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1281295                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1281295                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5974959                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      5974959                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4301001                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      4301001                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       801298                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       801298                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       627860                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       198419                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5974959                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5582296                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     12383534                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       627860                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       198419                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5974959                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5582296                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     12383534                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.040136                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.063603                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.045771                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999876                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999876                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999973                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999973                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.230453                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.230453                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.098432                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.098432                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.243011                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.243011                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.771045                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.771045                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.040136                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.063603                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.098432                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.240129                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.158793                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.040136                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.063603                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.098432                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.240129                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.158793                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35573.611111                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47357.091918                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39505.592279                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3815.709007                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3815.709007                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1579.236143                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1579.236143                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       400600                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       400600                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62361.268019                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62361.268019                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37976.811249                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37976.811249                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41231.654551                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41231.654551                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data     1.427561                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total     1.427561                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35573.611111                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47357.091918                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37976.811249                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45886.074273                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 43397.803867                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35573.611111                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47357.091918                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37976.811249                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45886.074273                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 43397.803867                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs         1100                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs              24                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    45.833333                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           49027                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks      1747264                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1747264                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker          192                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          348                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          540                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        21118                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total        21118                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            4                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            4                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5796                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5796                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           13                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total           13                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker          192                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          348                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            4                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        26914                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        27458                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker          192                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          348                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            4                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        26914                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        27458                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        25008                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        12272                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        37280                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       914694                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       914694                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       257381                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       257381                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       186815                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       186815                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       274160                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       274160                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       588126                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       588126                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1039396                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1039396                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       617824                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       617824                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        25008                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        12272                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       588126                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1313556                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1938962                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        25008                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        12272                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       588126                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1313556                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       914694                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2853656                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        29615                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        50908                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        29691                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        29691                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        59306                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        80599                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    742635500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    518427500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1261063000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  57180143123                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  57180143123                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4798228494                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4798228494                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2893409994                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2893409994                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1691000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1691000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  13686705498                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  13686705498                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  18806492000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  18806492000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  36387650483                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  36387650483                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  21673087497                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  21673087497                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    742635500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    518427500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  18806492000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  50074355981                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  70141910981                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    742635500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    518427500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  18806492000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  50074355981                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  57180143123                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 127322054104                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1867460000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5357476000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7224936000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1867460000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5357476000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7224936000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.039831                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.061849                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.045118                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999876                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999876                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999973                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999973                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.213971                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.213971                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.098432                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.098432                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.241664                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.241664                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.771029                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.771029                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.039831                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.061849                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.098432                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.235307                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.156576                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.039831                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.061849                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.098432                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.235307                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.230440                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33826.797210                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62512.865639                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18642.512439                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18642.512439                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15488.103172                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15488.103172                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       338200                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       338200                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 49922.328195                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 49922.328195                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31976.977722                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31976.977722                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35008.457299                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35008.457299                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35079.711207                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35079.711207                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31976.977722                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38121.219028                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36174.979696                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31976.977722                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38121.219028                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44617.169730                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180904.136417                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141921.426888                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90336.154858                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89640.516632                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests     25418604                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     13061865                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         3409                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       690419                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       690321                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops           98                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        966476                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     11336947                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        29691                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        29691                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5857040                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      8164049                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      1344034                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1151380                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       469212                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       335795                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       509398                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           66                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          113                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1315239                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1289150                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5975008                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5298799                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       872203                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       802449                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     17966980                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20229549                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       416579                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1325266                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         39938374                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    765101392                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    766341777                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1587352                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5022880                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1538053401                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    5977120                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic            119917960                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples     19518051                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.053731                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.225509                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          18469421     94.63%     94.63% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           1048532      5.37%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                98      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      19518051                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   25305808947                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    186983903                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   8989974042                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   9049403091                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    218640527                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    698295209                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              130931248                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         87112041                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          6567659                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            91792654                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               56129151                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            61.147759                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               17311793                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            174850                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        4346649                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           2655837                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses         1690812                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted       417178                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   551219                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               551219                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11436                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        86181                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       255688                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       295531                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2259.422869                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 13315.556253                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       293454     99.30%     99.30% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1395      0.47%     99.77% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607          424      0.14%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143          158      0.05%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679           50      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           38      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       295531                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       283173                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 21265.600887                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18470.492322                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 14814.339876                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       281324     99.35%     99.35% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1404      0.50%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          195      0.07%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143          146      0.05%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           42      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           27      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           10      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359           13      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       283173                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 475307081088                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.614132                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.549956                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 474122952588     99.75%     99.75% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3    603814500      0.13%     99.88% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5    247441500      0.05%     99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7    130616500      0.03%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9     93327500      0.02%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11     62495500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13     19627500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15     26354000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       445000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19         6500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 475307081088                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        86181     88.28%     88.28% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        11436     11.72%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        97617                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       551219                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       551219                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        97617                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        97617                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       648836                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    95947338                       # DTB read hits
system.cpu1.dtb.read_misses                    376138                       # DTB read misses
system.cpu1.dtb.write_hits                   79464123                       # DTB write hits
system.cpu1.dtb.write_misses                   175081                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              44658                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   35142                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      372                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  6075                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    39563                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                96323476                       # DTB read accesses
system.cpu1.dtb.write_accesses               79639204                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        175411461                       # DTB hits
system.cpu1.dtb.misses                         551219                       # DTB misses
system.cpu1.dtb.accesses                    175962680                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    82567                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                82567                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          985                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        60088                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore         9957                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        72610                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean   937.467291                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  7808.036609                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-65535        72461     99.79%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-131071          121      0.17%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-196607           15      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-262143            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-327679            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        72610                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        71030                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 24890.468816                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 22675.930059                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 19295.215598                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        70173     98.79%     98.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          554      0.78%     99.57% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          204      0.29%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           35      0.05%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           20      0.03%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215            8      0.01%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            5      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359           25      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        71030                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 397994478260                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.871343                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.334985                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    51225264788     12.87%     12.87% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   346750110472     87.12%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       17741500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        1276000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4          85500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 397994478260                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        60088     98.39%     98.39% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          985      1.61%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        61073                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        82567                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        82567                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        61073                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        61073                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       143640                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   204871540                       # ITB inst hits
system.cpu1.itb.inst_misses                     82567                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              44658                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   24862                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   205327                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               204954107                       # ITB inst accesses
system.cpu1.itb.hits                        204871540                       # DTB hits
system.cpu1.itb.misses                          82567                       # DTB misses
system.cpu1.itb.accesses                    204954107                       # DTB accesses
system.cpu1.numPwrStateTransitions              10338                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         5169                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    9100042413.076223                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   142913287882.442078                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3563     68.93%     68.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         1580     30.57%     99.50% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.04%     99.54% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            5      0.10%     99.63% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            2      0.04%     99.67% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11            1      0.02%     99.69% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11            1      0.02%     99.71% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.02%     99.73% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           14      0.27%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 7390880676264                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           5169                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   346821221809                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 47038119233191                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       693644050                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          87527745                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     578391241                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  130931248                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          76096781                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    569305331                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               14062296                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   1768387                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles              291884                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles      5735168                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       727906                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles       800824                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                204645173                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              1664411                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  27214                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         673188393                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.008077                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.227099                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               348457754     51.76%     51.76% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1               126514971     18.79%     70.56% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                42536092      6.32%     76.87% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3               155679576     23.13%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           673188393                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.188759                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.833844                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles               102787429                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            312284706                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                218180532                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             34930241                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               5005485                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            18306368                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              2064498                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             600925596                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts             22793962                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               5005485                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               136395689                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               44912882                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     210797905                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                219085305                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             56991127                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             584399745                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts              6001663                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents              9489847                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                242679                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                273258                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              24369803                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents           10662                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          555653486                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            898470064                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       689649249                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           841085                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            500004101                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                55649379                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          14907079                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      13060204                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 70305418                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            96437745                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           82644936                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          8695524                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         7557089                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 562795340                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           15022202                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                566786483                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued          2618124                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       52408988                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     33720273                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        259964                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    673188393                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.841943                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.073212                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          363862102     54.05%     54.05% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1          129787759     19.28%     73.33% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2          109122281     16.21%     89.54% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           62914886      9.35%     98.89% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            7497321      1.11%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               4044      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      673188393                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu               57388953     44.23%     44.23% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 51651      0.04%     44.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                  16856      0.01%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMultAcc                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMisc                 103      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead              34250281     26.40%     70.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite             37595364     28.98%     99.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemRead            47943      0.04%     99.70% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemWrite          388183      0.30%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               11      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            385773007     68.06%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1187343      0.21%     68.27% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                69773      0.01%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  8      0.00%     68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                 13      0.00%     68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                 27      0.00%     68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMultAcc              0      0.00%     68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMisc             84205      0.01%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                2      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            98926523     17.45%     85.75% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           80304665     14.17%     99.92% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemRead          64060      0.01%     99.93% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemWrite        376846      0.07%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             566786483                       # Type of FU issued
system.cpu1.iq.rate                          0.817114                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                  129739334                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.228903                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1937625833                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        629808815                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    550243700                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1492982                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            556682                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       518492                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             695564416                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 961390                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         2525668                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     12072145                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        16264                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       139965                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      5400546                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      2506634                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      3911021                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               5005485                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                6180671                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1541266                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          577948873                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             96437745                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            82644936                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          12856669                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 62955                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              1418771                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        139965                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       1860771                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      3017279                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4878050                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            559031023                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             95939165                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          7216233                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       131331                       # number of nop insts executed
system.cpu1.iew.exec_refs                   175402489                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               104887487                       # Number of branches executed
system.cpu1.iew.exec_stores                  79463324                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.805934                       # Inst execution rate
system.cpu1.iew.wb_sent                     551451357                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    550762192                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                266030186                       # num instructions producing a value
system.cpu1.iew.wb_consumers                436524752                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.794013                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.609427                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       45696838                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       14762238                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4541996                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    664504904                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.790677                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.583374                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    434201366     65.34%     65.34% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1    119136384     17.93%     83.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     51278197      7.72%     90.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     17339439      2.61%     93.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     12299899      1.85%     95.45% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      8244778      1.24%     96.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5665589      0.85%     97.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3433584      0.52%     98.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     12905668      1.94%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    664504904                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           446004136                       # Number of instructions committed
system.cpu1.commit.committedOps             525408547                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     161609989                       # Number of memory references committed
system.cpu1.commit.loads                     84365599                       # Number of loads committed
system.cpu1.commit.membars                    3561329                       # Number of memory barriers committed
system.cpu1.commit.branches                  99629625                       # Number of branches committed
system.cpu1.commit.fp_insts                    509948                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                482210935                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            12864051                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       362699186     69.03%     69.03% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult         966499      0.18%     69.22% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           55760      0.01%     69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             8      0.00%     69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp            13      0.00%     69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt            21      0.00%     69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMultAcc            0      0.00%     69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMisc        77071      0.01%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       84306280     16.05%     85.29% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      76870874     14.63%     99.92% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemRead        59319      0.01%     99.93% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemWrite       373516      0.07%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        525408547                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             12905668                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1219098786                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1150856845                       # The number of ROB writes
system.cpu1.timesIdled                         925679                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       20455657                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 94076236903                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  446004136                       # Number of Instructions Simulated
system.cpu1.committedOps                    525408547                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.555241                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.555241                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.642987                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.642987                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               659945611                       # number of integer regfile reads
system.cpu1.int_regfile_writes              391450025                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   826837                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  461620                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                120567774                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               121287073                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1215585693                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              14957440                       # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements          5242137                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          459.717362                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          151071021                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5242649                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            28.815780                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8517875621500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   459.717362                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.897885                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.897885                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          393                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           29                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        335085452                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       335085452                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data     78683388                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       78683388                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     67788952                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      67788952                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       181257                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       181257                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       140156                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       140156                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1756750                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1756750                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1770273                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1770273                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    146612496                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       146612496                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    146793753                       # number of overall hits
system.cpu1.dcache.overall_hits::total      146793753                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      6126313                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      6126313                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      6911292                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      6911292                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       643081                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       643081                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       451908                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       451908                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       241040                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       241040                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       183733                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       183733                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data     13489513                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total      13489513                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data     14132594                       # number of overall misses
system.cpu1.dcache.overall_misses::total     14132594                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  94548549000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  94548549000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 128933568944                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 128933568944                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  10455217570                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  10455217570                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3390405500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   3390405500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4379858500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4379858500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2605000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2605000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 233937335514                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 233937335514                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 233937335514                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 233937335514                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     84809701                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     84809701                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     74700244                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     74700244                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       824338                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       824338                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       592064                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       592064                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1997790                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1997790                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1954006                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1954006                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    160102009                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    160102009                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    160926347                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    160926347                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.072236                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.072236                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.092520                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.092520                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.780118                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.780118                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.763276                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.763276                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.120653                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120653                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.094029                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.094029                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.084256                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.084256                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.087820                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.087820                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15433.189424                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15433.189424                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18655.494363                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18655.494363                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23135.721364                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23135.721364                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14065.738052                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14065.738052                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23838.170062                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23838.170062                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17342.163169                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17342.163169                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16553.035877                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16553.035877                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs      2644851                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets     20463296                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs           369952                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets         688434                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     7.149173                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    29.724412                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      5242162                       # number of writebacks
system.cpu1.dcache.writebacks::total          5242162                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3113636                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total      3113636                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5578267                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      5578267                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3659                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total         3659                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       125068                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total       125068                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      8695562                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      8695562                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      8695562                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      8695562                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3012677                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      3012677                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1333025                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1333025                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       643006                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       643006                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       448249                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       448249                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       115972                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       115972                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       183726                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       183726                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4793951                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4793951                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5436957                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5436957                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         8871                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         8871                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         8695                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         8695                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        17566                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        17566                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  42819104500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  42819104500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26001782801                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26001782801                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14897861000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14897861000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   9889085570                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total   9889085570                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1553813500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1553813500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4196193500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4196193500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2544000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2544000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  78709972871                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  78709972871                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  93607833871                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  93607833871                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1354957000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1354957000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1354957000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1354957000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035523                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035523                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017845                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017845                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.780027                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.780027                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.757096                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.757096                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058050                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.058050                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.094025                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.094025                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029943                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.029943                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033785                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033785                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14212.975536                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14212.975536                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19505.847828                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19505.847828                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23169.085514                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23169.085514                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22061.589808                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22061.589808                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13398.178008                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13398.178008                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22839.410318                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22839.410318                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16418.601874                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16418.601874                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17216.953136                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17216.953136                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152740.051854                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 152740.051854                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 77135.204372                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 77135.204372                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements          5955489                       # number of replacements
system.cpu1.icache.tags.tagsinuse          501.186843                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          198342876                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5956001                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            33.301350                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8518419495000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.186843                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.978881                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.978881                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           64                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        415232377                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       415232377                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst    198342876                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      198342876                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    198342876                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       198342876                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    198342876                       # number of overall hits
system.cpu1.icache.overall_hits::total      198342876                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      6295293                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      6295293                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      6295293                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       6295293                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      6295293                       # number of overall misses
system.cpu1.icache.overall_misses::total      6295293                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  67919445914                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  67919445914                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  67919445914                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  67919445914                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  67919445914                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  67919445914                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    204638169                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    204638169                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    204638169                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    204638169                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    204638169                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    204638169                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030763                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.030763                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030763                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.030763                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030763                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.030763                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10788.925299                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10788.925299                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10788.925299                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10788.925299                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10788.925299                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10788.925299                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs      9829448                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          701                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs           729519                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              3                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.473875                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets   233.666667                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      5955489                       # number of writebacks
system.cpu1.icache.writebacks::total          5955489                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       339254                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total       339254                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst       339254                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total       339254                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst       339254                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total       339254                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5956039                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5956039                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5956039                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5956039                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5956039                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5956039                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  61337721519                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  61337721519                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  61337721519                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  61337721519                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  61337721519                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  61337721519                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6801498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6801498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6801498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      6801498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.029105                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.029105                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.029105                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.029105                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.029105                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.029105                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10298.408308                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10298.408308                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10298.408308                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10298.408308                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10298.408308                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10298.408308                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101514.895522                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101514.895522                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7017688                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7023313                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit         5116                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       831383                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements         2042934                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       12933.505047                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          10254699                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2058843                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            4.980807                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12624.033726                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    36.418354                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    27.691890                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   245.361077                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.770510                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002223                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001690                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.014976                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.789399                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          293                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           63                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15553                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          116                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           99                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           69                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           44                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          197                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1807                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         7301                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4524                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1724                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.017883                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003845                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.949280                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       390440087                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      390440087                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       557579                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       186161                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        743740                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3343376                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3343376                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      7851276                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      7851276                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data           37                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total           37                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       859794                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       859794                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5412981                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      5412981                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2828036                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2828036                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       191737                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       191737                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       557579                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       186161                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      5412981                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3687830                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        9844551                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       557579                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       186161                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      5412981                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3687830                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       9844551                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        21615                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9433                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        31048                       # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks            1                       # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total            1                       # number of WritebackDirty misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       224939                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       224939                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       183720                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       183720                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       255308                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       255308                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       543023                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       543023                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       939708                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       939708                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       256512                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       256512                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        21615                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9433                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       543023                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1195016                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1769087                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        21615                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9433                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       543023                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1195016                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1769087                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    686942500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    338389000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1025331500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    939480500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    939480500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    264112000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    264112000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2448496                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2448496                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  12203061000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  12203061000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  19608835500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  19608835500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  34743736987                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  34743736987                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data       165000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total       165000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    686942500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    338389000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  19608835500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  46946797987                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  67580964987                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    686942500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    338389000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  19608835500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  46946797987                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  67580964987                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       579194                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       195594                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       774788                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3343377                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3343377                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      7851276                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      7851276                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       224976                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       224976                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       183720                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       183720                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1115102                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1115102                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5956004                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      5956004                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3767744                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3767744                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       448249                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       448249                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       579194                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       195594                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5956004                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4882846                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     11613638                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       579194                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       195594                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5956004                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4882846                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     11613638                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.037319                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.048227                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.040073                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000000                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000000                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999836                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999836                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.228955                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.228955                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.091172                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.091172                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.249409                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.249409                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.572253                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.572253                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.037319                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.048227                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.091172                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.244738                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.152328                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.037319                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.048227                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.091172                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.244738                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.152328                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31780.823502                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 35872.893035                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 33024.075625                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4176.601212                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4176.601212                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1437.578924                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1437.578924                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 408082.666667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 408082.666667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47797.409404                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47797.409404                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36110.506369                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36110.506369                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36972.907528                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36972.907528                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data     0.643245                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total     0.643245                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 31780.823502                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 35872.893035                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36110.506369                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39285.497422                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 38201.040982                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 31780.823502                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 35872.893035                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36110.506369                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39285.497422                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 38201.040982                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs          345                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               8                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    43.125000                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches           42412                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks      1137390                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1137390                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker           59                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          256                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          315                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        10963                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total        10963                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         3995                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         3995                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            3                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker           59                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          256                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data        14958                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        15274                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker           59                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          256                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data        14958                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        15274                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        21556                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9177                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        30733                       # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       745312                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       745312                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       224939                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       224939                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       183720                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       183720                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       244345                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       244345                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       543022                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       543022                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       935713                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       935713                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       256509                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       256509                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        21556                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9177                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       543022                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1180058                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1753813                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        21556                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9177                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       543022                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1180058                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       745312                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2499125                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         8871                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         8938                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         8695                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         8695                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        17566                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        17633                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    556465500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    279014500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    835480000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  36237678760                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  36237678760                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4227924487                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4227924487                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2815609497                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2815609497                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2082496                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2082496                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   9065423000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   9065423000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  16350690000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  16350690000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  28869020987                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  28869020987                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   5973751999                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   5973751999                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    556465500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    279014500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  16350690000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  37934443987                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  55120613987                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    556465500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    279014500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  16350690000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  37934443987                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  36237678760                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  91358292747                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6298000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1283792500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1290090500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      6298000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1283792500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1290090500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.037217                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.046919                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.039666                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.999836                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.999836                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.219123                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.219123                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.091172                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.091172                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.248348                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248348                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.572247                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.572247                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.037217                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.046919                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.091172                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.241674                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.151013                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.037217                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.046919                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.091172                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.241674                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.215189                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27185.110468                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48620.817537                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18795.871267                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18795.871267                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15325.547012                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15325.547012                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347082.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347082.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37100.914690                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37100.914690                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30110.548007                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30110.548007                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30852.431234                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30852.431234                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23288.664331                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23288.664331                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30110.548007                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32146.253817                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31429.014374                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30110.548007                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32146.253817                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36556.111738                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        94000                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144717.901026                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 144337.715373                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst        94000                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 73083.940567                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 73163.415187                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests     23228623                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11943528                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         5072                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       598776                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       598706                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops           70                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq        867379                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     10679013                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         8695                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         8695                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4499349                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      7854270                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      1254191                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       938082                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       428069                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       332128                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       468300                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           58                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          113                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1145370                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1120388                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5956039                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4785637                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       521245                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       449809                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     17867666                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16911297                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       409122                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1224107                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         36412192                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    762336624                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    654015560                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1564752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4633552                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1422550488                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5059056                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic             80617704                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples     17392868                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.053991                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.226018                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          16453876     94.60%     94.60% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            938922      5.40%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                70      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      17392868                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   23086793966                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    170580468                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   8939751182                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7774836803                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    213941664                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    645834647                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40408                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40408                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136658                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136658                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47776                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122710                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231342                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231342                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354132                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47796                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155817                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339384                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7339384                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7497287                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             37041003                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               331500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               13000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            24305002                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36394500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           570335330                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92783000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148038000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115667                       # number of replacements
system.iocache.tags.tagsinuse               11.289924                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115683                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9156457442000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.417343                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.872581                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.463584                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.242036                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.705620                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1041396                       # Number of tag accesses
system.iocache.tags.data_accesses             1041396                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8943                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8980                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115671                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115711                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115671                       # number of overall misses
system.iocache.overall_misses::total           115711                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5200000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1878808543                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1884008543                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       370000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       370000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13080956787                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13080956787                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5570000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  14959765330                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  14965335330                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5570000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  14959765330                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  14965335330                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8943                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8980                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115671                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115711                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115671                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115711                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 210087.056133                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 209800.505902                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123333.333333                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123333.333333                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 122563.495868                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 122563.495868                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139250                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 129330.301718                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 129333.730847                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139250                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 129330.301718                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 129333.730847                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         43850                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3467                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.647822                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8943                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8980                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115671                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115711                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115671                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115711                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3350000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1431658543                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1435008543                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       220000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       220000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7738901569                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7738901569                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3570000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9170560112                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9174130112                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3570000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9170560112                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9174130112                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160087.056133                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 159800.505902                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73333.333333                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73333.333333                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 72510.508667                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 72510.508667                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89250                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 79281.411175                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 79284.857205                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89250                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 79281.411175                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 79284.857205                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1625787                       # number of replacements
system.l2c.tags.tagsinuse                65181.204595                       # Cycle average of tags in use
system.l2c.tags.total_refs                    6817657                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1687923                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.039081                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               3083223500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    9617.868100                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   445.484302                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   525.919749                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4087.647415                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    22210.879235                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20823.279726                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    29.752566                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker    32.095436                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2691.005366                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3224.848807                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1492.423894                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.146757                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.006798                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.008025                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.062373                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.338911                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.317738                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000454                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000490                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.041061                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.049207                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.022773                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.994586                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        12119                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          287                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        49730                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2         1349                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          918                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9840                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          283                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          261                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2201                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4435                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        42789                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.184921                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.004379                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.758820                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 77430161                       # Number of tag accesses
system.l2c.tags.data_accesses                77430161                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks      2884653                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2884653                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          199415                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          166641                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              366056                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         54285                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         48308                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total            102593                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            52113                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            55927                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               108040                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        12524                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4903                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       523305                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       612159                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       287889                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        14056                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5296                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       496370                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       569933                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       304905                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2831340                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       116676                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       127973                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           244649                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker         12524                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4903                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              523305                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              664272                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       287889                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         14056                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5296                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              496370                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              625860                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       304905                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2939380                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        12524                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4903                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             523305                       # number of overall hits
system.l2c.overall_hits::cpu0.data             664272                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       287889                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        14056                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5296                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             496370                       # number of overall hits
system.l2c.overall_hits::cpu1.data             625860                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       304905                       # number of overall hits
system.l2c.overall_hits::total                2939380                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         23367                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         23265                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             46632                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          687                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          824                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1511                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          90180                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          49097                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139277                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3479                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3368                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        64819                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       175048                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       338569                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1814                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1250                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        46649                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       114016                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       201392                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         950404                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       450671                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data        82488                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         533159                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         3479                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         3368                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             64819                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            265228                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       338569                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1814                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1250                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             46649                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            163113                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       201392                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1089681                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         3479                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         3368                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            64819                       # number of overall misses
system.l2c.overall_misses::cpu0.data           265228                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       338569                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1814                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1250                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            46649                       # number of overall misses
system.l2c.overall_misses::cpu1.data           163113                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       201392                       # number of overall misses
system.l2c.overall_misses::total              1089681                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    136803000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    150683000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    287486000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      9622000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      7084500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total     16706500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   9842771994                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5304657999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  15147429993                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    352314500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    351549500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   7169242500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  19597785998                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  51686460606                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    196164500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    138775500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5424777500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  13175715998                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  30642096870                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 128734883472                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    352314500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    351549500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   7169242500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  29440557992                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  51686460606                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    196164500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    138775500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   5424777500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  18480373997                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  30642096870                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    143882313465                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    352314500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    351549500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   7169242500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  29440557992                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  51686460606                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    196164500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    138775500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   5424777500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  18480373997                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  30642096870                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   143882313465                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2884653                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2884653                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       222782                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       189906                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          412688                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        54972                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        49132                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        104104                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       142293                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       105024                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247317                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        16003                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         8271                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       588124                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       787207                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       626458                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        15870                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6546                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       543019                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       683949                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       506297                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3781744                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       567347                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       210461                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       777808                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        16003                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         8271                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          588124                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          929500                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       626458                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        15870                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6546                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          543019                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          788973                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       506297                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4029061                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        16003                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         8271                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         588124                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         929500                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       626458                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        15870                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6546                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         543019                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         788973                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       506297                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4029061                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.104887                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.122508                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.112996                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.012497                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.016771                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.014514                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.633763                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.467484                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.563152                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.217397                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.407206                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.110213                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.222366                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.540450                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.114304                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.190956                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.085907                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.166702                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.397774                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.251314                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.794348                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.391940                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.685464                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.217397                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.407206                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.110213                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.285345                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.540450                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.114304                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.190956                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.085907                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.206741                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.397774                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.270455                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.217397                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.407206                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.110213                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.285345                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.540450                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.114304                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.190956                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.085907                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.206741                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.397774                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.270455                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5854.538452                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6476.810660                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6164.993996                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14005.822416                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  8597.694175                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 11056.585043                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 109145.841583                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108044.442614                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 108757.583758                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101268.899109                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 104379.305226                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110604.028140                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111956.640453                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 108139.195149                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 111020.400000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 116289.255933                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115560.237142                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 135452.800569                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101268.899109                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 104379.305226                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 110604.028140                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 111000.942555                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 108139.195149                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 111020.400000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 116289.255933                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 113297.983588                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 132040.765568                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101268.899109                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 104379.305226                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 110604.028140                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 111000.942555                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 108139.195149                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 111020.400000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 116289.255933                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 113297.983588                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 132040.765568                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              7046                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       62                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs    113.645161                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1244548                       # number of writebacks
system.l2c.writebacks::total                  1244548                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          102                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           15                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          118                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           19                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          254                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            102                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             15                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            118                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             19                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                254                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           102                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            15                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           118                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            19                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               254                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        67228                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        67228                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        23367                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        23265                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        46632                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          687                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          824                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1511                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        90180                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        49097                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139277                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3479                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3368                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        64717                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       175033                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       338569                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1814                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1250                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        46531                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       113997                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       201392                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       950150                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       450671                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data        82488                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       533159                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         3479                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         3368                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        64717                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       265213                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       338569                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1814                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1250                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        46531                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       163094                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       201392                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1089427                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         3479                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         3368                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        64717                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       265213                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       338569                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1814                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1250                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        46531                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       163094                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       201392                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1089427                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        29615                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         8869                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        59844                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        29691                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         8695                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38386                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        59306                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        17564                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        98230                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    466632500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    483108499                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    949740999                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     16616499                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     20367500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     36983999                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   8940824795                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4813505389                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  13754330184                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    317523502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    317869500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   6512407062                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17845292687                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  48300635417                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    178023502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    126275001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   4948966536                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  12033347692                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  28627972330                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 119208313229                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  11145696799                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   1615953000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  12761649799                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    317523502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    317869500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   6512407062                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  26786117482                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  48300635417                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    178023502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    126275001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   4948966536                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  16846853081                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  28627972330                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 132962643413                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    317523502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    317869500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   6512407062                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  26786117482                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  48300635417                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    178023502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    126275001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   4948966536                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  16846853081                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  28627972330                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 132962643413                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1484185500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4824158502                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5090000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1123983502                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7437417504                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1484185500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4824158502                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5090000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1123983502                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   7437417504                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.104887                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.122508                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.112996                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.012497                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.016771                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.014514                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.633763                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.467484                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.563152                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.217397                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.407206                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.110040                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.222347                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.540450                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.114304                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.190956                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.085689                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.166675                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.397774                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.251247                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.794348                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.391940                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.685464                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.217397                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.407206                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.110040                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.285329                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.540450                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.114304                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.190956                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.085689                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.206717                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.397774                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.270392                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.217397                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.407206                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.110040                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.285329                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.540450                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.114304                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.190956                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.085689                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.206717                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.397774                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.270392                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19969.722258                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20765.463099                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20366.722401                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24187.043668                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24717.839806                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24476.504964                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 99144.209304                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98040.723242                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 98755.215750                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100629.001066                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101953.875481                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 106358.482216                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105558.459363                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 125462.625090                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24731.337936                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19590.158569                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23935.917426                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100629.001066                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100998.508678                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 106358.482216                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103295.357775                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 122048.235828                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100629.001066                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100998.508678                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 106358.482216                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103295.357775                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 122048.235828                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162895.779233                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126731.706168                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124280.086625                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81343.515024                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 63993.594967                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 75714.318477                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       4039865                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2364937                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3552                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               59844                       # Transaction distribution
system.membus.trans_dist::ReadResp            1018974                       # Transaction distribution
system.membus.trans_dist::WriteReq              38386                       # Transaction distribution
system.membus.trans_dist::WriteResp             38386                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1351242                       # Transaction distribution
system.membus.trans_dist::CleanEvict           267627                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           336754                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         267840                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
system.membus.trans_dist::ReadExReq            152823                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138565                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        959130                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        652932                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        30629                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122710                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25810                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4892821                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5041417                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237968                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237968                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5279385                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155817                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51620                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    149644096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    149852089                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7250176                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7250176                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               157102265                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           616817                       # Total snoops (count)
system.membus.snoopTraffic                     199808                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2467715                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.013862                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.116919                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2433507     98.61%     98.61% # Request fanout histogram
system.membus.snoop_fanout::1                   34208      1.39%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2467715                       # Request fanout histogram
system.membus.reqLayer0.occupancy            98169995                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               52000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21686998                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9247698101                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5871093052                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           81490219                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     12086303                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      6387551                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      2235502                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         239971                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       217052                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        22919                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              59846                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4613854                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38386                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38386                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      4129201                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2768870                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          702098                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        370433                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1072531                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          113                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          113                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           298786                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          298786                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4554900                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       905153                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       886862                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9925339                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7679367                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17604706                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    251196049                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    191962664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              443158713                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3147878                       # Total snoops (count)
system.toL2Bus.snoopTraffic                 132377296                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples          8556431                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.371457                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.488706                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5401002     63.12%     63.12% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                3132510     36.61%     99.73% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  22919      0.27%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            8556431                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         9443624545                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          9237873                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4533014073                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3814018472                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13606                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    5169                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------