1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
|
---------- Begin Simulation Statistics ----------
sim_seconds 47.305566 # Number of seconds simulated
sim_ticks 47305566199500 # Number of ticks simulated
final_tick 47305566199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 108918 # Simulator instruction rate (inst/s)
host_op_rate 128082 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5794473291 # Simulator tick rate (ticks/s)
host_mem_usage 707548 # Number of bytes of host memory used
host_seconds 8163.91 # Real time elapsed on the host
sim_insts 889196991 # Number of instructions simulated
sim_ops 1045647845 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 75776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 60928 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 4503136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 12909720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 13016640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 167424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 164416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2523040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 10482528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 14576384 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 439104 # Number of bytes read from this memory
system.physmem.bytes_read::total 58919096 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 4503136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2523040 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7026176 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 75116864 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 75137680 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1184 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 952 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 86314 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 201736 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 203385 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2616 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2569 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 39466 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 163804 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 227756 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6861 # Number of read requests responded to by this memory
system.physmem.num_reads::total 936643 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1173701 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1176304 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1602 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1288 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 95193 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 272901 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 275161 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 3539 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 3476 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 53335 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 221592 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 308133 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9282 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1245500 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 95193 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 53335 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 148527 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1587908 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 440 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1588348 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1587908 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1602 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1288 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 95193 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 273341 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 275161 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 3539 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 3476 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 53335 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 221592 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 308133 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9282 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2833848 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 936643 # Number of read requests accepted
system.physmem.writeReqs 1837953 # Number of write requests accepted
system.physmem.readBursts 936643 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1837953 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 59924608 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue
system.physmem.bytesWritten 114470976 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 58919096 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 117483216 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 49325 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 117374 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 55305 # Per bank write bursts
system.physmem.perBankRdBursts::1 59995 # Per bank write bursts
system.physmem.perBankRdBursts::2 52034 # Per bank write bursts
system.physmem.perBankRdBursts::3 56018 # Per bank write bursts
system.physmem.perBankRdBursts::4 58058 # Per bank write bursts
system.physmem.perBankRdBursts::5 68871 # Per bank write bursts
system.physmem.perBankRdBursts::6 59545 # Per bank write bursts
system.physmem.perBankRdBursts::7 57406 # Per bank write bursts
system.physmem.perBankRdBursts::8 51483 # Per bank write bursts
system.physmem.perBankRdBursts::9 77850 # Per bank write bursts
system.physmem.perBankRdBursts::10 53930 # Per bank write bursts
system.physmem.perBankRdBursts::11 57982 # Per bank write bursts
system.physmem.perBankRdBursts::12 54532 # Per bank write bursts
system.physmem.perBankRdBursts::13 56851 # Per bank write bursts
system.physmem.perBankRdBursts::14 60976 # Per bank write bursts
system.physmem.perBankRdBursts::15 55486 # Per bank write bursts
system.physmem.perBankWrBursts::0 110085 # Per bank write bursts
system.physmem.perBankWrBursts::1 112883 # Per bank write bursts
system.physmem.perBankWrBursts::2 108062 # Per bank write bursts
system.physmem.perBankWrBursts::3 109070 # Per bank write bursts
system.physmem.perBankWrBursts::4 113169 # Per bank write bursts
system.physmem.perBankWrBursts::5 118310 # Per bank write bursts
system.physmem.perBankWrBursts::6 115499 # Per bank write bursts
system.physmem.perBankWrBursts::7 111959 # Per bank write bursts
system.physmem.perBankWrBursts::8 107874 # Per bank write bursts
system.physmem.perBankWrBursts::9 113071 # Per bank write bursts
system.physmem.perBankWrBursts::10 109141 # Per bank write bursts
system.physmem.perBankWrBursts::11 113654 # Per bank write bursts
system.physmem.perBankWrBursts::12 105244 # Per bank write bursts
system.physmem.perBankWrBursts::13 111328 # Per bank write bursts
system.physmem.perBankWrBursts::14 115976 # Per bank write bursts
system.physmem.perBankWrBursts::15 113284 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 81608 # Number of times write queue was full causing retry
system.physmem.totGap 47305564753000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 37 # Read request sizes (log2)
system.physmem.readPktSize::4 21333 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 915273 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2601 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1835350 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 429452 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 211261 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 82392 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 54481 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 35792 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 29912 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 27031 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 25347 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 22393 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 8038 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 3479 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 2226 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1304 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1011 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 581 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 510 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 459 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 145 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 106 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 25942 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 31294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 42762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 50992 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 57625 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 67617 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 67331 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 70370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 78632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 77296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 79817 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 88544 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 82050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 81883 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 102987 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 87472 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 82523 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 74776 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 11408 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 9295 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 8921 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 9951 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 10393 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 8748 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 8966 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 9255 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 8034 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 7640 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 7450 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 7439 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 6226 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 5791 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 5896 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 5137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 4222 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 3205 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 3127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 2893 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 3002 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 2681 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 2695 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 2825 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 2650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 2954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 3512 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 4384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 7063 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 7984 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 354953 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 953575 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 182.885667 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 110.719338 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 252.430373 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 592274 62.11% 62.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 190618 19.99% 82.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 51298 5.38% 87.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 22604 2.37% 89.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 16941 1.78% 91.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 10334 1.08% 92.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7600 0.80% 93.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 7080 0.74% 94.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 54826 5.75% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 953575 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 60764 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 15.409042 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 72.355469 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 60757 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 60764 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 60764 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 29.435340 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 19.473917 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 995.068690 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-4095 60761 100.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::98304-102399 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::102400-106495 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192512-196607 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 60764 # Writes before turning the bus around for reads
system.physmem.totQLat 43948740923 # Total ticks spent queuing
system.physmem.totMemAccLat 61504778423 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4681610000 # Total ticks spent in databus transfers
system.physmem.avgQLat 46937.64 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 65687.64 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.25 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.48 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.58 # Average write queue length when enqueuing
system.physmem.readRowHits 706637 # Number of row buffer hits during reads
system.physmem.writeRowHits 1064717 # Number of row buffer hits during writes
system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 59.53 # Row buffer hit rate for writes
system.physmem.avgGap 17049532.53 # Average gap between requests
system.physmem.pageHitRate 65.01 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3636465840 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1984182750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 3644362800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 5825759760 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1155369631905 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27369856613250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31630086518865 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.633528 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45532077679143 # Time in different power states
system.physmem_0.memoryStateTime::REF 1579636760000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 193851315857 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3572561160 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1949314125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 3658902000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 5764426560 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1152447208560 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27372420142500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31629582057465 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.622864 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45536350688414 # Time in different power states
system.physmem_1.memoryStateTime::REF 1579636760000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 189577142836 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 136259129 # Number of BP lookups
system.cpu0.branchPred.condPredicted 90543195 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 6799058 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 95853282 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 62504832 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 65.208860 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 18504887 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 186011 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 520196 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 520196 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10690 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 81668 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 225929 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 294267 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 1575.669375 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 10064.565371 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 292845 99.52% 99.52% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 1067 0.36% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 263 0.09% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 47 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 294267 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 252771 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 15945.045037 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 13637.155107 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 11018.196964 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767 241135 95.40% 95.40% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10520 4.16% 99.56% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303 548 0.22% 99.78% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071 339 0.13% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839 68 0.03% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607 47 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-229375 65 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::360448-393215 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 252771 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 499007353192 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.597965 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.527283 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 498187132192 99.84% 99.84% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 450171500 0.09% 99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 169118500 0.03% 99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 80846500 0.02% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 62229500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 34680000 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 10096500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 12800000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 278500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 499007353192 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 81668 88.43% 88.43% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 10690 11.57% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 92358 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 520196 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 520196 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92358 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92358 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 612554 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 98496070 # DTB read hits
system.cpu0.dtb.read_misses 369414 # DTB read misses
system.cpu0.dtb.write_hits 81551465 # DTB write hits
system.cpu0.dtb.write_misses 150782 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 36102 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 400 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 5365 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 40284 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 98865484 # DTB read accesses
system.cpu0.dtb.write_accesses 81702247 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 180047535 # DTB hits
system.cpu0.dtb.misses 520196 # DTB misses
system.cpu0.dtb.accesses 180567731 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 81590 # Table walker walks requested
system.cpu0.itb.walker.walksLong 81590 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 901 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59909 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 9188 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 72402 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 845.170023 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 6470.995618 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767 72024 99.48% 99.48% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535 242 0.33% 99.81% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303 56 0.08% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071 61 0.08% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 72402 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 69998 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 20035.793294 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 17827.568317 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 13688.582598 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 69301 99.00% 99.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 578 0.83% 99.83% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 67 0.10% 99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 29 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 69998 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 370135740312 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.825869 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.379347 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 64468447528 17.42% 17.42% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 305652352784 82.58% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 13699000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 1205500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 370135740312 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 59909 98.52% 98.52% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 901 1.48% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 60810 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81590 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81590 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60810 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60810 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 142400 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 213929001 # ITB inst hits
system.cpu0.itb.inst_misses 81590 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 25953 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 203878 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 214010591 # ITB inst accesses
system.cpu0.itb.hits 213929001 # DTB hits
system.cpu0.itb.misses 81590 # DTB misses
system.cpu0.itb.accesses 214010591 # DTB accesses
system.cpu0.numCycles 728554790 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 88185009 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 601844339 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 136259129 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 81009719 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 601618645 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 14617520 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 1590376 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 274448 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 5655980 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 730298 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 721373 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 213725526 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 1720356 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 27419 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 706084889 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.998504 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.224315 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 368651970 52.21% 52.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 130906496 18.54% 70.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 45457211 6.44% 77.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 161069212 22.81% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 706084889 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.187027 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.826080 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 103877352 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 333585554 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 228251571 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 35190646 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5179766 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 19720762 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 2170804 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 623516514 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 23718954 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5179766 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 138234059 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 46790455 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 227164838 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 228535971 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 60179800 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 606373965 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 6065859 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 8641063 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 231610 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 454065 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 27284745 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 11061 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 577786095 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 931076470 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 716156173 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 752358 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 519674265 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 58111818 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 14452887 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 12546195 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 71496186 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 99205558 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 84922074 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 8773729 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 7651066 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 585335843 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 14506928 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 587846614 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 2739409 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 54557687 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 35502721 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 263475 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 706084889 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.832544 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.074450 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 387752647 54.92% 54.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 129908491 18.40% 73.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 115071565 16.30% 89.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 65618038 9.29% 98.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 7729861 1.09% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 4287 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 706084889 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 62081849 46.00% 46.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 53806 0.04% 46.04% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 26012 0.02% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 10 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 46.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 34882864 25.85% 71.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 37902238 28.09% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 401971331 68.38% 68.38% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1424969 0.24% 68.62% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 76351 0.01% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 44028 0.01% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 101506921 17.27% 85.91% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 82822965 14.09% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 587846614 # Type of FU issued
system.cpu0.iq.rate 0.806867 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 134946779 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.229561 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 2018256641 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 654059965 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 571438682 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1207660 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 478909 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 443638 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 722040340 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 753051 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 2688850 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 12347690 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 15246 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 139538 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 5796061 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 2638151 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 4049170 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 5179766 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 6081153 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 2925805 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 599957845 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 99205558 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 84922074 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 12284210 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 51884 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 2819346 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 139538 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 2067264 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 2909526 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 4976790 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 580052597 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 98485742 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 7283117 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 115074 # number of nop insts executed
system.cpu0.iew.exec_refs 180036231 # number of memory reference insts executed
system.cpu0.iew.exec_branches 109604684 # Number of branches executed
system.cpu0.iew.exec_stores 81550489 # Number of stores executed
system.cpu0.iew.exec_rate 0.796169 # Inst execution rate
system.cpu0.iew.wb_sent 572646335 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 571882320 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 278067639 # num instructions producing a value
system.cpu0.iew.wb_consumers 456095391 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.784954 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.609670 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 47584416 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 14243453 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4670064 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 697066716 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.782257 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.580851 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 460295975 66.03% 66.03% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 120461861 17.28% 83.31% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 53495228 7.67% 90.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 18161397 2.61% 93.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 13064824 1.87% 95.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 8746806 1.25% 96.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 5864289 0.84% 97.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3641188 0.52% 98.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 13335148 1.91% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 697066716 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 464477894 # Number of instructions committed
system.cpu0.commit.committedOps 545285068 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 165983876 # Number of memory references committed
system.cpu0.commit.loads 86857868 # Number of loads committed
system.cpu0.commit.membars 3594521 # Number of memory barriers committed
system.cpu0.commit.branches 103961213 # Number of branches committed
system.cpu0.commit.fp_insts 434735 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 500421802 # Number of committed integer instructions.
system.cpu0.commit.function_calls 13758946 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 378032624 69.33% 69.33% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1169798 0.21% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 60419 0.01% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 38309 0.01% 69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 86857868 15.93% 85.49% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 79126008 14.51% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 545285068 # Class of committed instruction
system.cpu0.commit.bw_lim_events 13335148 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 1272468420 # The number of ROB reads
system.cpu0.rob.rob_writes 1194722923 # The number of ROB writes
system.cpu0.timesIdled 998377 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 22469901 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 93882577668 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 464477894 # Number of Instructions Simulated
system.cpu0.committedOps 545285068 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.568546 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.568546 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.637533 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.637533 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 684802624 # number of integer regfile reads
system.cpu0.int_regfile_writes 407591789 # number of integer regfile writes
system.cpu0.fp_regfile_reads 737398 # number of floating regfile reads
system.cpu0.fp_regfile_writes 323628 # number of floating regfile writes
system.cpu0.cc_regfile_reads 126081114 # number of cc regfile reads
system.cpu0.cc_regfile_writes 126833812 # number of cc regfile writes
system.cpu0.misc_regfile_reads 2842254449 # number of misc regfile reads
system.cpu0.misc_regfile_writes 14406777 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 5807270 # number of replacements
system.cpu0.dcache.tags.tagsinuse 503.185727 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 154700200 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 5807781 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 26.636714 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 1931738500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.185727 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.982785 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.982785 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 344453115 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 344453115 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 80805507 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 80805507 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 69071717 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 69071717 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209524 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 209524 # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 255543 # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total 255543 # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1772811 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1772811 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798532 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1798532 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 149877224 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 149877224 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 150086748 # number of overall hits
system.cpu0.dcache.overall_hits::total 150086748 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 6456855 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 6456855 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 6956516 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 6956516 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 664764 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 664764 # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 829133 # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total 829133 # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 256042 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 256042 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194087 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 194087 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 13413371 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 13413371 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 14078135 # number of overall misses
system.cpu0.dcache.overall_misses::total 14078135 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92345367100 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 92345367100 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 122121346040 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 122121346040 # number of WriteReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 37689944158 # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 37689944158 # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3513328512 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3513328512 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4123602814 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4123602814 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5259500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5259500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 214466713140 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 214466713140 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 214466713140 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 214466713140 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 87262362 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 87262362 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 76028233 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 76028233 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 874288 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 874288 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1084676 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total 1084676 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2028853 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2028853 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1992619 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 1992619 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 163290595 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 163290595 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 164164883 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 164164883 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073994 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.073994 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.091499 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.091499 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760349 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760349 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.764406 # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.764406 # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.126200 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.126200 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097403 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097403 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082144 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.082144 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085756 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.085756 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14301.911240 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14301.911240 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17554.957976 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17554.957976 # average WriteReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 45457.054728 # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 45457.054728 # average WriteInvalidateReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13721.688286 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13721.688286 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21246.156693 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21246.156693 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15989.024171 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15989.024171 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15234.028736 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15234.028736 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 10974284 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 17020056 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 751732 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 670987 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.598665 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 25.365702 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 3967066 # number of writebacks
system.cpu0.dcache.writebacks::total 3967066 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3312893 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 3312893 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5560546 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 5560546 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4546 # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4546 # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 132684 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 132684 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 8873439 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 8873439 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 8873439 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 8873439 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3143962 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3143962 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1395970 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1395970 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 657971 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 657971 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 824587 # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 824587 # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123358 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123358 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194072 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 194072 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4539932 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4539932 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5197903 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 5197903 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41375173894 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41375173894 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26017592924 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26017592924 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14556234769 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14556234769 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36285250520 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 36285250520 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1556312588 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1556312588 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3823478686 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3823478686 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5096000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5096000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 67392766818 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 67392766818 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81949001587 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 81949001587 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5745168998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5745168998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5504162016 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5504162016 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11249331014 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11249331014 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036029 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036029 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018361 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018361 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752579 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752579 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.760215 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.760215 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060802 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060802 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097395 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097395 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027803 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027803 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031663 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.031663 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13160.201648 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13160.201648 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18637.644737 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18637.644737 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22122.912361 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22122.912361 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 44004.150587 # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 44004.150587 # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12616.227468 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12616.227468 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19701.341183 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19701.341183 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14844.444106 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14844.444106 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15765.781237 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15765.781237 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 6071622 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.960367 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 207290998 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 6072134 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 34.138080 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 14063099250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960367 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999923 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999923 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 329 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 92 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 433467798 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 433467798 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 207290998 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 207290998 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 207290998 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 207290998 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 207290998 # number of overall hits
system.cpu0.icache.overall_hits::total 207290998 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 6406823 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 6406823 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 6406823 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 6406823 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 6406823 # number of overall misses
system.cpu0.icache.overall_misses::total 6406823 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 67980327142 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 67980327142 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 67980327142 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 67980327142 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 67980327142 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 67980327142 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 213697821 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 213697821 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 213697821 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 213697821 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 213697821 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 213697821 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029981 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.029981 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029981 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.029981 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029981 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.029981 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10610.614206 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10610.614206 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10610.614206 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10610.614206 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 9344678 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 782 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 720412 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.971297 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 78.200000 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 334667 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 334667 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 334667 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 334667 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 334667 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 334667 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6072156 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 6072156 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 6072156 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 6072156 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 6072156 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 6072156 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 58462486516 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 58462486516 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 58462486516 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 58462486516 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 58462486516 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 58462486516 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1881164498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1881164498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028415 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.028415 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.028415 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9627.961883 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 9627.961883 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 9627.961883 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7322641 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 7635134 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 270741 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 993362 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 2579397 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16158.447303 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 12271567 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2594941 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 4.729035 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 2266482500 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 5660.592746 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 40.404376 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 30.912164 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5710.050306 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3705.001610 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1011.486101 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.345495 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002466 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001887 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.348514 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.226135 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.061736 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.986233 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1380 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 93 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14071 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 414 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 620 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 688 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5473 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2257 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5451 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.084229 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005676 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.858826 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 277998240 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 277998240 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 501930 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167379 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5436143 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data 2922103 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 9027555 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 3967054 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 3967054 # number of Writeback hits
system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 228126 # number of WriteInvalidateReq hits
system.cpu0.l2cache.WriteInvalidateReq_hits::total 228126 # number of WriteInvalidateReq hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 108640 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 108640 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33975 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 33975 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 890755 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 890755 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 501930 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 167379 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 5436143 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3812858 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 9918310 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 501930 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 167379 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 5436143 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 3812858 # number of overall hits
system.cpu0.l2cache.overall_hits::total 9918310 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10652 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8152 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 635995 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data 1000489 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 1655288 # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks 10 # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total 10 # number of Writeback misses
system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 594866 # number of WriteInvalidateReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::total 594866 # number of WriteInvalidateReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 133117 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 133117 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160078 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 160078 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 19 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 19 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 274591 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 274591 # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10652 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8152 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 635995 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1275080 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 1929879 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10652 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8152 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 635995 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1275080 # number of overall misses
system.cpu0.l2cache.overall_misses::total 1929879 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 338313980 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 267505335 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 19973277607 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 34240699717 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 54819796639 # number of ReadReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 238254135 # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 238254135 # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2940744545 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 2940744545 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3318665043 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3318665043 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4985998 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4985998 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14040093164 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 14040093164 # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 338313980 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 267505335 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 19973277607 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 48280792881 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 68859889803 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 338313980 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 267505335 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 19973277607 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 48280792881 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 68859889803 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 512582 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175531 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6072138 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3922592 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 10682843 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 3967064 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 3967064 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 822992 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::total 822992 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 241757 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 241757 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194053 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 194053 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 19 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 19 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1165346 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1165346 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 512582 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175531 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 6072138 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 5087938 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 11848189 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 512582 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175531 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 6072138 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 5087938 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 11848189 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046442 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.104740 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.255058 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.154948 # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.722809 # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.722809 # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.550623 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.550623 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.824919 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.824919 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.235630 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.235630 # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046442 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.104740 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.250608 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.162884 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046442 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.104740 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.250608 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.162884 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 32814.687807 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31404.771432 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34223.964199 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33117.981064 # average ReadReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 400.517318 # average WriteInvalidateReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 400.517318 # average WriteInvalidateReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22091.427429 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22091.427429 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20731.549888 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20731.549888 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 262420.947368 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 262420.947368 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 51130.929870 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 51130.929870 # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 32814.687807 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31404.771432 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37864.912696 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 35680.936371 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 32814.687807 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31404.771432 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37864.912696 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 35680.936371 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 1389796 # number of writebacks
system.cpu0.l2cache.writebacks::total 1389796 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 142 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 4324 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 4477 # number of ReadReq MSHR hits
system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 6 # number of WriteInvalidateReq MSHR hits
system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 6 # number of WriteInvalidateReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 17304 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 17304 # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 142 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 21628 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 21781 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 142 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 21628 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 21781 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10648 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8010 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 635988 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 996165 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 1650811 # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks 10 # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total 10 # number of Writeback MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 695022 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 695022 # number of HardPFReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 594860 # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 594860 # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 133117 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 133117 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 160078 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 160078 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 19 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 19 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 257287 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 257287 # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10648 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8010 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 635988 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1253452 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 1908098 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10648 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8010 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 635988 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1253452 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 695022 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 2603120 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 209265519 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 15816568891 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 27389377929 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 43683913367 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34637549956 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 34637549956 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 28746452436 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 28746452436 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2662823288 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2662823288 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2368378420 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2368378420 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4277498 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4277498 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10397244749 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10397244749 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 209265519 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15816568891 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37786622678 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 54081158116 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 209265519 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15816568891 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37786622678 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34637549956 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 88718708072 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5486110502 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7197622502 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5256416460 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5256416460 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10742526962 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12454038962 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.253956 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.154529 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.722802 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.722802 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.550623 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.550623 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.824919 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824919 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220782 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220782 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.161046 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219706 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27494.820566 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26462.092491 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49836.623813 # average HardPFReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48324.735965 # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48324.735965 # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20003.630551 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20003.630551 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14795.152488 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14795.152488 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 225131.473684 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 225131.473684 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40411.076926 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40411.076926 # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28342.966722 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34081.682009 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 13109671 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 10998966 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 32265 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 32265 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 3967064 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 987402 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1170476 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 822992 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 487373 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355558 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 509064 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1297704 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1174184 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12186882 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16978089 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390292 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1142423 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 30697686 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 388957536 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 639747662 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404248 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4100656 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1034210102 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 4435865 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 21321710 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 3.191876 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.393776 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 17230589 80.81% 80.81% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 4091121 19.19% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 21321710 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 13464993223 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 208995484 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 9149850308 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 8376078494 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 215375806 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 630757127 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 124182653 # Number of BP lookups
system.cpu1.branchPred.condPredicted 82299269 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 6251064 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 87493813 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 57426824 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 65.635297 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 17076023 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 176220 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 534049 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 534049 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11595 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85531 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 242787 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 291262 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2048.229773 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 11850.953616 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535 289126 99.27% 99.27% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071 1672 0.57% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607 329 0.11% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679 62 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 291262 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 270383 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 17183.802917 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 14328.415565 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16454.576356 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 267229 98.83% 98.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2235 0.83% 99.66% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 352 0.13% 99.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 368 0.14% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 149 0.06% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 270383 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 438879688048 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.596096 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.540539 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 437883178548 99.77% 99.77% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3 543837500 0.12% 99.90% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5 218551000 0.05% 99.95% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7 91365500 0.02% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9 75836500 0.02% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11 38561500 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13 12555000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15 15271000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17 530000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 438879688048 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 85532 88.06% 88.06% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 11595 11.94% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 97127 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 534049 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 534049 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97127 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97127 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 631176 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 91849877 # DTB read hits
system.cpu1.dtb.read_misses 382442 # DTB read misses
system.cpu1.dtb.write_hits 75119650 # DTB write hits
system.cpu1.dtb.write_misses 151607 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 39274 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 401 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 5573 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 36948 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 92232319 # DTB read accesses
system.cpu1.dtb.write_accesses 75271257 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 166969527 # DTB hits
system.cpu1.dtb.misses 534049 # DTB misses
system.cpu1.dtb.accesses 167503576 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 85651 # Table walker walks requested
system.cpu1.itb.walker.walksLong 85651 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 898 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61483 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 9913 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 75738 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1212.145818 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 8774.873802 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767 75006 99.03% 99.03% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535 365 0.48% 99.52% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303 180 0.24% 99.75% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071 161 0.21% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 75738 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 72294 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 21947.554182 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 18825.235250 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 19960.579515 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 70492 97.51% 97.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 1482 2.05% 99.56% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 157 0.22% 99.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 99 0.14% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 72294 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 404519897680 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.847972 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.359205 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 61519279012 15.21% 15.21% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 342981503668 84.79% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 17484500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 1520000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 101500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5 9000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 404519897680 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 61483 98.56% 98.56% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 898 1.44% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 62381 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85651 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85651 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62381 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62381 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 148032 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 196330607 # ITB inst hits
system.cpu1.itb.inst_misses 85651 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 28544 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 219679 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 196416258 # ITB inst accesses
system.cpu1.itb.hits 196330607 # DTB hits
system.cpu1.itb.misses 85651 # DTB misses
system.cpu1.itb.accesses 196416258 # DTB accesses
system.cpu1.numCycles 659201565 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 81623724 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 551229784 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 124182653 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 74502847 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 545141022 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 13475474 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 1814701 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 236397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 6195125 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 729177 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 658891 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 196089515 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 1603144 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 28612 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 643136774 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.007577 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.226676 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 333162826 51.80% 51.80% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 120232758 18.69% 70.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 41446819 6.44% 76.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 148294371 23.06% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 643136774 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.188383 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.836208 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 97937463 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 300403958 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 205522733 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 34511986 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 4760634 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 17730932 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 2017504 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 571814983 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 21511068 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 4760634 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 130465176 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 39849524 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 206232237 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 207101717 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 54727486 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 556322152 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 5380569 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 8461915 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 304416 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 605845 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 22227660 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 11247 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 528347539 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 856455710 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 657084844 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 755426 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 475426080 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 52921453 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 14732861 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 12829203 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 69624573 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 92331469 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 78236769 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 8977003 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 7612209 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 535459998 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 14979383 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 539826932 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 2475624 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 50076597 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 32301398 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 273094 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 643136774 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.839366 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.069808 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 347132433 53.97% 53.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 125915806 19.58% 73.55% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 103467009 16.09% 89.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 59513725 9.25% 98.89% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 7103072 1.10% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 4729 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 643136774 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 53820631 43.79% 43.79% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 63940 0.05% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 7561 0.01% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 33515144 27.27% 71.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 35487446 28.88% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 367420702 68.06% 68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1281309 0.24% 68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 73255 0.01% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 2 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 83298 0.02% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 94677124 17.54% 85.87% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 76291227 14.13% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 539826932 # Type of FU issued
system.cpu1.iq.rate 0.818910 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 122894739 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.227656 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1846883379 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 600138356 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 524462260 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1277620 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 518844 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 476158 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 661932910 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 788750 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 2478321 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 11570290 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 16551 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 142141 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 5437069 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 2465198 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 3688063 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 4760634 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 6603988 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 1453249 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 550562460 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 92331469 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 78236769 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 12610859 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 52882 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 1339609 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 142141 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 1900150 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2649580 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 4549730 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 532747017 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 91844367 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 6553150 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 123079 # number of nop insts executed
system.cpu1.iew.exec_refs 166962398 # number of memory reference insts executed
system.cpu1.iew.exec_branches 99765376 # Number of branches executed
system.cpu1.iew.exec_stores 75118031 # Number of stores executed
system.cpu1.iew.exec_rate 0.808170 # Inst execution rate
system.cpu1.iew.wb_sent 525632708 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 524938418 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 254712512 # num instructions producing a value
system.cpu1.iew.wb_consumers 416314102 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.796325 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.611828 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 43862550 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 14706289 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4273961 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 634802902 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.788218 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.581621 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 414870625 65.35% 65.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 114759147 18.08% 83.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 48245889 7.60% 91.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 16373665 2.58% 93.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 11678245 1.84% 95.45% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 7925650 1.25% 96.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 5354812 0.84% 97.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3238197 0.51% 98.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 12356672 1.95% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 634802902 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 424719097 # Number of instructions committed
system.cpu1.commit.committedOps 500362777 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 153560878 # Number of memory references committed
system.cpu1.commit.loads 80761178 # Number of loads committed
system.cpu1.commit.membars 3652883 # Number of memory barriers committed
system.cpu1.commit.branches 94624372 # Number of branches committed
system.cpu1.commit.fp_insts 463166 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 459868567 # Number of committed integer instructions.
system.cpu1.commit.function_calls 12685398 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 345616008 69.07% 69.07% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 1054252 0.21% 69.28% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 58059 0.01% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 73580 0.01% 69.31% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 80761178 16.14% 85.45% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 72799700 14.55% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction
system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads
system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes
system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 16064791 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 93951930875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 424719097 # Number of Instructions Simulated
system.cpu1.committedOps 500362777 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.552088 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.552088 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.644293 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.644293 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 629086185 # number of integer regfile reads
system.cpu1.int_regfile_writes 373708704 # number of integer regfile writes
system.cpu1.fp_regfile_reads 742781 # number of floating regfile reads
system.cpu1.fp_regfile_writes 462024 # number of floating regfile writes
system.cpu1.cc_regfile_reads 113147370 # number of cc regfile reads
system.cpu1.cc_regfile_writes 113825607 # number of cc regfile writes
system.cpu1.misc_regfile_reads 2613251902 # number of misc regfile reads
system.cpu1.misc_regfile_writes 14637394 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 5151228 # number of replacements
system.cpu1.dcache.tags.tagsinuse 427.693854 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 143143391 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5151740 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 27.785445 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8478589557500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.693854 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835340 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.835340 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 318663535 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 318663535 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 75155961 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 75155961 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 63737585 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 63737585 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 169811 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 169811 # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 58007 # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total 58007 # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1657429 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1657429 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1683439 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1683439 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 138893546 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 138893546 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 139063357 # number of overall hits
system.cpu1.dcache.overall_hits::total 139063357 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 6025315 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 6025315 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 6706823 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 6706823 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630176 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 630176 # number of SoftPFReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 421123 # number of WriteInvalidateReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::total 421123 # number of WriteInvalidateReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 264252 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 264252 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195781 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 195781 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 12732138 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 12732138 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 13362314 # number of overall misses
system.cpu1.dcache.overall_misses::total 13362314 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87326420147 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 87326420147 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 117804291686 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 117804291686 # number of WriteReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13004978477 # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13004978477 # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3882326694 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 3882326694 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4150746008 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 4150746008 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4758000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4758000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 205130711833 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 205130711833 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 205130711833 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 205130711833 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 81181276 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 81181276 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 70444408 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 70444408 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799987 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 799987 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 479130 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total 479130 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1921681 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1921681 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1879220 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1879220 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 151625684 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 151625684 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 152425671 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 152425671 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074221 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.074221 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095207 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.095207 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787733 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787733 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.878933 # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.878933 # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137511 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137511 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104182 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104182 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083971 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.083971 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087664 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.087664 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14493.253904 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14493.253904 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17564.842801 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17564.842801 # average WriteReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 30881.662785 # average WriteInvalidateReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 30881.662785 # average WriteInvalidateReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14691.758980 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14691.758980 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21200.964384 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21200.964384 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16111.254200 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16111.254200 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15351.436273 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15351.436273 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 3328310 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 18296285 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 353421 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 675053 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.417409 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 27.103479 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 3264704 # number of writebacks
system.cpu1.dcache.writebacks::total 3264704 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3035971 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 3035971 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5416489 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 5416489 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3258 # number of WriteInvalidateReq MSHR hits
system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3258 # number of WriteInvalidateReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 136728 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 136728 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 8452460 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 8452460 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 8452460 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 8452460 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2989344 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2989344 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1290334 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1290334 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630111 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 630111 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 417865 # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 417865 # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127524 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127524 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195781 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 195781 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4279678 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4279678 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 4909789 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 4909789 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39357294362 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39357294362 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22683763866 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22683763866 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12612160940 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12612160940 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12265252837 # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12265252837 # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1674709739 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1674709739 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3848237992 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3848237992 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4609500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4609500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62041058228 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 62041058228 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74653219168 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 74653219168 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 688989750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 688989750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 785556502 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 785556502 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1474546252 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1474546252 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036823 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036823 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018317 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018317 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787652 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787652 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.872133 # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.872133 # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066361 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066361 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104182 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104182 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028225 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.028225 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032211 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.032211 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13165.863267 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13165.863267 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17579.761415 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17579.761415 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20015.776490 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20015.776490 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 29352.189911 # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29352.189911 # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13132.506344 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13132.506344 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19655.829687 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19655.829687 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14496.664989 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14496.664989 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15204.975034 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15204.975034 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 5667991 # number of replacements
system.cpu1.icache.tags.tagsinuse 501.848972 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 190104103 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 5668503 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 33.536915 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8518313865250 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.848972 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980174 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.980174 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 397835903 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 397835903 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 190104103 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 190104103 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 190104103 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 190104103 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 190104103 # number of overall hits
system.cpu1.icache.overall_hits::total 190104103 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 5979587 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 5979587 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 5979587 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 5979587 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 5979587 # number of overall misses
system.cpu1.icache.overall_misses::total 5979587 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61433525378 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 61433525378 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 61433525378 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 61433525378 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 61433525378 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 61433525378 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 196083690 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 196083690 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 196083690 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 196083690 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 196083690 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 196083690 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030495 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.030495 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030495 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.030495 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030495 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.030495 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10273.874329 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10273.874329 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10273.874329 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10273.874329 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 8139519 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 675212 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.054761 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 311064 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 311064 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 311064 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 311064 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 311064 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 311064 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5668523 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 5668523 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 5668523 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 5668523 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 5668523 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 5668523 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 52921398555 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 52921398555 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 52921398555 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 52921398555 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 52921398555 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 52921398555 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6131248 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6131248 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6131248 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 6131248 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028909 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.028909 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.028909 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9336.011966 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 6924956 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 7115948 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 165163 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 889052 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 2136964 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13504.433199 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 11477625 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2153158 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 5.330600 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 9723406338993 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 5663.402040 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.532496 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 97.953204 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3050.006780 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3697.963934 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 913.574746 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.345667 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004976 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005979 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.186158 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225706 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055760 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.824245 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1347 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14805 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 237 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 720 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 360 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1369 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5255 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5224 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2823 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.082214 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903625 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 249290678 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 249290678 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 527309 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 181952 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5073722 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data 2781354 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 8564337 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 3264689 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 3264689 # number of Writeback hits
system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 166971 # number of WriteInvalidateReq hits
system.cpu1.l2cache.WriteInvalidateReq_hits::total 166971 # number of WriteInvalidateReq hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 66098 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 66098 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34177 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 34177 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 845253 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 845253 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 527309 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 181952 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 5073722 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3626607 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 9409590 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 527309 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 181952 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 5073722 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3626607 # number of overall hits
system.cpu1.l2cache.overall_hits::total 9409590 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12633 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9907 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 594787 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data 963518 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 1580845 # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks 14 # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total 14 # number of Writeback misses
system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 249743 # number of WriteInvalidateReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::total 249743 # number of WriteInvalidateReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139723 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 139723 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 161589 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 161589 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 15 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 15 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 245189 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 245189 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12633 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9907 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 594787 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1208707 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1826034 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12633 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9907 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 594787 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1208707 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1826034 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 491583485 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 427969129 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 16999057098 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 31500874862 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 49419484574 # number of ReadReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 236089966 # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 236089966 # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3003661220 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 3003661220 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3342420381 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3342420381 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4508496 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4508496 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11309728111 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 11309728111 # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 491583485 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 427969129 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16999057098 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 42810602973 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 60729212685 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 491583485 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 427969129 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16999057098 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 42810602973 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 60729212685 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 539942 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 191859 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5668509 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3744872 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 10145182 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 3264703 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 3264703 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 416714 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::total 416714 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205821 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 205821 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195766 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 195766 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 15 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 15 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1090442 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1090442 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 539942 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 191859 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 5668509 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 4835314 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 11235624 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 539942 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 191859 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 5668509 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 4835314 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 11235624 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051637 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.104928 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.257290 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.155822 # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.599315 # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.599315 # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.678857 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.678857 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.825419 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.825419 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224853 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224853 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051637 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.104928 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.249975 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.162522 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051637 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.104928 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.249975 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.162522 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 43198.660442 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 28580.075049 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32693.602882 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31261.435861 # average ReadReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 945.331665 # average WriteInvalidateReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 945.331665 # average WriteInvalidateReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21497.256858 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21497.256858 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20684.702430 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20684.702430 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 300566.400000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 300566.400000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 46126.572199 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 46126.572199 # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 43198.660442 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28580.075049 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35418.511660 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 33257.438079 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 43198.660442 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28580.075049 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35418.511660 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 33257.438079 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 969171 # number of writebacks
system.cpu1.l2cache.writebacks::total 969171 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 194 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 3035 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 3232 # number of ReadReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 1 # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 1 # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 16069 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 16069 # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 194 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 19104 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 19301 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 194 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 19104 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 19301 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12630 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9713 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 594787 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 960483 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 1577613 # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks 14 # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total 14 # number of Writeback MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688186 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 688186 # number of HardPFReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 249742 # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 249742 # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139723 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139723 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 161589 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 161589 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 15 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 15 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 229120 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 229120 # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12630 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9713 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 594787 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1189603 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 1806733 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12630 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9713 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 594787 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1189603 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688186 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 2494919 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 358018255 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 13119737402 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 25025673719 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 38912076401 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36938967043 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 36938967043 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8412735671 # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 8412735671 # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2759951656 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2759951656 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2380296086 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2380296086 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3864996 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3864996 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7878318651 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7878318651 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 358018255 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13119737402 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32903992370 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 46790395052 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 358018255 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13119737402 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32903992370 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36938967043 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 83729362095 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5602750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 639050750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 644653500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 738464498 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 738464498 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5602750 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1377515248 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1383117998 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.256480 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.155504 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.599313 # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.599313 # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.678857 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.678857 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825419 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825419 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.210117 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.210117 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.160804 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222054 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26055.301051 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24665.159580 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53675.847871 # average HardPFReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33685.706333 # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33685.706333 # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19753.023167 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19753.023167 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14730.557686 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14730.557686 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 257666.400000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 257666.400000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34385.119811 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34385.119811 # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25897.791789 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33559.952085 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 12589327 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 10390309 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 6277 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 6277 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 3264703 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 969369 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1138126 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 416714 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 449544 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355754 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 472453 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1246255 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1097731 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11337166 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14775069 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416528 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186159 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 27714922 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 362785648 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 551966772 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1534872 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4319536 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 920606828 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 4866324 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 20006897 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 3.227379 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.419140 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 15457744 77.26% 77.26% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 4549153 22.74% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 20006897 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 11420254845 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 196151972 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 8513145317 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 7729223292 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 225599484 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 647309419 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 40298 # Transaction distribution
system.iobus.trans_dist::ReadResp 40298 # Transaction distribution
system.iobus.trans_dist::WriteReq 136633 # Transaction distribution
system.iobus.trans_dist::WriteResp 29905 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47726 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122608 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231174 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231174 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353862 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47746 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338712 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338712 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7496536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36251000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 607686128 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92706000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 148478785 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115568 # number of replacements
system.iocache.tags.tagsinuse 11.294495 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115584 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9116942023000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.849176 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.445319 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.240573 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.465332 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.705906 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040640 # Number of tag accesses
system.iocache.tags.data_accesses 1040640 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8859 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8896 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8859 # number of demand (read+write) misses
system.iocache.demand_misses::total 8899 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8859 # number of overall misses
system.iocache.overall_misses::total 8899 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1636729691 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1641925191 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19864825652 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 19864825652 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1636729691 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1642294191 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1636729691 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1642294191 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8859 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8896 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8859 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8899 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8859 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8899 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 184753.323287 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 184568.928844 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186125.718200 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 186125.718200 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 184548.172941 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 184548.172941 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 112586 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 16234 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 6.935198 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8859 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 8859 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8899 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 8859 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8899 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174861151 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1178131651 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14314859762 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14314859762 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1174861151 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1178344651 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1174861151 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1178344651 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132617.806863 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 132433.863647 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134124.688573 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134124.688573 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 1377424 # number of replacements
system.l2c.tags.tagsinuse 64428.474571 # Cycle average of tags in use
system.l2c.tags.total_refs 4496154 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1437791 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 3.127126 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 3245891000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 17415.702003 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.555673 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 13.071281 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4037.254225 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 5874.753333 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3721.003209 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 357.239386 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 523.990627 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2776.282665 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 11847.144423 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17848.477746 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.265743 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000207 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000199 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.061604 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.089642 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.056778 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005451 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.007995 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.042363 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.180773 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272346 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.983101 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 10320 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 289 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 49758 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 29 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 260 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 9845 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 285 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2371 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4137 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 42888 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.157471 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.759247 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 59850638 # Number of tag accesses
system.l2c.tags.data_accesses 59850638 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 6609 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 5089 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 570808 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 585040 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 302541 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 6014 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 4366 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 555272 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 535796 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 269863 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2841398 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 2358990 # number of Writeback hits
system.l2c.Writeback_hits::total 2358990 # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data 147857 # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data 120344 # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total 268201 # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data 33100 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 25345 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 58445 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 6120 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 5439 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 11559 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 54193 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 49865 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 104058 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 6609 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 5089 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 570808 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 639233 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 302541 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 6014 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4366 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 555272 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 585661 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 269863 # number of demand (read+write) hits
system.l2c.demand_hits::total 2945456 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 6609 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 5089 # number of overall hits
system.l2c.overall_hits::cpu0.inst 570808 # number of overall hits
system.l2c.overall_hits::cpu0.data 639233 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 302541 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 6014 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4366 # number of overall hits
system.l2c.overall_hits::cpu1.inst 555272 # number of overall hits
system.l2c.overall_hits::cpu1.data 585661 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 269863 # number of overall hits
system.l2c.overall_hits::total 2945456 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1186 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 952 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 65177 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 129551 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 203502 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 2616 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 2569 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 39512 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 114014 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 227886 # number of ReadReq misses
system.l2c.ReadReq_misses::total 786965 # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data 437920 # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data 120290 # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total 558210 # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data 45660 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 46311 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 91971 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 9121 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 8967 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 18088 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 74847 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 51643 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 126490 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1186 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 952 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 65177 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 204398 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 203502 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2616 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 2569 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 39512 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 165657 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 227886 # number of demand (read+write) misses
system.l2c.demand_misses::total 913455 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1186 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 952 # number of overall misses
system.l2c.overall_misses::cpu0.inst 65177 # number of overall misses
system.l2c.overall_misses::cpu0.data 204398 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 203502 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2616 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 2569 # number of overall misses
system.l2c.overall_misses::cpu1.inst 39512 # number of overall misses
system.l2c.overall_misses::cpu1.data 165657 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 227886 # number of overall misses
system.l2c.overall_misses::total 913455 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 111035273 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 90655016 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 5679579933 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 12742001076 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 236867766 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 230645249 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 3413499724 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 10938718079 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 95639804522 # number of ReadReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 58893966 # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 45248781 # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::total 104142747 # number of WriteInvalidateReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 276167379 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 268661108 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 544828487 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46772512 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 48520461 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 95292973 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 6912544305 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4650422855 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 11562967160 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 111035273 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 90655016 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 5679579933 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 19654545381 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 236867766 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 230645249 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 3413499724 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 15589140934 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 107202771682 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 111035273 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 90655016 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 5679579933 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 19654545381 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 236867766 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 230645249 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 3413499724 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 15589140934 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of overall miss cycles
system.l2c.overall_miss_latency::total 107202771682 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 7795 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 6041 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 635985 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 714591 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 506043 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 8630 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 6935 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 594784 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 649810 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 497749 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 3628363 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 2358990 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 2358990 # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data 585777 # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data 240634 # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total 826411 # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 78760 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 71656 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 150416 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 15241 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 14406 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 29647 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 129040 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 101508 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 230548 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 7795 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 6041 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 635985 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 843631 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 506043 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 8630 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6935 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 594784 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 751318 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 497749 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3858911 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 7795 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 6041 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 635985 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 843631 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 506043 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 8630 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6935 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 594784 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 751318 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 497749 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3858911 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.157590 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.102482 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.181294 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.370440 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.066431 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.175457 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.216893 # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.747588 # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.499888 # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total 0.675463 # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.579736 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.646296 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.611444 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.598452 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.622449 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.610112 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.580029 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.508758 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.548649 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.157590 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.102482 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.242284 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.370440 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.066431 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.220489 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.236713 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.157590 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.102482 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.242284 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.370440 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.066431 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.220489 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.236713 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 95225.857143 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87140.861546 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 98355.096263 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89780.166991 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 86391.469022 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 95941.885023 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 121529.934015 # average ReadReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 134.485673 # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 376.164112 # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::total 186.565534 # average WriteInvalidateReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6048.343824 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5801.237460 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 5923.916093 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5128.002631 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5411.002676 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 5268.297932 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92355.662952 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 90049.432740 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 91414.081429 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 95225.857143 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 87140.861546 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 96158.207913 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89780.166991 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 86391.469022 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 94104.933290 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 117359.663784 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 95225.857143 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 87140.861546 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 96158.207913 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89780.166991 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 86391.469022 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 94104.933290 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 117359.663784 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 11943 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 84 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 142.178571 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 1067007 # number of writebacks
system.l2c.writebacks::total 1067007 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.inst 133 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 17 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 90 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 20 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 133 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 17 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 90 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 20 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 264 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 133 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 17 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 90 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 264 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1184 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 952 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 65044 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 129534 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 203500 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2616 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2569 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 39422 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 113994 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 227886 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 786701 # number of ReadReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 437920 # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 120290 # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::total 558210 # number of WriteInvalidateReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 45660 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 46311 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 91971 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9121 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8967 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 18088 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 74847 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 51643 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 126490 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1184 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 952 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 65044 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 204381 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 203500 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 2616 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 2569 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 39422 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 165637 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 227886 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 913191 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1184 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 952 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 65044 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 204381 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 203500 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 2616 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 2569 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 39422 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 165637 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 227886 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 913191 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 78660484 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4853701817 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11124617158 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 198329749 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2912777274 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9514272921 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 85885889998 # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17416176424 # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3960645719 # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total 21376822143 # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 814816958 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 825298541 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 1640115499 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 162191592 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 159645428 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 321837020 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5979693683 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4008215143 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 9987908826 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 78660484 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 4853701817 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 17104310841 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 198329749 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 2912777274 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 13522488064 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 95873798824 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 78660484 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 4853701817 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 17104310841 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 198329749 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 2912777274 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 13522488064 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 95873798824 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4853989000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4264250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 516390251 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6660266501 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4658794041 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 621932502 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 5280726543 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9512783041 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4264250 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1138322753 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 11940993044 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181270 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.175427 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.216820 # mshr miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.747588 # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.499888 # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.675463 # mshr miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.579736 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.646296 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.611444 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.598452 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.622449 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.610112 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.580029 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508758 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.548649 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.242264 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.220462 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.236645 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.242264 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.220462 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.236645 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 85881.831473 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 83462.927180 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 109172.214092 # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39770.223840 # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32925.810283 # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38295.304891 # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.312265 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.788603 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17832.963641 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17782.215985 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.660979 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17792.847192 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79892.229254 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77613.909784 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 78962.043055 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 855568 # Transaction distribution
system.membus.trans_dist::ReadResp 855568 # Transaction distribution
system.membus.trans_dist::WriteReq 38542 # Transaction distribution
system.membus.trans_dist::WriteResp 38542 # Transaction distribution
system.membus.trans_dist::Writeback 1173701 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 661649 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 661649 # Transaction distribution
system.membus.trans_dist::UpgradeReq 438223 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 309934 # Transaction distribution
system.membus.trans_dist::UpgradeResp 117397 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution
system.membus.trans_dist::ReadExReq 139893 # Transaction distribution
system.membus.trans_dist::ReadExResp 122444 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122608 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26394 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4925384 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 5074464 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335910 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 335910 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5410374 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155738 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52788 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 162304200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 162513298 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14098112 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 14098112 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 176611410 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 651055 # Total snoops (count)
system.membus.snoop_fanout::samples 3600660 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 3600660 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3600660 # Request fanout histogram
system.membus.reqLayer0.occupancy 98274497 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 22081484 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 10699049257 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 5725496770 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 151866715 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 4566673 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4559437 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38542 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38542 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 2358990 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 933261 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp 826411 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 489333 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 321493 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 810826 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 208 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 288168 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 288168 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7677415 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6169065 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 13846480 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255017262 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196496484 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 451513746 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1675443 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 8934179 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.012956 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.113084 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 8818430 98.70% 98.70% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 115749 1.30% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 8934179 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 7984163233 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 2491500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 4301185209 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 3898685571 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 13668 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 5222 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
|