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|
---------- Begin Simulation Statistics ----------
sim_seconds 47.422278 # Number of seconds simulated
sim_ticks 47422277747000 # Number of ticks simulated
final_tick 47422277747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 91986 # Simulator instruction rate (inst/s)
host_op_rate 108182 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4717167353 # Simulator tick rate (ticks/s)
host_mem_usage 870208 # Number of bytes of host memory used
host_seconds 10053.13 # Real time elapsed on the host
sim_insts 924745220 # Number of instructions simulated
sim_ops 1087564829 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 123008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 83392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1145824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 12461528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 54523392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 250240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 244864 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 679904 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 13804768 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 35481280 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 451200 # Number of bytes read from this memory
system.physmem.bytes_read::total 119249400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1145824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 679904 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1825728 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 92428416 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 92449232 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1922 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1303 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 33856 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 194733 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 851928 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3910 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 3826 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 10667 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 215714 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 554395 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 7050 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1879304 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1444194 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1446797 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 2594 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 24162 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 262778 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 1149742 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 5277 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 5163 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 14337 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 291103 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 748199 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9515 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2514628 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 24162 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 14337 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 38499 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1949051 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1949489 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1949051 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2594 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 24162 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 263217 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 1149742 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 5277 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 5163 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 14337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 291103 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 748199 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9515 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4464118 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1879304 # Number of read requests accepted
system.physmem.writeReqs 1600997 # Number of write requests accepted
system.physmem.readBursts 1879304 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1600997 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 120227392 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 48064 # Total number of bytes read from write queue
system.physmem.bytesWritten 101998144 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 119249400 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 102318032 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 751 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 7249 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 97584 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 111371 # Per bank write bursts
system.physmem.perBankRdBursts::1 133364 # Per bank write bursts
system.physmem.perBankRdBursts::2 107237 # Per bank write bursts
system.physmem.perBankRdBursts::3 129396 # Per bank write bursts
system.physmem.perBankRdBursts::4 116369 # Per bank write bursts
system.physmem.perBankRdBursts::5 129089 # Per bank write bursts
system.physmem.perBankRdBursts::6 116664 # Per bank write bursts
system.physmem.perBankRdBursts::7 120571 # Per bank write bursts
system.physmem.perBankRdBursts::8 118226 # Per bank write bursts
system.physmem.perBankRdBursts::9 133705 # Per bank write bursts
system.physmem.perBankRdBursts::10 98234 # Per bank write bursts
system.physmem.perBankRdBursts::11 110272 # Per bank write bursts
system.physmem.perBankRdBursts::12 110364 # Per bank write bursts
system.physmem.perBankRdBursts::13 124983 # Per bank write bursts
system.physmem.perBankRdBursts::14 111960 # Per bank write bursts
system.physmem.perBankRdBursts::15 106748 # Per bank write bursts
system.physmem.perBankWrBursts::0 99185 # Per bank write bursts
system.physmem.perBankWrBursts::1 109011 # Per bank write bursts
system.physmem.perBankWrBursts::2 97054 # Per bank write bursts
system.physmem.perBankWrBursts::3 108172 # Per bank write bursts
system.physmem.perBankWrBursts::4 98286 # Per bank write bursts
system.physmem.perBankWrBursts::5 106076 # Per bank write bursts
system.physmem.perBankWrBursts::6 100140 # Per bank write bursts
system.physmem.perBankWrBursts::7 103851 # Per bank write bursts
system.physmem.perBankWrBursts::8 98795 # Per bank write bursts
system.physmem.perBankWrBursts::9 98239 # Per bank write bursts
system.physmem.perBankWrBursts::10 89198 # Per bank write bursts
system.physmem.perBankWrBursts::11 97505 # Per bank write bursts
system.physmem.perBankWrBursts::12 95822 # Per bank write bursts
system.physmem.perBankWrBursts::13 102116 # Per bank write bursts
system.physmem.perBankWrBursts::14 95043 # Per bank write bursts
system.physmem.perBankWrBursts::15 95228 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
system.physmem.totGap 47422276363500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 37 # Read request sizes (log2)
system.physmem.readPktSize::4 21333 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1857934 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2601 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1598394 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 506038 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 360780 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 256406 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 156907 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 129304 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 95738 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 81613 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 74114 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 66527 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 41507 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 30519 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 26998 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 23594 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 21466 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 2821 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2006 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 877 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 672 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 365 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 268 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 23051 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 29130 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 37353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44982 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 51054 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 59346 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 67111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 76742 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 83422 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 92810 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 99100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 107174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 114191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 124207 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 117512 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 121939 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 125600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 118087 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 27656 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 21524 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 15466 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 10008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 6220 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 4458 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 3377 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 2458 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1856 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1380 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 875 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 716 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 599 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 528 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 476 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 432 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 975956 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 227.699905 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 133.562466 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 280.517231 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 518192 53.10% 53.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 197775 20.26% 73.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 73464 7.53% 80.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 39205 4.02% 84.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 32875 3.37% 88.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 20645 2.12% 90.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 14690 1.51% 91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 16974 1.74% 93.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 62136 6.37% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 975956 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 85700 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 21.919883 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 65.914571 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 85693 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 85700 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 85700 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18.596511 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.559355 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 11.221946 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 76419 89.17% 89.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 4825 5.63% 94.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 861 1.00% 95.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 776 0.91% 96.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 493 0.58% 97.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 137 0.16% 97.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 117 0.14% 97.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 137 0.16% 97.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 585 0.68% 98.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 72 0.08% 98.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 76 0.09% 98.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 72 0.08% 98.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 110 0.13% 98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 48 0.06% 98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 42 0.05% 98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 81 0.09% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 124 0.14% 99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 28 0.03% 99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 35 0.04% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 50 0.06% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 194 0.23% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 14 0.02% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 23 0.03% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 14 0.02% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 54 0.06% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 16 0.02% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 21 0.02% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 26 0.03% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 106 0.12% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 28 0.03% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 8 0.01% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 9 0.01% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 15 0.02% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 15 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 3 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 3 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 11 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 6 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 4 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 2 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 6 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 2 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 3 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207 3 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223 5 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 4 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::244-247 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 85700 # Writes before turning the bus around for reads
system.physmem.totQLat 131185455773 # Total ticks spent queuing
system.physmem.totMemAccLat 166408324523 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 9392765000 # Total ticks spent in databus transfers
system.physmem.avgQLat 69833.25 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 88583.25 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.54 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.15 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.51 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing
system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing
system.physmem.readRowHits 1529879 # Number of row buffer hits during reads
system.physmem.writeRowHits 966437 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 60.64 # Row buffer hit rate for writes
system.physmem.avgGap 13625912.35 # Average gap between requests
system.physmem.pageHitRate 71.89 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 45568926392500 # Time in different power states
system.physmem.memoryStateTime::REF 1583533900000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 269814192000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.actEnergy::0 3837713040 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 3540506760 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 2093990250 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 1931824125 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 7519675800 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 7132967400 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 5325102000 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 5002210080 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 3097392308400 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 3097392308400 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 1175879799405 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 1172220553305 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 27421890099000 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 27425099964000 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 31713938687895 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 31712320334070 # Total energy per rank (pJ)
system.physmem.averagePower::0 668.756196 # Core power per rank (mW)
system.physmem.averagePower::1 668.722070 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 136692903 # Number of BP lookups
system.cpu0.branchPred.condPredicted 91051024 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 6675955 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 96641264 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 62499971 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 64.672137 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 18343531 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 188881 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 98285730 # DTB read hits
system.cpu0.dtb.read_misses 371363 # DTB read misses
system.cpu0.dtb.write_hits 82429878 # DTB write hits
system.cpu0.dtb.write_misses 160428 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 34259 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 6211 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 37781 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 98657093 # DTB read accesses
system.cpu0.dtb.write_accesses 82590306 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 180715608 # DTB hits
system.cpu0.dtb.misses 531791 # DTB misses
system.cpu0.dtb.accesses 181247399 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 214588445 # ITB inst hits
system.cpu0.itb.inst_misses 81035 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 24176 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 217359 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 214669480 # ITB inst accesses
system.cpu0.itb.hits 214588445 # DTB hits
system.cpu0.itb.misses 81035 # DTB misses
system.cpu0.itb.accesses 214669480 # DTB accesses
system.cpu0.numCycles 723605959 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 84128505 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 603958712 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 136692903 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 80843502 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 610845531 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 14389096 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 1590613 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 145998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 6064926 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 691327 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 308415 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 214371554 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 1629958 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 26989 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 710969863 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.995603 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.223531 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 371943625 52.31% 52.31% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 132005479 18.57% 70.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 45223870 6.36% 77.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 161796889 22.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 710969863 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.188905 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.834651 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 100859820 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 341670501 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 226894689 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 36450722 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5094131 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 19684552 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 2143149 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 625299942 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 23465263 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5094131 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 135677386 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 49836875 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 228336608 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 227963533 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 64061330 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 608231586 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 5949574 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 8548374 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 231810 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 263882 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 30185355 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 12581 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 579905224 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 937754781 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 718843517 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 1013139 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 522903039 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 57002179 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 15055979 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 13152707 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 73956769 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 99026206 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 85770687 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 8763922 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 7686093 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 586686508 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 15156086 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 590156830 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 2681738 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 50409396 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 34542071 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 266225 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 710969863 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.830073 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.072195 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 390297771 54.90% 54.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 132320625 18.61% 73.51% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 115120103 16.19% 89.70% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 65333726 9.19% 98.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 7893369 1.11% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 4269 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 710969863 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 61459839 45.63% 45.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 50531 0.04% 45.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 24866 0.02% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 22 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 34471783 25.59% 71.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 38693635 28.73% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 403696370 68.40% 68.40% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1373917 0.23% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 72713 0.01% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 2 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 82685 0.01% 68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 101222055 17.15% 85.82% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 83709039 14.18% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 590156830 # Type of FU issued
system.cpu0.iq.rate 0.815578 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 134700676 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.228246 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 2027250728 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 651818194 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 574107974 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1415207 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 570288 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 525567 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 723981962 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 875543 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 2649036 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 12005066 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 15997 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 137574 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 5832630 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 2633268 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 3783846 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 5094131 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 6289107 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 4809356 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 601961701 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 99026206 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 85770687 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 12881584 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 63147 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 4682481 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 137574 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 1984191 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 2898838 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 4883029 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 582493668 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 98279194 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 7144205 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 119107 # number of nop insts executed
system.cpu0.iew.exec_refs 180711366 # number of memory reference insts executed
system.cpu0.iew.exec_branches 110157991 # Number of branches executed
system.cpu0.iew.exec_stores 82432172 # Number of stores executed
system.cpu0.iew.exec_rate 0.804987 # Inst execution rate
system.cpu0.iew.wb_sent 575359382 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 574633541 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 278757047 # num instructions producing a value
system.cpu0.iew.wb_consumers 457962623 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.794125 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.608690 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 46943290 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 14889861 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4575538 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 702085405 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.780670 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.579297 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 463334360 65.99% 65.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 122538358 17.45% 83.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 53278812 7.59% 91.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 18006181 2.56% 93.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 13261797 1.89% 95.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 8597155 1.22% 96.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 5895517 0.84% 97.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3809437 0.54% 98.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 13363788 1.90% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 702085405 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 466411686 # Number of instructions committed
system.cpu0.commit.committedOps 548096953 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 166959196 # Number of memory references committed
system.cpu0.commit.loads 87021139 # Number of loads committed
system.cpu0.commit.membars 3711025 # Number of memory barriers committed
system.cpu0.commit.branches 104496556 # Number of branches committed
system.cpu0.commit.fp_insts 513447 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 502627891 # Number of committed integer instructions.
system.cpu0.commit.function_calls 13679873 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 379865208 69.31% 69.31% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1141082 0.21% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 57492 0.01% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 73933 0.01% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 87021139 15.88% 85.42% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 79938057 14.58% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 548096953 # Class of committed instruction
system.cpu0.commit.bw_lim_events 13363788 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 1279505618 # The number of ROB reads
system.cpu0.rob.rob_writes 1198929363 # The number of ROB writes
system.cpu0.timesIdled 780048 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 12636096 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 94120949562 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 466411686 # Number of Instructions Simulated
system.cpu0.committedOps 548096953 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.551432 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.551432 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.644566 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.644566 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 688144011 # number of integer regfile reads
system.cpu0.int_regfile_writes 408577767 # number of integer regfile writes
system.cpu0.fp_regfile_reads 842658 # number of floating regfile reads
system.cpu0.fp_regfile_writes 455584 # number of floating regfile writes
system.cpu0.cc_regfile_reads 127446024 # number of cc regfile reads
system.cpu0.cc_regfile_writes 128164594 # number of cc regfile writes
system.cpu0.misc_regfile_reads 2855519856 # number of misc regfile reads
system.cpu0.misc_regfile_writes 15107964 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 5838402 # number of replacements
system.cpu0.dcache.tags.tagsinuse 504.465464 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 155155227 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 5838912 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 26.572626 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 504.465464 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.985284 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.985284 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 346167633 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 346167633 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 80535549 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 80535549 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 69641264 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 69641264 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207056 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 207056 # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 203093 # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total 203093 # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877400 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1877400 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1900232 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1900232 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 150176813 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 150176813 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 150383869 # number of overall hits
system.cpu0.dcache.overall_hits::total 150383869 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 6642832 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 6642832 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 7191098 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 7191098 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 692118 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 692118 # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 798159 # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total 798159 # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 243998 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 243998 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 184133 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 184133 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 13833930 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 13833930 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 14526048 # number of overall misses
system.cpu0.dcache.overall_misses::total 14526048 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 99514286008 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 99514286008 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 115098035706 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 115098035706 # number of WriteReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 53560236062 # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 53560236062 # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3359260407 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3359260407 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3823760481 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 3823760481 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2172500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2172500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 214612321714 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 214612321714 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 214612321714 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 214612321714 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 87178381 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 87178381 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 76832362 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 76832362 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899174 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 899174 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1001252 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total 1001252 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2121398 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2121398 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2084365 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2084365 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 164010743 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 164010743 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 164909917 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 164909917 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076198 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.076198 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.093595 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.093595 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769726 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.769726 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.797161 # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.797161 # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.115018 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.115018 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088340 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088340 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084348 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.084348 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088085 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.088085 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14980.701907 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14980.701907 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16005.627472 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 16005.627472 # average WriteReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 67104.719814 # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 67104.719814 # average WriteInvalidateReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13767.573533 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13767.573533 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20766.296541 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20766.296541 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15513.474603 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15513.474603 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14774.309001 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14774.309001 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 16118603 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 16176348 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 692801 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 696412 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.265848 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 23.228129 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 3975125 # number of writebacks
system.cpu0.dcache.writebacks::total 3975125 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3497983 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 3497983 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5763188 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 5763188 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4492 # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4492 # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 123982 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 123982 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 9261171 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 9261171 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 9261171 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 9261171 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3144849 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3144849 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1427910 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1427910 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 685927 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 685927 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 793667 # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 793667 # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120016 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120016 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 184129 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 184129 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4572759 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4572759 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5258686 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 5258686 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40981205496 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40981205496 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22755476630 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22755476630 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17996613568 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17996613568 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 51855736982 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 51855736982 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1434297417 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1434297417 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3446370519 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3446370519 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2070500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2070500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 63736682126 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 63736682126 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81733295694 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 81733295694 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5581760391 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5581760391 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5277895398 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5277895398 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10859655789 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10859655789 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036074 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036074 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018585 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018585 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762841 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762841 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.792675 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.792675 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056574 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056574 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088338 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088338 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027881 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027881 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031888 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.031888 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13031.215647 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13031.215647 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15936.212107 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15936.212107 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26236.922541 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26236.922541 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 65336.894418 # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 65336.894418 # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11950.885024 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11950.885024 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18717.152209 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18717.152209 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13938.342722 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13938.342722 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15542.532050 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15542.532050 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 6042830 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.967320 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 208050611 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 6043342 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 34.426417 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 11201042000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.967320 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999936 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999936 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 434737408 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 434737408 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 208050611 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 208050611 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 208050611 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 208050611 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 208050611 # number of overall hits
system.cpu0.icache.overall_hits::total 208050611 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 6296413 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 6296413 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 6296413 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 6296413 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 6296413 # number of overall misses
system.cpu0.icache.overall_misses::total 6296413 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55127710497 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 55127710497 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 55127710497 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 55127710497 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 55127710497 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 55127710497 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 214347024 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 214347024 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 214347024 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 214347024 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 214347024 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 214347024 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029375 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.029375 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029375 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.029375 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029375 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.029375 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8755.415265 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8755.415265 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8755.415265 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8755.415265 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4477144 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 62 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 570538 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.847232 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 62 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 253053 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 253053 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 253053 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 253053 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 253053 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 253053 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6043360 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 6043360 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 6043360 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 6043360 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 6043360 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 6043360 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 44707631164 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 44707631164 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 44707631164 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 44707631164 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 44707631164 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 44707631164 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699559498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699559498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028194 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.028194 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.028194 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7397.810351 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 60184765 # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4393414 # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 48808124 # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3087530 # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 452633 # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3443064 # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 5114963 # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements 4158550 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16214.275256 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 12594287 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 4174696 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 3.016815 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 9944532000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 3315.303513 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.862270 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.140550 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 967.067959 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2910.372119 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8960.528846 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.202350 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002372 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001351 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.059025 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.177635 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.546907 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.989641 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8340 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7728 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 111 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 951 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3646 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 2631 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1001 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 51 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1103 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3816 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2122 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 566 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.509033 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.471680 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 280330704 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 280330704 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522125 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 166946 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5796903 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data 2821623 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 9307597 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 3975115 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 3975115 # number of Writeback hits
system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 222232 # number of WriteInvalidateReq hits
system.cpu0.l2cache.WriteInvalidateReq_hits::total 222232 # number of WriteInvalidateReq hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 121282 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 121282 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 38571 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 38571 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 940340 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 940340 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 522125 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 166946 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 5796903 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3761963 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 10247937 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 522125 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 166946 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 5796903 # number of overall hits
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system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5036994556 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1519173000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10364091160 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11883264160 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.278529 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.122077 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.129074 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.129074 # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.503091 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.503091 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.790514 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.790514 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.185504 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.185504 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128447 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.417806 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27642.980057 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27083.574890 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55593.563487 # average HardPFReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32521.484628 # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32521.484628 # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17427.856472 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17427.856472 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13830.282341 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13830.282341 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 237500 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 237500 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 33377.085578 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 33377.085578 # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27996.319261 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47109.300568 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 15173335 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 11005084 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 31316 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 31316 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 3975122 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 5222365 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 963549 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 792291 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 491639 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 333223 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 494297 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1332515 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1202467 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12129286 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16997895 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390025 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1185916 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 30703122 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 387114336 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641181457 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1414144 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4287888 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1033997825 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 10518238 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 27441081 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 5.371527 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.483213 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5 17245975 62.85% 62.85% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6 10195106 37.15% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 27441081 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 13452656135 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 192867736 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 9099601288 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 8421572630 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 213967447 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 651243914 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 133961841 # Number of BP lookups
system.cpu1.branchPred.condPredicted 89061347 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 6618163 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 94585757 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 62217505 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 65.778936 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 18340774 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 186545 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 98830623 # DTB read hits
system.cpu1.dtb.read_misses 443426 # DTB read misses
system.cpu1.dtb.write_hits 80619639 # DTB write hits
system.cpu1.dtb.write_misses 165440 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 44150 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 612 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 6848 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 42554 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 99274049 # DTB read accesses
system.cpu1.dtb.write_accesses 80785079 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 179450262 # DTB hits
system.cpu1.dtb.misses 608866 # DTB misses
system.cpu1.dtb.accesses 180059128 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.inst_hits 211899162 # ITB inst hits
system.cpu1.itb.inst_misses 88988 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 32114 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 230833 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 211988150 # ITB inst accesses
system.cpu1.itb.hits 211899162 # DTB hits
system.cpu1.itb.misses 88988 # DTB misses
system.cpu1.itb.accesses 211988150 # DTB accesses
system.cpu1.numCycles 705261968 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 81258744 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 595261780 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 133961841 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 80558279 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 597026773 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 14270848 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 1888771 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 137791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 6543938 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 793820 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 311963 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 211646234 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 1619349 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 28847 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 695097224 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.005850 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.225976 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 360486788 51.86% 51.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 129920524 18.69% 70.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 44826389 6.45% 77.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 159863523 23.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 695097224 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.189946 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.844029 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 99752260 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 332349824 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 219841712 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 38085588 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 5067840 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 18995502 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 2109796 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 616514692 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 22877728 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 5067840 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 135033848 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 48639647 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 225189127 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 222148294 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 59018468 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 599774214 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 5804898 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 8803158 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 361913 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 923044 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 23085631 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 14113 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 571116000 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 927515458 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 708750961 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 721490 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 514023695 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 57092304 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 16265387 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 14239236 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 76589893 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 99537313 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 83963206 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 9607701 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 8257946 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 576970515 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 16478044 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 581773999 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 2685793 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 50643585 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 34938077 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 295595 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 695097224 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.836968 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.068825 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 375720628 54.05% 54.05% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 136500819 19.64% 73.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 111041420 15.97% 89.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 64151608 9.23% 98.89% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 7678235 1.10% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 4508 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 6 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 695097224 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 58467261 44.14% 44.14% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 65736 0.05% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 8975 0.01% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 28 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 36077917 27.24% 71.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 37847209 28.57% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 396486231 68.15% 68.15% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1392625 0.24% 68.39% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 78812 0.01% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 42928 0.01% 68.41% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 101899765 17.52% 85.93% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 81873638 14.07% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 581773999 # Type of FU issued
system.cpu1.iq.rate 0.824905 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 132467126 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.227695 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1992741902 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 643831652 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 565540483 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1056239 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 418449 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 388115 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 713583395 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 657730 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 2682619 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 12570649 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 16823 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 158978 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 5834378 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 2724944 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 3729174 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 5067840 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 8144414 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 2028582 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 593577386 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 99537313 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 83963206 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 14010879 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 57965 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 1901764 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 158978 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 2040667 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2820650 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 4861317 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 574179310 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 98827451 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 6993764 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 128827 # number of nop insts executed
system.cpu1.iew.exec_refs 179445358 # number of memory reference insts executed
system.cpu1.iew.exec_branches 107524158 # Number of branches executed
system.cpu1.iew.exec_stores 80617907 # Number of stores executed
system.cpu1.iew.exec_rate 0.814136 # Inst execution rate
system.cpu1.iew.wb_sent 566651750 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 565928598 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 274900610 # num instructions producing a value
system.cpu1.iew.wb_consumers 450009146 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.802437 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.610878 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 47337627 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 16182449 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4550579 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 686146419 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.786229 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.582193 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 448874592 65.42% 65.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 124520992 18.15% 83.57% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 51724584 7.54% 91.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 17115210 2.49% 93.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 12441515 1.81% 95.41% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 8692682 1.27% 96.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 5812900 0.85% 97.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3666336 0.53% 98.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 13297608 1.94% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 686146419 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 458333534 # Number of instructions committed
system.cpu1.commit.committedOps 539467876 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 165095491 # Number of memory references committed
system.cpu1.commit.loads 86966664 # Number of loads committed
system.cpu1.commit.membars 3858042 # Number of memory barriers committed
system.cpu1.commit.branches 101991370 # Number of branches committed
system.cpu1.commit.fp_insts 379596 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 495494093 # Number of committed integer instructions.
system.cpu1.commit.function_calls 13607824 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 373132612 69.17% 69.17% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 1140635 0.21% 69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 62088 0.01% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.39% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 37050 0.01% 69.40% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.40% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.40% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.40% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 86966664 16.12% 85.52% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 78128827 14.48% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 539467876 # Class of committed instruction
system.cpu1.commit.bw_lim_events 13297608 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 1255653176 # The number of ROB reads
system.cpu1.rob.rob_writes 1182522736 # The number of ROB writes
system.cpu1.timesIdled 784634 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 10164744 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 94139293558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 458333534 # Number of Instructions Simulated
system.cpu1.committedOps 539467876 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.538753 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.538753 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.649877 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.649877 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 678371688 # number of integer regfile reads
system.cpu1.int_regfile_writes 402814905 # number of integer regfile writes
system.cpu1.fp_regfile_reads 627803 # number of floating regfile reads
system.cpu1.fp_regfile_writes 323588 # number of floating regfile writes
system.cpu1.cc_regfile_reads 123299886 # number of cc regfile reads
system.cpu1.cc_regfile_writes 123979632 # number of cc regfile writes
system.cpu1.misc_regfile_reads 2817640596 # number of misc regfile reads
system.cpu1.misc_regfile_writes 16155257 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 5719154 # number of replacements
system.cpu1.dcache.tags.tagsinuse 428.720007 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 153241322 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5719665 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 26.792010 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8515430590500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.720007 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837344 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.837344 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 342874086 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 342874086 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 80584085 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 80584085 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 68058878 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 68058878 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187635 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 187635 # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 112453 # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total 112453 # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1764554 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1764554 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1816897 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1816897 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 148642963 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 148642963 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 148830598 # number of overall hits
system.cpu1.dcache.overall_hits::total 148830598 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 6869643 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 6869643 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 7494314 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 7494314 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 706318 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 706318 # number of SoftPFReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 458418 # number of WriteInvalidateReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::total 458418 # number of WriteInvalidateReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 288948 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 288948 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 190861 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 190861 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 14363957 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 14363957 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 15070275 # number of overall misses
system.cpu1.dcache.overall_misses::total 15070275 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 105402463849 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 105402463849 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 121649241613 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 121649241613 # number of WriteReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 17403154350 # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 17403154350 # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4078869410 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 4078869410 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3937390159 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 3937390159 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1956500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1956500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 227051705462 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 227051705462 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 227051705462 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 227051705462 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 87453728 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 87453728 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 75553192 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 75553192 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 893953 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 893953 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 570871 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total 570871 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2053502 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 2053502 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2007758 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 2007758 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 163006920 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 163006920 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 163900873 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 163900873 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099193 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.099193 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790106 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790106 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.803015 # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.803015 # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140710 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140710 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095062 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095062 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088119 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.088119 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.091947 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.091947 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.222908 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.222908 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16232.205057 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 16232.205057 # average WriteReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 37963.505687 # average WriteInvalidateReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 37963.505687 # average WriteInvalidateReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14116.274935 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14116.274935 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20629.621342 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20629.621342 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15807.044358 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15807.044358 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15066.195239 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15066.195239 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 4622048 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 18188306 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 368036 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 754235 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.558684 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 24.114906 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 3658567 # number of writebacks
system.cpu1.dcache.writebacks::total 3658567 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3579229 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 3579229 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6058526 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 6058526 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3270 # number of WriteInvalidateReq MSHR hits
system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3270 # number of WriteInvalidateReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 146042 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 146042 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 9637755 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 9637755 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 9637755 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 9637755 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3290414 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 3290414 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1435788 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1435788 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 706224 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 706224 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 455148 # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 455148 # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 142906 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 142906 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 190858 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 190858 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4726202 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4726202 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5432426 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 5432426 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44800014998 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44800014998 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23381887855 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23381887855 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16359112476 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16359112476 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 16414544257 # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 16414544257 # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1722097666 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1722097666 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3546227841 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3546227841 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1864500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1864500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68181902853 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 68181902853 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84541015329 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 84541015329 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 790979694 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 790979694 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 944680456 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 944680456 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1735660150 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1735660150 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037625 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037625 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019004 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019004 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790001 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790001 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.797287 # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.797287 # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069591 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069591 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095060 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095060 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028994 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.028994 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033145 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.033145 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13615.312541 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13615.312541 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16285.055910 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16285.055910 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23164.197869 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23164.197869 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 36064.190674 # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 36064.190674 # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12050.562370 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12050.562370 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18580.451650 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18580.451650 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14426.362405 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14426.362405 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15562.294881 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15562.294881 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 5881686 # number of replacements
system.cpu1.icache.tags.tagsinuse 501.904324 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 205507195 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 5882198 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 34.937143 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8555135625500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.904324 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980282 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.980282 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 371 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 429168724 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 429168724 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 205507195 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 205507195 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 205507195 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 205507195 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 205507195 # number of overall hits
system.cpu1.icache.overall_hits::total 205507195 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 6136058 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 6136058 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 6136058 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 6136058 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 6136058 # number of overall misses
system.cpu1.icache.overall_misses::total 6136058 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53889413624 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 53889413624 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 53889413624 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 53889413624 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 53889413624 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 53889413624 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 211643253 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 211643253 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 211643253 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 211643253 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 211643253 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 211643253 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028992 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.028992 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028992 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.028992 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028992 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.028992 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8782.415946 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 8782.415946 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8782.415946 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 8782.415946 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8782.415946 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 8782.415946 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 4496430 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 574651 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.824627 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 253840 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 253840 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 253840 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 253840 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 253840 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 253840 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5882218 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 5882218 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 5882218 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 5882218 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 5882218 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 5882218 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43727434357 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 43727434357 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43727434357 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 43727434357 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43727434357 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 43727434357 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6637997 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6637997 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6637997 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 6637997 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027793 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.027793 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.027793 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7433.834373 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 7433.834373 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 7433.834373 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 56932742 # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2823095 # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 47812216 # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2677811 # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 382726 # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3236886 # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4916498 # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements 4092617 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13780.930785 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 12621619 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 4108487 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 3.072084 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 9637211064000 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 3757.362843 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.809020 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 56.863279 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 599.057552 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3491.075179 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5813.762913 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.229331 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003834 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003471 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036564 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.213078 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.354844 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.841121 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8933 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6853 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 68 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 777 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3625 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2921 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1542 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3137 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2007 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 750 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.545227 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.418274 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 271640392 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 271640392 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 596119 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 184681 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5616426 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data 2971260 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 9368486 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 3658557 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 3658557 # number of Writeback hits
system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 182266 # number of WriteInvalidateReq hits
system.cpu1.l2cache.WriteInvalidateReq_hits::total 182266 # number of WriteInvalidateReq hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 95807 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 95807 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41710 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 41710 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 960995 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 960995 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 596119 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 184681 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 5616426 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3932255 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 10329481 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 596119 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 184681 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 5616426 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3932255 # number of overall hits
system.cpu1.l2cache.overall_hits::total 10329481 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 16104 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 12169 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 265788 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data 1166045 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 1460106 # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks 9 # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total 9 # number of Writeback misses
system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 271820 # number of WriteInvalidateReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::total 271820 # number of WriteInvalidateReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 129531 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 129531 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 149141 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 149141 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255657 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 255657 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 16104 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 12169 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 265788 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1421702 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1715763 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 16104 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 12169 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 265788 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1421702 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1715763 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 666484538 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 571688851 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 6944017926 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 40559833009 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 48742024324 # number of ReadReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 11677447356 # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 11677447356 # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2603211060 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 2603211060 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3027794367 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3027794367 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1818500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1818500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11891425269 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 11891425269 # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 666484538 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 571688851 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 6944017926 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 52451258278 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 60633449593 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 666484538 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 571688851 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 6944017926 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 52451258278 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 60633449593 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 612223 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 196850 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5882214 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4137305 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 10828592 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 3658566 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 3658566 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 454086 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::total 454086 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 225338 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 225338 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 190851 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 190851 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1216652 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1216652 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 612223 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 196850 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 5882214 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 5353957 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 12045244 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 612223 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 196850 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 5882214 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 5353957 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 12045244 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026304 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061819 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.045185 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.281837 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.134838 # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.598609 # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.598609 # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.574830 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.574830 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.781453 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.781453 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210132 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210132 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026304 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061819 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.045185 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.265542 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.142443 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026304 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061819 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.045185 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.265542 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.142443 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41386.272851 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46979.115046 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26126.152896 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34784.106110 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 33382.524504 # average ReadReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 42960.221308 # average WriteInvalidateReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 42960.221308 # average WriteInvalidateReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20097.204993 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20097.204993 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20301.556024 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20301.556024 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 259785.714286 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 259785.714286 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 46513.200378 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 46513.200378 # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41386.272851 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46979.115046 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26126.152896 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36893.285849 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 35339.058829 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41386.272851 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46979.115046 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26126.152896 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36893.285849 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 35339.058829 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 176494 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 8388 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 21.041249 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 1389640 # number of writebacks
system.cpu1.l2cache.writebacks::total 1389640 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 164 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 69245 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 8993 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 78405 # number of ReadReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 181850 # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 181850 # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 36174 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 36174 # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 164 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 69245 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 45167 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 114579 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 164 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 69245 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 45167 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 114579 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 16101 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 12005 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 196543 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 1157052 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 1381701 # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks 9 # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total 9 # number of Writeback MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 3236467 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 3236467 # number of HardPFReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 89970 # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 89970 # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 129531 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 129531 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 149141 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 149141 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 219483 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 219483 # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 16101 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 12005 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 196543 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1376535 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 1601184 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 16101 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 12005 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 196543 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1376535 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 3236467 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 4837651 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 552512324 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 478828801 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 4373003012 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 32056735781 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 37461079918 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 119200504380 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 119200504380 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2795660291 # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 2795660291 # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2211789154 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2211789154 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2062142611 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2062142611 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1496500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1496500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7294562114 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7294562114 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 552512324 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 478828801 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 4373003012 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39351297895 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 44755642032 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 552512324 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 478828801 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 4373003012 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39351297895 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 119200504380 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 163956146412 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6077501 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 736923302 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 743000803 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 890555024 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 890555024 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6077501 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1627478326 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1633555827 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.279663 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.127597 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.198134 # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.198134 # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.574830 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.574830 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.781453 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.781453 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.180399 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.180399 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132931 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.401623 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27705.527306 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27112.291240 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36830.440224 # average HardPFReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31073.249872 # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31073.249872 # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17075.365387 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17075.365387 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13826.798875 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13826.798875 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213785.714286 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213785.714286 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33235.203246 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33235.203246 # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27951.592092 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33891.685533 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 15325840 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 11081361 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 7210 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 7210 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 3658566 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 4807205 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 18 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 637593 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 454086 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 471082 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 336358 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 477965 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1352070 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1222067 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11764566 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16293479 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 431287 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1341589 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 29830921 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 376462768 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 612089908 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1574800 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4897784 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 995025260 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 10166385 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 26584709 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 5.370632 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.482974 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5 16731578 62.94% 62.94% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6 9853131 37.06% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 26584709 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 12493291014 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 175961487 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 8832336643 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 8528127192 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 235484276 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 730977975 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 40396 # Transaction distribution
system.iobus.trans_dist::ReadResp 40396 # Transaction distribution
system.iobus.trans_dist::WriteReq 136775 # Transaction distribution
system.iobus.trans_dist::WriteResp 30047 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 123062 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 354342 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48148 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 156169 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7497071 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36581000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 1043032876 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 93018000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 179190812 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115581 # number of replacements
system.iocache.tags.tagsinuse 11.295325 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9153631711000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.835501 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.459825 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.239719 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.466239 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.705958 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040757 # Number of tag accesses
system.iocache.tags.data_accesses 1040757 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8872 # number of demand (read+write) misses
system.iocache.demand_misses::total 8912 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8872 # number of overall misses
system.iocache.overall_misses::total 8912 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1960529318 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1966236318 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 365000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 365000 # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28841569746 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 28841569746 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 6072000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1960529318 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1966601318 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 6072000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1960529318 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1966601318 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8872 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8912 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8872 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8912 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 220979.409152 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 220702.246941 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 121666.666667 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 121666.666667 # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270234.331628 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 270234.331628 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 151800 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 220668.909111 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 151800 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 220668.909111 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 224453 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 27297 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.222625 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8872 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8909 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 8872 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8912 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 8872 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8912 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1499010380 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1502793380 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 209000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 209000 # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23291152308 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23291152308 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3992000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1499010380 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1503002380 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3992000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1499010380 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1503002380 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168959.691163 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 168682.610843 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667 # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.071172 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.071172 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 1916125 # number of replacements
system.l2c.tags.tagsinuse 64884.880884 # Cycle average of tags in use
system.l2c.tags.total_refs 8755676 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1978999 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.424295 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 3437261500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 8337.656958 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.346754 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 14.129416 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 627.039592 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3445.654069 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15412.309931 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 351.392171 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 435.207962 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 621.389971 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 11403.863316 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 24218.890744 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.127223 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000265 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000216 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.009568 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.052577 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.235173 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005362 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.006641 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.009482 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.174009 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.369551 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.990065 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 38428 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 201 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 24245 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 143 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 2926 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 6291 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 29058 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 187 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1447 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 2670 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 19923 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.586365 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.003067 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.369949 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 93004482 # Number of tag accesses
system.l2c.tags.data_accesses 93004482 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 9030 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 6306 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 171973 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 713080 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1991967 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 8819 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 5864 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 186687 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 740221 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 2136612 # number of ReadReq hits
system.l2c.ReadReq_hits::total 5970559 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 3063024 # number of Writeback hits
system.l2c.Writeback_hits::total 3063024 # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data 47241 # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data 45742 # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total 92983 # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data 33885 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 29324 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 63209 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 7714 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 7828 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 15542 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 60878 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 59021 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 119899 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 9030 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 6306 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 171973 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 773958 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 1991967 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 8819 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 5864 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 186687 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 799242 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 2136612 # number of demand (read+write) hits
system.l2c.demand_hits::total 6090458 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 9030 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 6306 # number of overall hits
system.l2c.overall_hits::cpu0.inst 171973 # number of overall hits
system.l2c.overall_hits::cpu0.data 773958 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 1991967 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 8819 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 5864 # number of overall hits
system.l2c.overall_hits::cpu1.inst 186687 # number of overall hits
system.l2c.overall_hits::cpu1.data 799242 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 2136612 # number of overall hits
system.l2c.overall_hits::total 6090458 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1923 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1303 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 12603 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 144091 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 852232 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 3910 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 3826 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 10632 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 164104 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 554912 # number of ReadReq misses
system.l2c.ReadReq_misses::total 1749536 # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data 29537 # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data 18781 # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total 48318 # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data 37338 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 36221 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 73559 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 9578 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 9902 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 19480 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 52901 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 53544 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 106445 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1923 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1303 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 12603 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 196992 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 852232 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3910 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 3826 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 10632 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 217648 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 554912 # number of demand (read+write) misses
system.l2c.demand_misses::total 1855981 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1923 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1303 # number of overall misses
system.l2c.overall_misses::cpu0.inst 12603 # number of overall misses
system.l2c.overall_misses::cpu0.data 196992 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 852232 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3910 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 3826 # number of overall misses
system.l2c.overall_misses::cpu1.inst 10632 # number of overall misses
system.l2c.overall_misses::cpu1.data 217648 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 554912 # number of overall misses
system.l2c.overall_misses::total 1855981 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 177025748 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 119617998 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 1238513239 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 13834613079 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 153097994602 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 331865247 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 326979750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 1012532239 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 14885938635 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 79345151118 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 264370231655 # number of ReadReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 10044630 # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 10457617 # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::total 20502247 # number of WriteInvalidateReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 175354905 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 165935687 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 341290592 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 48698982 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 55173706 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 103872688 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 4424762459 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4377056558 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 8801819017 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 177025748 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 119617998 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1238513239 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 18259375538 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 153097994602 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 331865247 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 326979750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 1012532239 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 19262995193 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 79345151118 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 273172050672 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 177025748 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 119617998 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1238513239 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 18259375538 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 153097994602 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 331865247 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 326979750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 1012532239 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 19262995193 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 79345151118 # number of overall miss cycles
system.l2c.overall_miss_latency::total 273172050672 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 10953 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 7609 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 184576 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 857171 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2844199 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 12729 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 9690 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 197319 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 904325 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2691524 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 7720095 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 3063024 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 3063024 # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data 76778 # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data 64523 # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total 141301 # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 71223 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 65545 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 136768 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 17292 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 17730 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 35022 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 113779 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 112565 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 226344 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 10953 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 7609 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 184576 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 970950 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2844199 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 12729 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 9690 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 197319 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 1016890 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2691524 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 7946439 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 10953 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 7609 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 184576 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 970950 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2844199 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 12729 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 9690 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 197319 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 1016890 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2691524 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 7946439 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.175568 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.171245 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.068281 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.168101 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.299639 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.307173 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.394840 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.053882 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.181466 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.206170 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.226621 # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.384707 # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.291075 # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total 0.341951 # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.524241 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.552613 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.537838 # miss rate for UpgradeReq accesses
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system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.553898 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.558488 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.556222 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.464945 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.475672 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.470280 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.202855 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.214002 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.233479 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.202855 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.214002 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.233479 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 83613.975559 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78300.094379 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 138960.075245 # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 26965.564241 # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27931.878814 # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 27341.166584 # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10302.647357 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.691394 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10275.094224 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10301.097202 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10284.711472 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10292.768070 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71179.305627 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69289.702936 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 70228.797041 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80274.212183 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76083.115009 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 135016.780662 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80274.212183 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76083.115009 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 135016.780662 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 1817706 # Transaction distribution
system.membus.trans_dist::ReadResp 1817706 # Transaction distribution
system.membus.trans_dist::WriteReq 38526 # Transaction distribution
system.membus.trans_dist::WriteResp 38526 # Transaction distribution
system.membus.trans_dist::Writeback 1444194 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 154200 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 154200 # Transaction distribution
system.membus.trans_dist::UpgradeReq 434662 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 279066 # Transaction distribution
system.membus.trans_dist::UpgradeResp 97607 # Transaction distribution
system.membus.trans_dist::ReadExReq 117028 # Transaction distribution
system.membus.trans_dist::ReadExResp 102726 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123062 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25796 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6008493 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 6157429 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336112 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 336112 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6493541 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156169 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51592 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 207457224 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 207665557 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 14110208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 221775765 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 633029 # Total snoops (count)
system.membus.snoop_fanout::samples 4186947 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 4186947 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 4186947 # Request fanout histogram
system.membus.reqLayer0.occupancy 98514469 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 21244987 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 16738053981 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 17312327015 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 187280188 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 8653355 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 8646086 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38526 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38526 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 3063024 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 248029 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp 141301 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 493306 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 294608 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 787914 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 273153 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 273153 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10956928 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10351144 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 21308072 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 369780529 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 344544100 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 714324629 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1644746 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 12968411 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.008917 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.094008 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 12852771 99.11% 99.11% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 115640 0.89% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 12968411 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 19352517195 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 7381500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 20456793572 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 20083133002 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 13518 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 5604 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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