path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.345385                       # Number of seconds simulated
sim_ticks                                47345385235500                       # Number of ticks simulated
final_tick                               47345385235500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 106392                       # Simulator instruction rate (inst/s)
host_op_rate                                   125133                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5453309126                       # Simulator tick rate (ticks/s)
host_mem_usage                                 767036                       # Number of bytes of host memory used
host_seconds                                  8681.96                       # Real time elapsed on the host
sim_insts                                   923688991                       # Number of instructions simulated
sim_ops                                    1086395427                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       161152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       146432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          4268768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         16023832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     20180672                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       179840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       156416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3463536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         11559072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     14510464                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        437312                       # Number of bytes read from this memory
system.physmem.bytes_read::total             71087496                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      4268768                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3463536                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7732304                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     86253568                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20812                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          86274384                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2518                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2288                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             82652                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            250394                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       315323                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2810                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2444                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             54162                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            180625                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       226726                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6833                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1126775                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1347712                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2602                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1350315                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3404                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          3093                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               90162                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              338445                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       426244                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          3798                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          3304                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               73155                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              244144                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       306481                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9237                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1501466                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          90162                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          73155                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             163317                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1821795                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                440                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1822234                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1821795                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3404                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         3093                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              90162                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             338885                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       426244                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         3798                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         3304                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              73155                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             244144                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       306481                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9237                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3323700                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1126775                       # Number of read requests accepted
system.physmem.writeReqs                      2040290                       # Number of write requests accepted
system.physmem.readBursts                     1126775                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    2040290                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 72094336                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     19264                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 130093376                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  71087496                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              130432784                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      301                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    7556                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         121134                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               65675                       # Per bank write bursts
system.physmem.perBankRdBursts::1               75833                       # Per bank write bursts
system.physmem.perBankRdBursts::2               67256                       # Per bank write bursts
system.physmem.perBankRdBursts::3               67290                       # Per bank write bursts
system.physmem.perBankRdBursts::4               71240                       # Per bank write bursts
system.physmem.perBankRdBursts::5               82191                       # Per bank write bursts
system.physmem.perBankRdBursts::6               67013                       # Per bank write bursts
system.physmem.perBankRdBursts::7               67787                       # Per bank write bursts
system.physmem.perBankRdBursts::8               61707                       # Per bank write bursts
system.physmem.perBankRdBursts::9               85775                       # Per bank write bursts
system.physmem.perBankRdBursts::10              61014                       # Per bank write bursts
system.physmem.perBankRdBursts::11              72520                       # Per bank write bursts
system.physmem.perBankRdBursts::12              65793                       # Per bank write bursts
system.physmem.perBankRdBursts::13              74631                       # Per bank write bursts
system.physmem.perBankRdBursts::14              69278                       # Per bank write bursts
system.physmem.perBankRdBursts::15              71471                       # Per bank write bursts
system.physmem.perBankWrBursts::0              122526                       # Per bank write bursts
system.physmem.perBankWrBursts::1              130111                       # Per bank write bursts
system.physmem.perBankWrBursts::2              125889                       # Per bank write bursts
system.physmem.perBankWrBursts::3              127486                       # Per bank write bursts
system.physmem.perBankWrBursts::4              126972                       # Per bank write bursts
system.physmem.perBankWrBursts::5              136977                       # Per bank write bursts
system.physmem.perBankWrBursts::6              126845                       # Per bank write bursts
system.physmem.perBankWrBursts::7              128268                       # Per bank write bursts
system.physmem.perBankWrBursts::8              123854                       # Per bank write bursts
system.physmem.perBankWrBursts::9              125736                       # Per bank write bursts
system.physmem.perBankWrBursts::10             125360                       # Per bank write bursts
system.physmem.perBankWrBursts::11             131761                       # Per bank write bursts
system.physmem.perBankWrBursts::12             119984                       # Per bank write bursts
system.physmem.perBankWrBursts::13             126166                       # Per bank write bursts
system.physmem.perBankWrBursts::14             125889                       # Per bank write bursts
system.physmem.perBankWrBursts::15             128885                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         614                       # Number of times write queue was full causing retry
system.physmem.totGap                    47345383810500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21334                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1105404                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                2037687                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    495851                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    234383                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    118863                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     70028                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     51854                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     39852                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     34830                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     31890                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     28010                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      7930                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     4174                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2742                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1780                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1381                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      844                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      715                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      607                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      457                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      161                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    30752                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    44920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    58821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    69578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    77864                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    89177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    97306                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   106336                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   112038                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   121912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   121861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   124135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   125483                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   131449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   118558                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   117002                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   113440                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   105060                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                    29238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                    25813                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                    22998                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                    20720                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                    18797                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                    16980                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                    15279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                    13444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                    11652                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                    10311                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     9180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     8124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     7426                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     6654                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     6134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     5597                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     5145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     4620                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     4249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     3863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     3550                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     3131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                     2559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                     2104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                     1878                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                     1591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                     1280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                     1141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                     1049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                     1018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                     1502                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1131657                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      178.664737                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     108.493979                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     249.059793                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         718344     63.48%     63.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       219262     19.38%     82.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        56669      5.01%     87.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        25497      2.25%     90.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        20148      1.78%     91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11584      1.02%     92.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         9545      0.84%     93.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         8895      0.79%     94.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        61713      5.45%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1131657                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         74075                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        15.207155                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       65.468886                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           74072    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           74075                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         74075                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        27.441228                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.793858                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev      451.068024                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-1023          74039     99.95%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1024-2047           13      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2048-3071            9      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3072-4095            5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4096-5119            2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5120-6143            2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26624-27647            1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33792-34815            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64512-65535            3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           74075                       # Writes before turning the bus around for reads
system.physmem.totQLat                    56140564025                       # Total ticks spent queuing
system.physmem.totMemAccLat               77261951525                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5632370000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       49837.43                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  68587.43                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.52                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.75                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.50                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.75                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.42                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.34                       # Average write queue length when enqueuing
system.physmem.readRowHits                     851046                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1176475                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.55                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  57.88                       # Row buffer hit rate for writes
system.physmem.avgGap                     14949293.37                       # Average gap between requests
system.physmem.pageHitRate                      64.18                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 4318120800                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2356117500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4401423000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               6642421200                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3092370278400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1163515422960                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27386602512000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31660206295860                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.707358                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45559855793000                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1580966400000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    204562609000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 4237153200                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2311938750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4385027400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               6529429440                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3092370278400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1165548686490                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27384818947500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31660201461180                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.707256                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45556862760500                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1580966400000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    207555509500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           572                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          528                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             39                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           11                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              145356452                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         96435082                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          7088203                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups           101789401                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               67765064                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            66.573792                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               20004195                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            205158                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   580611                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               580611                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13679                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        93135                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       259311                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       321300                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  1669.368192                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 10492.971715                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-32767       317448     98.80%     98.80% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-65535         2037      0.63%     99.44% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-98303          845      0.26%     99.70% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-131071          576      0.18%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-163839          232      0.07%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::163840-196607           45      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-229375           28      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::229376-262143           26      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-294911           42      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::294912-327679            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-360447            9      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       321300                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       293805                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 15781.864128                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 13334.413537                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 14277.098383                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       291279     99.14%     99.14% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         1809      0.62%     99.76% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          367      0.12%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          189      0.06%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          105      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           25      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           21      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       293805                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 521650035508                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.610400                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.526555                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 520697119508     99.82%     99.82% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3    543124000      0.10%     99.92% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5    195186500      0.04%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7     85165500      0.02%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9     70245500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11     34070500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13     11934000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15     12740000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       448500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19         1500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 521650035508                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        93135     87.19%     87.19% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        13679     12.81%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       106814                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       580611                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       580611                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       106814                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       106814                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       687425                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   105404836                       # DTB read hits
system.cpu0.dtb.read_misses                    420652                       # DTB read misses
system.cpu0.dtb.write_hits                   86890500                       # DTB write hits
system.cpu0.dtb.write_misses                   159959                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              45064                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1074                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   40944                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      605                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  8089                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    40127                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               105825488                       # DTB read accesses
system.cpu0.dtb.write_accesses               87050459                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        192295336                       # DTB hits
system.cpu0.dtb.misses                         580611                       # DTB misses
system.cpu0.dtb.accesses                    192875947                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    84622                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                84622                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          994                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61729                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore         9515                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        75107                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1146.297948                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  8819.384812                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        74551     99.26%     99.26% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          182      0.24%     99.50% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303          223      0.30%     99.80% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071          112      0.15%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839            5      0.01%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607            9      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375           12      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        75107                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        72238                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 20242.257302                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 17307.169845                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 18587.015651                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        70635     97.78%     97.78% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071         1318      1.82%     99.61% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          148      0.20%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           80      0.11%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           29      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        72238                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 405678068016                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.851697                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.355553                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    60184359568     14.84%     14.84% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   345473805948     85.16%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       18871000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        1025500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4           6000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 405678068016                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        61729     98.42%     98.42% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          994      1.58%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        62723                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        84622                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        84622                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        62723                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        62723                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       147345                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   229226252                       # ITB inst hits
system.cpu0.itb.inst_misses                     84622                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              45064                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1074                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   29308                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   225641                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               229310874                       # ITB inst accesses
system.cpu0.itb.hits                        229226252                       # DTB hits
system.cpu0.itb.misses                          84622                       # DTB misses
system.cpu0.itb.accesses                    229310874                       # DTB accesses
system.cpu0.numCycles                       787784387                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          93175923                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     642526185                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  145356452                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          87769259                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    654798115                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               15283958                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   1702071                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles              255624                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      6308926                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       745987                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles       671334                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                229000663                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              1782311                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  27660                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         765299959                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.983676                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.220176                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               404626902     52.87%     52.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1               139960190     18.29%     71.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                49291261      6.44%     77.60% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3               171421606     22.40%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           765299959                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.184513                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.815612                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               110781464                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            368356745                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                241543971                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             39160465                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5457314                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            20998766                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              2230758                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             666506782                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts             24554495                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5457314                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               147799214                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               53385858                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     247347968                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                243020975                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             68288630                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             648373688                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              6354822                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents              9340488                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                358878                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                691420                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              31770877                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents           13042                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          618836498                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups           1000163983                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       765756832                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           980941                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            557557100                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                61279388                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          16104693                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      13959035                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 79116837                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           106280749                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           90455195                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          9698755                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         8363084                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 625354037                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           16149817                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                628774014                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued          2896491                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       54006760                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     37569824                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        287316                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    765299959                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.821605                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.068919                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          423230722     55.30%     55.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1          141522259     18.49%     73.79% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2          122647115     16.03%     89.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           69647275      9.10%     98.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            8247243      1.08%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5               5342      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  3      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      765299959                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               65414267     45.68%     45.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 59912      0.04%     45.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                  17829      0.01%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc              19      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead              37349884     26.08%     71.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite             40363750     28.19%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            430163495     68.41%     68.41% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1578221      0.25%     68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                81407      0.01%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                125      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         78656      0.01%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           108646479     17.28%     85.97% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           88225631     14.03%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             628774014                       # Type of FU issued
system.cpu0.iq.rate                          0.798155                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                  143205661                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.227754                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        2167577171                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        695106277                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    611404783                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1372966                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            554126                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       508083                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             771129089                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 850586                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         2930031                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     13213228                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        17078                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       150900                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      6091069                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2819130                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      4221569                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5457314                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                7826815                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              3783393                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          641629807                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            106280749                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            90455195                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          13677015                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 59030                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              3651240                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        150900                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2214888                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      3025224                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             5240112                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            620548589                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            105398618                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          7653008                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       125953                       # number of nop insts executed
system.cpu0.iew.exec_refs                   192287971                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               117275797                       # Number of branches executed
system.cpu0.iew.exec_stores                  86889353                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.787714                       # Inst execution rate
system.cpu0.iew.wb_sent                     612710943                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    611912866                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                297952907                       # num instructions producing a value
system.cpu0.iew.wb_consumers                488842231                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.776752                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.609507                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       50177444                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       15862501                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4903538                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    755787028                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.772749                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.571704                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    501065306     66.30%     66.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1    130810768     17.31%     83.61% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     56911365      7.53%     91.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     19253126      2.55%     93.68% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     13929285      1.84%     95.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      9339201      1.24%     96.76% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      6281388      0.83%     97.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      4033068      0.53%     98.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     14163521      1.87%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    755787028                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           497564314                       # Number of instructions committed
system.cpu0.commit.committedOps             584033993                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     177431645                       # Number of memory references committed
system.cpu0.commit.loads                     93067519                       # Number of loads committed
system.cpu0.commit.membars                    3925399                       # Number of memory barriers committed
system.cpu0.commit.branches                 111370146                       # Number of branches committed
system.cpu0.commit.fp_insts                    496516                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                535821487                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            14891305                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       405157799     69.37%     69.37% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1311833      0.22%     69.60% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           63039      0.01%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        69677      0.01%     69.62% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.62% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.62% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.62% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       93067519     15.94%     85.55% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      84364126     14.45%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        584033993                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             14163521                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                  1371348086                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1277898548                       # The number of ROB writes
system.cpu0.timesIdled                        1050969                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       22484428                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 93902986117                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  497564314                       # Number of Instructions Simulated
system.cpu0.committedOps                    584033993                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.583282                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.583282                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.631600                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.631600                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               732616408                       # number of integer regfile reads
system.cpu0.int_regfile_writes              435784003                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   812591                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  450624                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                135724425                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               136350840                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             3048491910                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              15942846                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements          6332598                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          484.098749                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          164710199                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6333110                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            26.007791                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1750140500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   484.098749                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.945505                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.945505                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          275                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        368140426                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       368140426                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     86285504                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       86285504                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     73342402                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      73342402                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       227851                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       227851                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       264480                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       264480                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1878345                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1878345                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1911240                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1911240                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    159627906                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       159627906                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    159855757                       # number of overall hits
system.cpu0.dcache.overall_hits::total      159855757                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      7088092                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7088092                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      7774496                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      7774496                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       746133                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       746133                       # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       842824                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total       842824                       # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       281020                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       281020                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       209055                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       209055                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     14862588                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      14862588                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     15608721                       # number of overall misses
system.cpu0.dcache.overall_misses::total     15608721                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 105859717159                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 105859717159                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137077029934                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 137077029934                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  45622327717                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  45622327717                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4025426932                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4025426932                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4395434712                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4395434712                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3232000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3232000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 242936747093                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 242936747093                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 242936747093                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 242936747093                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     93373596                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     93373596                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     81116898                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     81116898                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       973984                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       973984                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1107304                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total      1107304                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2159365                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2159365                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2120295                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2120295                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    174490494                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    174490494                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    175464478                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    175464478                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.075911                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.075911                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.095843                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.095843                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766063                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766063                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.761150                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.761150                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.130140                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.130140                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098597                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098597                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.085177                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.085177                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088957                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.088957                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14934.867826                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14934.867826                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17631.629103                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17631.629103                       # average WriteReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 54130.313941                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 54130.313941                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14324.343221                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14324.343221                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21025.255134                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21025.255134                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16345.521190                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16345.521190                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15564.167435                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15564.167435                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     13488103                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets     19786702                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           752105                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         757651                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    17.933803                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    26.115853                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      4276528                       # number of writebacks
system.cpu0.dcache.writebacks::total          4276528                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3664529                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      3664529                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6233308                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      6233308                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data         4741                       # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         4741                       # number of WriteInvalidateReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       141328                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       141328                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      9897837                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      9897837                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      9897837                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      9897837                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3423563                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3423563                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1541188                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1541188                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       739665                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       739665                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       838083                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       838083                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       139692                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       139692                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       209050                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       209050                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4964751                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4964751                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5704416                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5704416                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  44975748199                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  44975748199                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  28501279892                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  28501279892                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16804666332                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16804666332                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  43773018566                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  43773018566                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1737566757                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1737566757                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3967184288                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3967184288                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3082000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3082000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  73477028091                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  73477028091                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  90281694423                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  90281694423                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5575976491                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5575976491                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5325987989                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5325987989                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10901964480                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10901964480                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036665                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036665                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019000                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019000                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.759422                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.759422                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.756868                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.756868                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064691                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064691                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098595                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098595                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028453                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028453                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032510                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032510                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13137.117149                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13137.117149                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18493.058531                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18493.058531                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22719.293642                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22719.293642                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 52229.932556                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 52229.932556                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12438.555945                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12438.555945                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18977.203004                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18977.203004                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14799.740831                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14799.740831                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15826.632283                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15826.632283                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          6368542                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.961816                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          222275153                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          6369054                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            34.899241                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      14184385750                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.961816                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999925                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999925                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          202                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        464315009                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       464315009                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    222275153                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      222275153                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    222275153                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       222275153                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    222275153                       # number of overall hits
system.cpu0.icache.overall_hits::total      222275153                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6697664                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      6697664                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6697664                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       6697664                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6697664                       # number of overall misses
system.cpu0.icache.overall_misses::total      6697664                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  70928372732                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  70928372732                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  70928372732                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  70928372732                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  70928372732                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  70928372732                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    228972817                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    228972817                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    228972817                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    228972817                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    228972817                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    228972817                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029251                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.029251                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029251                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.029251                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029251                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.029251                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10590.016569                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10590.016569                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10590.016569                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10590.016569                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10590.016569                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10590.016569                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      8781241                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          821                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           708037                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             11                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.402235                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets    74.636364                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       328289                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       328289                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       328289                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       328289                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       328289                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       328289                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6369375                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      6369375                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6369375                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      6369375                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6369375                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      6369375                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  57966761800                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  57966761800                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  57966761800                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  57966761800                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  57966761800                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  57966761800                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1699560248                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1699560248                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1699560248                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1699560248                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027817                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027817                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027817                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.027817                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027817                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.027817                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9100.855547                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9100.855547                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9100.855547                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9100.855547                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9100.855547                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9100.855547                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      8232125                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      8569505                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit       292099                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1116447                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2928300                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16202.554411                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          13089790                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2944355                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            4.445724                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      2067342500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  7528.605833                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    71.466332                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    91.040507                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  3487.680197                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  4098.714387                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   925.047154                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.459510                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004362                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005557                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.212871                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.250166                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.056460                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.988925                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1513                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023          121                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14421                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           66                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          709                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          196                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          537                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1           13                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           70                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           31                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          818                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         6042                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         2879                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4513                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.092346                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.007385                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.880188                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       298616625                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      298616625                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       582155                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       182687                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      5666433                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data      3184946                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       9616221                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      4276521                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      4276521                       # number of Writeback hits
system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       198743                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.WriteInvalidateReq_hits::total       198743                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       114761                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total       114761                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36815                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        36815                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       991246                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       991246                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       582155                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       182687                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      5666433                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      4176192                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       10607467                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       582155                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       182687                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      5666433                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      4176192                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      10607467                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12607                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9261                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst       702626                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data      1115482                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total      1839976                       # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks            4                       # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total            4                       # number of Writeback misses
system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data       637762                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::total       637762                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       138114                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       138114                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       172230                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       172230                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       309290                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       309290                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12607                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9261                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       702626                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1424772                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2149266                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12607                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9261                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       702626                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1424772                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2149266                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    468497682                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    383886915                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  20661944862                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  39743352793                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total  61257682252                       # number of ReadReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data    212101792                       # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total    212101792                       # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2828322980                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2828322980                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3448129857                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3448129857                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      3007000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      3007000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16311576734                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  16311576734                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    468497682                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    383886915                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  20661944862                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  56054929527                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  77569258986                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    468497682                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    383886915                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  20661944862                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  56054929527                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  77569258986                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       594762                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       191948                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      6369059                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data      4300428                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total     11456197                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      4276525                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      4276525                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       836505                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::total       836505                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       252875                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       252875                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       209045                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       209045                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1300536                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1300536                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       594762                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       191948                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      6369059                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5600964                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     12756733                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       594762                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       191948                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      6369059                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5600964                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     12756733                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021197                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.048247                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.110319                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.259389                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.160610                       # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000001                       # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total     0.000001                       # miss rate for Writeback accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.762413                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.762413                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.546175                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.546175                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.823890                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.823890                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.237817                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.237817                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021197                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.048247                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.110319                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.254380                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.168481                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021197                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.048247                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.110319                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.254380                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.168481                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37161.710320                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41451.993845                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29406.746779                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 35628.860701                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33292.652867                       # average ReadReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data   332.572013                       # average WriteInvalidateReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total   332.572013                       # average WriteInvalidateReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20478.177303                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20478.177303                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20020.495018                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20020.495018                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       601400                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       601400                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 52738.778279                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 52738.778279                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37161.710320                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41451.993845                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29406.746779                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39343.087545                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 36091.046425                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37161.710320                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41451.993845                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29406.746779                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39343.087545                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 36091.046425                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          272                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               7                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    38.857143                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1592666                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1592666                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            3                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          178                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst            3                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         5842                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total         6026                       # number of ReadReq MSHR hits
system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data           65                       # number of WriteInvalidateReq MSHR hits
system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total           65                       # number of WriteInvalidateReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        39394                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total        39394                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          178                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            3                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        45236                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        45420                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            3                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          178                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            3                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        45236                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        45420                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12604                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9083                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       702623                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data      1109640                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total      1833950                       # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks            4                       # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total            4                       # number of Writeback MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       823501                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       823501                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data       637697                       # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total       637697                       # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       138114                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       138114                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       172230                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       172230                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       269896                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       269896                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12604                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9083                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       702623                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1379536                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      2103846                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12604                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         9083                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       702623                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1379536                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       823501                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2927347                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    379527210                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    312895441                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  15722901634                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  31613467375                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  48028791660                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  55041075389                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  55041075389                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  36305734974                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  36305734974                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2408365451                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2408365451                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2333282169                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2333282169                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2482000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2482000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  11186143543                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  11186143543                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    379527210                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    312895441                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  15722901634                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  42799610918                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  59214935203                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    379527210                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    312895441                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  15722901634                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  42799610918                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  55041075389                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 114256010592                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1519174250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5322353508                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6841527758                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5082599974                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5082599974                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1519174250                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10404953482                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11924127732                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021192                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.047320                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.110318                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.258030                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.160084                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000001                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.762335                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.762335                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.546175                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.546175                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.823890                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.823890                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.207527                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.207527                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021192                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.047320                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.110318                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.246303                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.164920                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021192                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.047320                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.110318                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.246303                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229475                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22377.436597                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 28489.841187                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26188.713793                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66837.897451                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 56932.579225                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 56932.579225                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17437.518651                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17437.518651                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13547.478192                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13547.478192                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       496400                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       496400                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41446.125704                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41446.125704                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22377.436597                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31024.642284                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28146.040729                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22377.436597                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31024.642284                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39030.566104                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq      13921371                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     11750633                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        31686                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        31686                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      4276525                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1274288                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            6                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1162561                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       836505                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       509905                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       381643                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       535354                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           87                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          157                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1437620                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1309284                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     12781022                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18390339                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       414542                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1294088                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         32879991                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    407960480                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    693234728                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1535584                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4758096                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1107488888                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    4767578                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     22911203                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.193957                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.395396                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5          18467409     80.60%     80.60% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6           4443794     19.40%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      22911203                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   14408211332                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    208870495                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   9596174213                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   9165770534                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    223497560                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    700918244                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              124370032                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         83075187                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          6189003                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            87824878                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               56905034                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            64.793752                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               16687776                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            168367                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   538943                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               538943                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11373                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        87574                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       237839                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       301104                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  1852.353340                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 11107.804354                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-32767       297190     98.70%     98.70% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-65535         2030      0.67%     99.37% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-98303          795      0.26%     99.64% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-131071          637      0.21%     99.85% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-163839          257      0.09%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::163840-196607           66      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-229375           39      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::229376-262143           29      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-294911           48      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::294912-327679            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       301104                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       268131                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 15772.437909                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 12981.371112                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15992.673962                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       265367     98.97%     98.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1941      0.72%     99.69% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          396      0.15%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143          232      0.09%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679          106      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           37      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           35      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       268131                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 435751861088                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.614829                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.532518                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 434859464588     99.80%     99.80% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3    474800000      0.11%     99.90% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5    202701000      0.05%     99.95% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7     89682000      0.02%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9     62866500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11     34103000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13     13310500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15     14713000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       214000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19         6500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 435751861088                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        87574     88.51%     88.51% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        11373     11.49%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        98947                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       538943                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       538943                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        98947                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        98947                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       637890                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    91392867                       # DTB read hits
system.cpu1.dtb.read_misses                    373745                       # DTB read misses
system.cpu1.dtb.write_hits                   75805429                       # DTB write hits
system.cpu1.dtb.write_misses                   165198                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              45064                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1074                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   37451                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      309                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  5879                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    40297                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                91766612                       # DTB read accesses
system.cpu1.dtb.write_accesses               75970627                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        167198296                       # DTB hits
system.cpu1.dtb.misses                         538943                       # DTB misses
system.cpu1.dtb.accesses                    167737239                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    85244                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                85244                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          675                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        61262                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore         9941                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        75303                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1139.330438                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  8399.837182                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767        74771     99.29%     99.29% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535          180      0.24%     99.53% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303          193      0.26%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071          128      0.17%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839           12      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911            6      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        75303                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        71878                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 20268.763168                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 17115.147893                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 19721.935997                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        70231     97.71%     97.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071         1324      1.84%     99.55% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          179      0.25%     99.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           68      0.09%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           46      0.06%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        71878                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 397094361424                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.878531                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.326828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    48253813024     12.15%     12.15% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   348822790900     87.84%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       16535000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        1219500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4           3000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 397094361424                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        61262     98.91%     98.91% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          675      1.09%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        61937                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        85244                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        85244                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        61937                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        61937                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       147181                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   196146030                       # ITB inst hits
system.cpu1.itb.inst_misses                     85244                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              45064                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1074                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   26780                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   213163                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               196231274                       # ITB inst accesses
system.cpu1.itb.hits                        196146030                       # DTB hits
system.cpu1.itb.misses                          85244                       # DTB misses
system.cpu1.itb.accesses                    196231274                       # DTB accesses
system.cpu1.numCycles                       664388878                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          79880322                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     552169788                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  124370032                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          73592810                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    551328487                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               13340182                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   1707326                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles              246511                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles      6080767                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       727313                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles       602439                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                195911596                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              1586691                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  28723                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         647243256                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.003235                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.226187                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               336573756     52.00%     52.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1               120960986     18.69%     70.69% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                40749741      6.30%     76.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3               148958773     23.01%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           647243256                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.187195                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.831094                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                96356177                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            306396299                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                204571849                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             35206357                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               4712574                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            17589142                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1996203                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             573391383                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts             21361954                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               4712574                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               129172911                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               40460241                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     212107385                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                206565063                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             54225082                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             557977037                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts              5352379                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents              8193976                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                222351                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                303036                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              21276416                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents           13923                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          530659712                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            862978619                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       659902858                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           766208                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            478267677                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                52392029                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          15246817                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      13453544                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 71065053                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            91863812                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           78915989                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          8629555                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         7664780                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 536633802                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           15513444                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                541699362                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued          2485495                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       46695905                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     31776612                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        271399                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    647243256                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.836933                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.069144                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          349912497     54.06%     54.06% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1          127097301     19.64%     73.70% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2          103346931     15.97%     89.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           59640858      9.21%     98.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            7242720      1.12%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               2949      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      647243256                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu               54464030     43.99%     43.99% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 55578      0.04%     44.03% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                  15828      0.01%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               9      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead              33234382     26.84%     70.89% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite             36043585     29.11%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               12      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            369233279     68.16%     68.16% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1193564      0.22%     68.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                69127      0.01%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  2      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                1      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         46847      0.01%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.40% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            94164053     17.38%     85.79% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           76992429     14.21%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             541699362                       # Type of FU issued
system.cpu1.iq.rate                          0.815335                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                  123813412                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.228565                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1855831634                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        598546046                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    526634223                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1109251                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            439129                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       408402                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             664822270                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 690492                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         2431611                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     11396985                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        16347                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       143339                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      5491640                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      2526857                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      3486247                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               4712574                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                5829545                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1427417                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          552265728                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             91863812                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            78915989                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          13236985                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 56254                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              1314129                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        143339                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       1858186                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2653609                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4511795                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            534690067                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             91388435                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          6481283                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       118482                       # number of nop insts executed
system.cpu1.iew.exec_refs                   167194328                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               100087893                       # Number of branches executed
system.cpu1.iew.exec_stores                  75805893                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.804785                       # Inst execution rate
system.cpu1.iew.wb_sent                     527704335                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    527042625                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                254576573                       # num instructions producing a value
system.cpu1.iew.wb_consumers                416898701                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.793274                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.610644                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       43642021                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       15242045                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4231486                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    638973832                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.786200                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.579868                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    417556945     65.35%     65.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1    116379063     18.21%     83.56% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     48152991      7.54%     91.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     16068254      2.51%     93.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     11811974      1.85%     95.46% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      7886914      1.23%     96.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5403679      0.85%     97.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3345009      0.52%     98.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     12369003      1.94%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    638973832                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           426124677                       # Number of instructions committed
system.cpu1.commit.committedOps             502361434                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     153891175                       # Number of memory references committed
system.cpu1.commit.loads                     80466826                       # Number of loads committed
system.cpu1.commit.membars                    3635433                       # Number of memory barriers committed
system.cpu1.commit.branches                  94895008                       # Number of branches committed
system.cpu1.commit.fp_insts                    399904                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                461321486                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            12405087                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       347396188     69.15%     69.15% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult         977319      0.19%     69.35% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           55389      0.01%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        41321      0.01%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       80466826     16.02%     85.38% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      73424349     14.62%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        502361434                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             12369003                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                  1168820475                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1100237743                       # The number of ROB writes
system.cpu1.timesIdled                         913492                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       17145622                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 94026381638                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  426124677                       # Number of Instructions Simulated
system.cpu1.committedOps                    502361434                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.559142                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.559142                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.641378                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.641378                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               632226075                       # number of integer regfile reads
system.cpu1.int_regfile_writes              374528717                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   661926                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  331836                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                114587184                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               115385602                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             2619636946                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              15333141                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements          5236220                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          457.332610                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          143091306                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5236730                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            27.324553                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8478701081000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   457.332610                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.893228                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.893228                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          159                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        319394188                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       319394188                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     74655263                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       74655263                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     64023189                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      64023189                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       163779                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       163779                       # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        39797                       # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total        39797                       # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1738928                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1738928                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1751406                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1751406                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    138678452                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       138678452                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    138842231                       # number of overall hits
system.cpu1.dcache.overall_hits::total      138842231                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      6126939                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      6126939                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      6982821                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      6982821                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       659533                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       659533                       # number of SoftPFReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       425377                       # number of WriteInvalidateReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::total       425377                       # number of WriteInvalidateReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       260578                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       260578                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       204152                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       204152                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data     13109760                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total      13109760                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data     13769293                       # number of overall misses
system.cpu1.dcache.overall_misses::total     13769293                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  92549514245                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  92549514245                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 116311286360                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 116311286360                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  11708163921                       # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  11708163921                       # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3758503444                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   3758503444                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4320848660                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4320848660                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3489000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3489000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 208860800605                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 208860800605                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 208860800605                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 208860800605                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     80782202                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     80782202                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     71006010                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     71006010                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       823312                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       823312                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       465174                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total       465174                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1999506                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1999506                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1955558                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1955558                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    151788212                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    151788212                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    152611524                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    152611524                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.075845                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.075845                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.098341                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.098341                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.801073                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.801073                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.914447                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.914447                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.130321                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.130321                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.104396                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.104396                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.086369                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.086369                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.090224                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.090224                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15105.342855                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15105.342855                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16656.776160                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 16656.776160                       # average WriteReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.205401                       # average WriteInvalidateReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.205401                       # average WriteInvalidateReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14423.717444                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14423.717444                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21164.860790                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21164.860790                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15931.702839                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15931.702839                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15168.592941                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15168.592941                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs      2855420                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets     17544431                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs           337066                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets         700468                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     8.471397                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    25.046727                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3392584                       # number of writebacks
system.cpu1.dcache.writebacks::total          3392584                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3127909                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total      3127909                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5647115                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      5647115                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data         3296                       # number of WriteInvalidateReq MSHR hits
system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total         3296                       # number of WriteInvalidateReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       132105                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total       132105                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      8775024                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      8775024                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      8775024                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      8775024                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2999030                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2999030                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1335706                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1335706                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       659449                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       659449                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       422081                       # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       422081                       # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       128473                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       128473                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       204145                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       204145                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4334736                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4334736                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4994185                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4994185                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38225367292                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38225367292                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  21845579142                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  21845579142                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  15240654080                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  15240654080                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  10753431338                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  10753431338                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1629520255                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1629520255                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3904363340                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3904363340                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3325000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3325000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  60070946434                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  60070946434                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  75311600514                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  75311600514                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    796916503                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    796916503                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    897774501                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    897774501                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1694691004                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1694691004                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037125                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037125                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018811                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018811                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.800971                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.800971                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.907362                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.907362                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064252                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064252                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.104392                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.104392                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028558                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.028558                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032725                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.032725                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12745.910275                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12745.910275                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16355.080491                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16355.080491                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23111.194467                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23111.194467                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25477.174613                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25477.174613                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12683.756548                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12683.756548                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19125.441916                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19125.441916                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13858.040359                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13858.040359                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15079.857978                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15079.857978                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          5522406                       # number of replacements
system.cpu1.icache.tags.tagsinuse          501.856310                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          190094169                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5522918                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            34.419155                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8518418347000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.856310                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980188                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.980188                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          335                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        397333844                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       397333844                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    190094169                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      190094169                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    190094169                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       190094169                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    190094169                       # number of overall hits
system.cpu1.icache.overall_hits::total      190094169                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      5811281                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      5811281                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      5811281                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       5811281                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      5811281                       # number of overall misses
system.cpu1.icache.overall_misses::total      5811281                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  61520167992                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  61520167992                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  61520167992                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  61520167992                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  61520167992                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  61520167992                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    195905450                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    195905450                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    195905450                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    195905450                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    195905450                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    195905450                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029664                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.029664                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029664                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.029664                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029664                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.029664                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10586.335094                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10586.335094                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10586.335094                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10586.335094                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10586.335094                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10586.335094                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs      7857995                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets           39                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs           642168                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.236665                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets           39                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       288337                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total       288337                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst       288337                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total       288337                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst       288337                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total       288337                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5522944                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5522944                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5522944                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5522944                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5522944                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5522944                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  50254087338                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  50254087338                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  50254087338                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  50254087338                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  50254087338                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  50254087338                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5802498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5802498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5802498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      5802498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028192                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028192                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028192                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.028192                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028192                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.028192                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9099.148450                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9099.148450                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9099.148450                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  9099.148450                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9099.148450                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  9099.148450                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7021877                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7194867                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit       149461                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       884477                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2159012                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13531.891931                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          11463233                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2175036                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            5.270365                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9606894527000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5515.011217                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    81.352016                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    87.650961                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3854.550779                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3125.340880                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   867.986079                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.336610                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004965                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005350                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.235263                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.190756                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.052978                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.825921                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1495                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           53                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14476                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           35                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          465                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          510                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          477                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1150                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5680                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4086                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3438                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.091248                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003235                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.883545                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       250860566                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      250860566                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       536921                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       182584                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      4917912                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data      2781477                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       8418894                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3392565                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3392565                       # number of Writeback hits
system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       191757                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.WriteInvalidateReq_hits::total       191757                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        71744                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        71744                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        31465                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        31465                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       867581                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       867581                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       536921                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       182584                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4917912                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3649058                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        9286475                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       536921                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       182584                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4917912                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3649058                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       9286475                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12339                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9008                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst       605020                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data      1001664                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total      1628031                       # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks           17                       # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total           17                       # number of Writeback misses
system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       228944                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::total       228944                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       145584                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       145584                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       172667                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       172667                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           13                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total           13                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       259180                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       259180                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12339                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9008                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       605020                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1260844                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1887211                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12339                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9008                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       605020                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1260844                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1887211                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    492758189                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    397546188                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  17874502757                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  34268686598                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total  53033493732                       # number of ReadReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data    241449363                       # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total    241449363                       # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2956550746                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   2956550746                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3438458831                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3438458831                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3243000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3243000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10870225593                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10870225593                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    492758189                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    397546188                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  17874502757                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  45138912191                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  63903719325                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    492758189                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    397546188                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  17874502757                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  45138912191                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  63903719325                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       549260                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       191592                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      5522932                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3783141                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total     10046925                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3392582                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3392582                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       420701                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::total       420701                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       217328                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       217328                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       204132                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       204132                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           13                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           13                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1126761                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1126761                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       549260                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       191592                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5522932                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4909902                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     11173686                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       549260                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       191592                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5522932                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4909902                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     11173686                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022465                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.047017                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.109547                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.264770                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.162043                       # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000005                       # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total     0.000005                       # miss rate for Writeback accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.544196                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.544196                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.669881                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.669881                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.845860                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.845860                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.230022                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.230022                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022465                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.047017                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.109547                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.256796                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.168898                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022465                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.047017                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.109547                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.256796                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.168898                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39935.018154                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44132.569716                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29543.656006                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34211.758232                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32575.235811                       # average ReadReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data  1054.621929                       # average WriteInvalidateReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total  1054.621929                       # average WriteInvalidateReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20308.212070                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20308.212070                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19913.815790                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19913.815790                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 249461.538462                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 249461.538462                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41940.834914                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41940.834914                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39935.018154                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44132.569716                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29543.656006                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35800.552797                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 33861.459755                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39935.018154                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44132.569716                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29543.656006                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35800.552797                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 33861.459755                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            9                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs     4.500000                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks       971322                       # number of writebacks
system.cpu1.l2cache.writebacks::total          971322                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            2                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          153                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst            1                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data         6612                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total         6768                       # number of ReadReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data           63                       # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total           63                       # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        20490                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total        20490                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            2                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          153                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data        27102                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        27258                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            2                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          153                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data        27102                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        27258                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12337                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8855                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       605019                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data       995052                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total      1621263                       # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks           17                       # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total           17                       # number of Writeback MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       705681                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       705681                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data       228881                       # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total       228881                       # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       145584                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       145584                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       172667                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       172667                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           13                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           13                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       238690                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       238690                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12337                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8855                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       605019                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1233742                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1859953                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12337                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8855                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       605019                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1233742                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       705681                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2565634                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    405599231                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    327287462                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  13621135743                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  26954578760                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  41308601196                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  39485552404                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  39485552404                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   6916972959                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   6916972959                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2477712924                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2477712924                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2304203121                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2304203121                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2669000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2669000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7509818481                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7509818481                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    405599231                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    327287462                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13621135743                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34464397241                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  48818419677                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    405599231                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    327287462                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13621135743                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34464397241                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  39485552404                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  88303972081                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5233250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    741632996                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    746866246                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    846035990                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    846035990                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5233250                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1587668986                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1592902236                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022461                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.046218                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.109547                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.263023                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.161369                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000005                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000005                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.544047                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.544047                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.669881                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.669881                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.845860                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.845860                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.211837                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.211837                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022461                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.046218                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.109547                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.251276                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.166458                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022461                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.046218                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.109547                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.251276                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.229614                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22513.566918                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27088.613218                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25479.272145                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55953.826735                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30220.826364                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30220.826364                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17019.129327                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17019.129327                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13344.779958                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13344.779958                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 205307.692308                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 205307.692308                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31462.643936                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31462.643936                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22513.566918                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27934.849621                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26247.125426                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22513.566918                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27934.849621                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34417.992621                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq      12802922                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     10291743                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         6895                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         6895                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      3392582                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq      1076196                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp           13                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1156933                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       420701                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       464615                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       376292                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       486818                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           88                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          157                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1296360                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1132878                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     11046012                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15089863                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       415115                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1210522                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         27761512                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    353468736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    564735319                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1532736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4394080                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         924130871                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5316111                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     20559073                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.243524                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.429209                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5          15552442     75.65%     75.65% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6           5006631     24.35%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      20559073                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   11602796673                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    182870488                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   8299279905                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7848510644                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    224378946                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    662954125                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40399                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40399                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136785                       # Transaction distribution
system.iobus.trans_dist::WriteResp              30057                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48154                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       123088                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231200                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231200                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354368                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48174                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156195                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7497097                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36604000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy          1043087367                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            93034000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           179187461                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115604                       # number of replacements
system.iocache.tags.tagsinuse               11.301402                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115620                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9117040369000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.419209                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.882193                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.463701                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.242637                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706338                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040757                       # Number of tag accesses
system.iocache.tags.data_accesses             1040757                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8872                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8909                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8872                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8912                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8872                       # number of overall misses
system.iocache.overall_misses::total             8912                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5707000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1954318592                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1960025592                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       357000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       357000                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28939092314                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  28939092314                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      6064000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1954318592                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1960382592                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      6064000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1954318592                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1960382592                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8872                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8909                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8872                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8912                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8872                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8912                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 220279.372408                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 220005.117522                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       119000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       119000                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271148.080298                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 271148.080298                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 220279.372408                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 219971.116697                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 220279.372408                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 219971.116697                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        228427                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27535                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.295878                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106702                       # number of writebacks
system.iocache.writebacks::total               106702                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8872                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8909                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106728                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106728                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8872                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8912                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8872                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8912                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3783000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1492830122                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1496613122                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23388843706                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23388843706                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3984000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1492830122                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1496814122                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3984000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1492830122                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1496814122                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168263.088593                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 167988.901336                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219144.401713                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219144.401713                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 168263.088593                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 167954.905969                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 168263.088593                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 167954.905969                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1613331                       # number of replacements
system.l2c.tags.tagsinuse                64339.343113                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4797018                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1673818                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.865914                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               3243842500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   19101.398352                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   185.742619                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   228.186438                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3981.341018                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    11353.199987                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11643.208368                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   179.349370                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   266.651363                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3248.685748                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     4974.329517                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  9177.250333                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.291464                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002834                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003482                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.060750                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.173236                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.177661                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002737                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.004069                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.049571                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.075902                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.140034                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.981740                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10683                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          245                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        49559                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0           76                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1           11                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          157                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          995                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9444                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::1            5                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          227                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          285                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3090                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         3968                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        42149                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.163010                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003738                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.756210                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 64781750                       # Number of tag accesses
system.l2c.tags.data_accesses                64781750                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         6508                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4319                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             640995                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             651108                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       307248                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         6236                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         4043                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             550704                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             545723                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher       278481                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2995365                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         2564009                       # number of Writeback hits
system.l2c.Writeback_hits::total              2564009                       # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data       138658                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data       123170                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total       261828                       # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data           30955                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           32781                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               63736                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          6525                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          5847                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             12372                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            54058                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            53543                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               107601                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6508                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4319                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              640995                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              705166                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       307248                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6236                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4043                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              550704                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              599266                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       278481                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3102966                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6508                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4319                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             640995                       # number of overall hits
system.l2c.overall_hits::cpu0.data             705166                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       307248                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6236                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4043                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             550704                       # number of overall hits
system.l2c.overall_hits::cpu1.data             599266                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       278481                       # number of overall hits
system.l2c.overall_hits::total                3102966                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2518                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2288                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            61626                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           165027                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       315511                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2810                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2444                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst            54313                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data           130678                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       226783                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               963998                       # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data       490361                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data        96104                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total       586465                       # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data         48125                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         46732                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             94857                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        10442                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         8446                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           18888                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          87770                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          52309                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140079                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2518                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2288                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             61626                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            252797                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       315511                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2810                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2444                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             54313                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            182987                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       226783                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1104077                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2518                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2288                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            61626                       # number of overall misses
system.l2c.overall_misses::cpu0.data           252797                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       315511                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2810                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2444                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            54313                       # number of overall misses
system.l2c.overall_misses::cpu1.data           182987                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       226783                       # number of overall misses
system.l2c.overall_misses::total              1104077                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    214285749                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    198628497                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   4954310957                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  15651071560                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  48231685466                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    246385494                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    217660244                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst   4359245951                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data  12707402041                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  33186692902                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total   119967368861                       # number of ReadReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu0.data     38113099                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu1.data     39381504                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::total     77494603                       # number of WriteInvalidateReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    206747895                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    214995003                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    421742898                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     39945327                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     36079463                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total     76024790                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   7797935308                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4285574180                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  12083509488                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    214285749                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    198628497                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   4954310957                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  23449006868                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  48231685466                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    246385494                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    217660244                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   4359245951                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  16992976221                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  33186692902                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    132050878349                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    214285749                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    198628497                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   4954310957                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  23449006868                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  48231685466                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    246385494                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    217660244                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   4359245951                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  16992976221                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  33186692902                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   132050878349                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         9026                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6607                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         702621                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         816135                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       622759                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         9046                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6487                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         605017                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         676401                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher       505264                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            3959363                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      2564009                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2564009                       # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data       629019                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data       219274                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total       848293                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        79080                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        79513                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          158593                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        16967                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        14293                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         31260                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       141828                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       105852                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247680                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         9026                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6607                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          702621                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          957963                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       622759                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         9046                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6487                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          605017                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          782253                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       505264                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4207043                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         9026                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6607                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         702621                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         957963                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       622759                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         9046                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6487                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         605017                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         782253                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       505264                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4207043                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.278972                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.346299                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.087709                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.202206                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.506634                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.310635                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.376754                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.089771                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.193196                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.243473                       # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.779565                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.438283                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total     0.691347                       # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.608561                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.587728                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.598116                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.615430                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.590919                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.604223                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.618848                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.494171                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.565564                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.278972                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.346299                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.087709                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.263890                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.506634                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.310635                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.376754                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.089771                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.233923                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.262435                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.278972                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.346299                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.087709                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.263890                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.506634                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.310635                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.376754                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.089771                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.233923                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.262435                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85101.568308                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 86813.154283                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.193733                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 94839.459967                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87681.670463                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89059.019640                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80261.557104                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 97242.091561                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 124447.736262                       # average ReadReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data    77.724572                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   409.780072                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::total   132.138496                       # average WriteInvalidateReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4296.060156                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4600.594946                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  4446.091464                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3825.447903                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4271.781080                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4025.031237                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88845.110038                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81928.046416                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 86262.105583                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85101.568308                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 86813.154283                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80393.193733                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 92758.248191                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87681.670463                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89059.019640                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80261.557104                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 92864.390481                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 119602.960979                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85101.568308                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 86813.154283                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80393.193733                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 92758.248191                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87681.670463                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89059.019640                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80261.557104                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 92864.390481                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 119602.960979                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             13381                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                      234                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     57.183761                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1241010                       # number of writebacks
system.l2c.writebacks::total                  1241010                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst           230                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            68                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst           210                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            83                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               591                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            230                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             68                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            210                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             83                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                591                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           230                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            68                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           210                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            83                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               591                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2518                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2288                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        61396                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       164959                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       315511                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2810                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2444                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst        54103                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data       130595                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       226783                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          963407                       # number of ReadReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data       490361                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data        96104                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::total       586465                       # number of WriteInvalidateReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        48125                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        46732                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        94857                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10442                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8446                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        18888                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        87770                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        52309                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140079                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2518                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2288                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        61396                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       252729                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       315511                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2810                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2444                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        54103                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       182904                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       226783                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1103486                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2518                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2288                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        61396                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       252729                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       315511                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2810                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2444                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        54103                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       182904                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       226783                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1103486                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    182832749                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    170078497                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   4169491707                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  13595488810                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  44400149466                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    211305994                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    187184244                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   3666713475                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data  11080588209                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  30429379906                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 108093213057                       # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data  23987646886                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   2627282944                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total  26614929830                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    490076505                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    479520804                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    969597309                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    106392293                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     85816866                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    192209159                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6696791958                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3633299230                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  10330091188                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    182832749                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    170078497                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   4169491707                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  20292280768                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  44400149466                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    211305994                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    187184244                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   3666713475                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  14713887439                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  30429379906                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 118423304245                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    182832749                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    170078497                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   4169491707                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  20292280768                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  44400149466                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    211305994                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    187184244                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   3666713475                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  14713887439                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  30429379906                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 118423304245                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1103208750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4750572496                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      3896750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    616502003                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6474179999                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4542606997                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    728363997                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5270970994                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1103208750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9293179493                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      3896750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1344866000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  11745150993                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.278972                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.346299                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.087381                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.202122                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.506634                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.310635                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.376754                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.089424                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.193073                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.243324                       # mshr miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.779565                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.438283                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.691347                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.608561                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.587728                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.598116                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.615430                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.590919                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.604223                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.618848                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.494171                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.565564                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.278972                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.346299                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.087381                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.263819                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.506634                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.310635                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.376754                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.089424                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.233817                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.262295                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.278972                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.346299                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.087381                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.263819                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.506634                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.310635                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.376754                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.089424                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.233817                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.262295                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67911.455258                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 82417.381349                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67772.830989                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 84846.955925                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 112198.907686                       # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48918.341561                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27337.914593                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 45381.957713                       # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10183.407896                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10261.080288                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10221.673772                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10188.880770                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10160.651906                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10176.257889                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76299.327310                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69458.395878                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 73744.752518                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67911.455258                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80292.648521                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67772.830989                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 80445.957655                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 107317.450557                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67911.455258                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80292.648521                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67772.830989                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 80445.957655                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 107317.450557                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq             1032278                       # Transaction distribution
system.membus.trans_dist::ReadResp            1032278                       # Transaction distribution
system.membus.trans_dist::WriteReq              38581                       # Transaction distribution
system.membus.trans_dist::WriteResp             38581                       # Transaction distribution
system.membus.trans_dist::Writeback           1347712                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       689975                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       689975                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           447979                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         332386                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          121150                       # Transaction distribution
system.membus.trans_dist::ReadExReq            152231                       # Transaction distribution
system.membus.trans_dist::ReadExResp           135895                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123088                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25972                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5571157                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5720295                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335903                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       335903                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6056198                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156195                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51944                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    187423448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    187632159                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14096832                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14096832                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               201728991                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           678374                       # Total snoops (count)
system.membus.snoop_fanout::samples           3943213                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3943213    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3943213                       # Request fanout histogram
system.membus.reqLayer0.occupancy            98700492                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               45500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21600991                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         19952700228                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy        11115498245                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          187180539                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            4932840                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4925609                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38581                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38581                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          2564009                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq       955023                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp       848293                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          504313                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        344758                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         849071                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          157                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          157                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           306644                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          306644                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8600677                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6275419                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              14876096                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    289885704                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    198430935                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              488316639                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1740265                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          9550575                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.012108                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.109370                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                9434933     98.79%     98.79% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 115642      1.21%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            9550575                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        18722164156                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          7552500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       13115425494                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       11201753623                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13602                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    5345                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------