path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.384351                       # Number of seconds simulated
sim_ticks                                47384351300000                       # Number of ticks simulated
final_tick                               47384351300000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 183431                       # Simulator instruction rate (inst/s)
host_op_rate                                   207694                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7126665146                       # Simulator tick rate (ticks/s)
host_mem_usage                                 777076                       # Number of bytes of host memory used
host_seconds                                  6648.88                       # Real time elapsed on the host
sim_insts                                  1219610005                       # Number of instructions simulated
sim_ops                                    1380933056                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       205248                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       202880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          4270112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         16788488                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     21729728                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       123968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        83584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3109600                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         10061712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     12393536                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        438400                       # Number of bytes read from this memory
system.physmem.bytes_read::total             69407256                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      4270112                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3109600                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7379712                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     85545984                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          85566568                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         3207                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         3170                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             82673                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            262333                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       339527                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1937                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1306                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             48631                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            157227                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       193649                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6850                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1100510                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1336656                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1339230                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          4332                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          4282                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               90117                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              354304                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       458584                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2616                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          1764                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               65625                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              212343                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       261553                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9252                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1464772                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          90117                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          65625                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             155742                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1805364                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1805798                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1805364                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         4332                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         4282                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              90117                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             354739                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       458584                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2616                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         1764                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              65625                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             212343                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       261553                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9252                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3270570                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1100510                       # Number of read requests accepted
system.physmem.writeReqs                      1339230                       # Number of write requests accepted
system.physmem.readBursts                     1100510                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1339230                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 70408640                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     24000                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  85564992                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  69407256                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               85566568                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      375                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2249                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               70416                       # Per bank write bursts
system.physmem.perBankRdBursts::1               75191                       # Per bank write bursts
system.physmem.perBankRdBursts::2               64063                       # Per bank write bursts
system.physmem.perBankRdBursts::3               69912                       # Per bank write bursts
system.physmem.perBankRdBursts::4               59812                       # Per bank write bursts
system.physmem.perBankRdBursts::5               69643                       # Per bank write bursts
system.physmem.perBankRdBursts::6               65430                       # Per bank write bursts
system.physmem.perBankRdBursts::7               68144                       # Per bank write bursts
system.physmem.perBankRdBursts::8               61950                       # Per bank write bursts
system.physmem.perBankRdBursts::9               89644                       # Per bank write bursts
system.physmem.perBankRdBursts::10              68037                       # Per bank write bursts
system.physmem.perBankRdBursts::11              70586                       # Per bank write bursts
system.physmem.perBankRdBursts::12              61163                       # Per bank write bursts
system.physmem.perBankRdBursts::13              71056                       # Per bank write bursts
system.physmem.perBankRdBursts::14              65094                       # Per bank write bursts
system.physmem.perBankRdBursts::15              69994                       # Per bank write bursts
system.physmem.perBankWrBursts::0               85481                       # Per bank write bursts
system.physmem.perBankWrBursts::1               90029                       # Per bank write bursts
system.physmem.perBankWrBursts::2               81966                       # Per bank write bursts
system.physmem.perBankWrBursts::3               85433                       # Per bank write bursts
system.physmem.perBankWrBursts::4               77921                       # Per bank write bursts
system.physmem.perBankWrBursts::5               84076                       # Per bank write bursts
system.physmem.perBankWrBursts::6               83054                       # Per bank write bursts
system.physmem.perBankWrBursts::7               85039                       # Per bank write bursts
system.physmem.perBankWrBursts::8               78873                       # Per bank write bursts
system.physmem.perBankWrBursts::9               84297                       # Per bank write bursts
system.physmem.perBankWrBursts::10              83224                       # Per bank write bursts
system.physmem.perBankWrBursts::11              86586                       # Per bank write bursts
system.physmem.perBankWrBursts::12              79852                       # Per bank write bursts
system.physmem.perBankWrBursts::13              85124                       # Per bank write bursts
system.physmem.perBankWrBursts::14              80745                       # Per bank write bursts
system.physmem.perBankWrBursts::15              85253                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                       51215                       # Number of times write queue was full causing retry
system.physmem.totGap                    47384349786500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1079152                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1336656                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    480448                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    272774                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     88894                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     67384                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     42690                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     36411                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     33268                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     30721                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     27820                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      7595                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     4180                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2606                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1628                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1243                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      684                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      590                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      501                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      173                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      105                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       17                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    24574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    28512                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    38198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    43791                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    48248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    52275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    57744                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    62191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    67593                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    69901                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    75312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    79272                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    77429                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    80341                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    90816                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    80863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    73646                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    69003                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     5131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     3743                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2880                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1733                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1620                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1427                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1364                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1515                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1785                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1829                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1988                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     2100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     2366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     2471                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                     2894                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                     3089                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                     3468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                     3580                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                     3839                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                     4719                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                     6200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                    24545                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                   120342                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1069816                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      145.794462                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      98.799028                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     192.755385                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         712470     66.60%     66.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       211048     19.73%     86.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        55044      5.15%     91.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        23596      2.21%     93.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        18557      1.73%     95.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        10547      0.99%     96.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7452      0.70%     97.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5550      0.52%     97.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        25552      2.39%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1069816                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         62458                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        17.613853                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       71.325725                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           62454     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           62458                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         62458                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        21.405633                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.660061                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev      609.107080                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-4095          62456    100.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45056-49151            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::143360-147455            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           62458                       # Writes before turning the bus around for reads
system.physmem.totQLat                    48895390505                       # Total ticks spent queuing
system.physmem.totMemAccLat               69522921755                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5500675000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       44444.90                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  63194.90                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.49                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.81                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.46                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.81                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.21                       # Average write queue length when enqueuing
system.physmem.readRowHits                     830166                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    537104                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.46                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  40.17                       # Row buffer hit rate for writes
system.physmem.avgGap                     19421885.03                       # Average gap between requests
system.physmem.pageHitRate                      56.10                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 4087639080                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2230358625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4232326800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4361033520                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3094915112640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1166279241240                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27407555547000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31683661258905                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.652499                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45594888254330                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1582267440000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    207195159170                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 4000169880                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2182632375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4348679400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4302421920                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3094915112640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1168435080135                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27405664460250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31683848556600                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.656452                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45591701065782                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1582267440000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    210382633218                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           556                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          368                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           23                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           11                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              199183431                       # Number of BP lookups
system.cpu0.branchPred.condPredicted        140489040                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          7036065                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups           156342542                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               99990575                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            63.956089                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               20013017                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            198399                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4618183                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           2919648                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses         1698535                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted       412858                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   607513                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               607513                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13877                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        97395                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       289192                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       318321                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2219.643065                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 12711.673990                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       315923     99.25%     99.25% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         1786      0.56%     99.81% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          409      0.13%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          127      0.04%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679           41      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           31      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       318321                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       324666                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 20482.457356                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 17703.017560                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16938.599592                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       320665     98.77%     98.77% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         2783      0.86%     99.62% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          369      0.11%     99.74% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          625      0.19%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          139      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           57      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           21      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       324666                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 513372677252                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.571567                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.552695                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 512028975252     99.74%     99.74% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3    726675000      0.14%     99.88% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5    290458500      0.06%     99.94% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7    129299000      0.03%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9    102361000      0.02%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11     55725500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13     16517000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15     21785000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       858500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19        22500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 513372677252                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        97395     87.53%     87.53% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        13877     12.47%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       111272                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       607513                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       607513                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       111272                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       111272                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       718785                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   141538315                       # DTB read hits
system.cpu0.dtb.read_misses                    437252                       # DTB read misses
system.cpu0.dtb.write_hits                   86796370                       # DTB write hits
system.cpu0.dtb.write_misses                   170261                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              44490                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   43183                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      271                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  6902                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    42288                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               141975567                       # DTB read accesses
system.cpu0.dtb.write_accesses               86966631                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        228334685                       # DTB hits
system.cpu0.dtb.misses                         607513                       # DTB misses
system.cpu0.dtb.accesses                    228942198                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    87943                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                87943                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1130                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        62851                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        10253                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        77690                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1458.353713                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 10159.922633                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        76707     98.73%     98.73% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          405      0.52%     99.26% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303          337      0.43%     99.69% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071          198      0.25%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839            9      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607           14      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        77690                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        74234                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26234.178409                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23080.051735                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 21732.027543                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        71871     96.82%     96.82% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071         1986      2.68%     99.49% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          153      0.21%     99.70% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143          128      0.17%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           62      0.08%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           21      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        74234                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 410290287148                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.846605                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.360675                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    62979367364     15.35%     15.35% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   347270506784     84.64%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       38246000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        1931000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         236000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 410290287148                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        62851     98.23%     98.23% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         1130      1.77%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        63981                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        87943                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        87943                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        63981                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        63981                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       151924                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   282848559                       # ITB inst hits
system.cpu0.itb.inst_misses                     87943                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              44490                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   30949                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   212727                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               282936502                       # ITB inst accesses
system.cpu0.itb.hits                        282848559                       # DTB hits
system.cpu0.itb.misses                          87943                       # DTB misses
system.cpu0.itb.accesses                    282936502                       # DTB accesses
system.cpu0.numPwrStateTransitions              28168                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples        14084                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    3333377849.836978                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   92382687873.308472                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         4020     28.54%     28.54% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10        10033     71.24%     99.78% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11           12      0.09%     99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            2      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.91% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           13      0.09%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 6914082605000                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total          14084                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   437057662896                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46947293637104                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       874125395                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          92275983                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     768900237                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  199183431                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches         122923240                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    738928784                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               15190816                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   2037144                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles              294842                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      6072240                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       792344                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles       839757                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                282635522                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              1737700                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  28623                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         848836502                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.034930                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.208968                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               416377385     49.05%     49.05% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1               176079063     20.74%     69.80% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                66732959      7.86%     77.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3               189647095     22.34%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           848836502                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.227866                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.879622                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               110330106                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            381856903                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                311429263                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             39757521                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5462709                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            29836532                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              2173523                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             791623702                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts             24444549                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5462709                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               147675961                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               53914284                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     258297798                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                313275075                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             70210675                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             773227105                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              6509157                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents             10689754                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                377832                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                811571                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              32991272                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents           11799                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          742885425                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups           1169549966                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       880889153                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           700737                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            682115784                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                60769635                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          16576266                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      14423738                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 79729853                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           141637487                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           90242008                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          9692958                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         8374311                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 749539213                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           16620515                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                754385019                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued          2849937                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       57154900                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     36998097                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        294454                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    848836502                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.888728                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.088535                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          442949824     52.18%     52.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1          161566736     19.03%     71.22% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2          148384909     17.48%     88.70% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           87697049     10.33%     99.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            8232602      0.97%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5               5382      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      848836502                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               74538342     48.88%     48.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 62447      0.04%     48.92% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                  15099      0.01%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               9      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     48.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead              37581602     24.64%     73.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite             40298347     26.43%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass               51      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            519755806     68.90%     68.90% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1543884      0.20%     69.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                77211      0.01%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                 64      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   2      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                1      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         42719      0.01%     69.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.12% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           144854124     19.20%     88.32% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           88111156     11.68%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             754385019                       # Type of FU issued
system.cpu0.iq.rate                          0.863017                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                  152495846                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.202146                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        2511823586                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        823027375                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    736101219                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1128735                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            443604                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       415332                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             906176667                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 704147                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         2868207                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     13104832                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        17724                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       157642                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      5794849                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2875718                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      4918474                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5462709                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                7926079                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1884320                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          766295642                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            141637487                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            90242008                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          14144816                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 61216                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1749510                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        157642                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2035907                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      3235941                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             5271848                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            745963336                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            141529970                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          7821454                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       135914                       # number of nop insts executed
system.cpu0.iew.exec_refs                   228324326                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               170531782                       # Number of branches executed
system.cpu0.iew.exec_stores                  86794356                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.853383                       # Inst execution rate
system.cpu0.iew.wb_sent                     737330155                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    736516551                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                351214969                       # num instructions producing a value
system.cpu0.iew.wb_consumers                595098705                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.842575                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.590179                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       49835507                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       16326061                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4903366                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    839368834                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.844688                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.533259                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    512658006     61.08%     61.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1    158759517     18.91%     79.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     92536082     11.02%     91.02% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     27862473      3.32%     94.33% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     13576189      1.62%     95.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      9358920      1.11%     97.07% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      6289735      0.75%     97.82% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3875341      0.46%     98.28% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     14452571      1.72%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    839368834                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           622433451                       # Number of instructions committed
system.cpu0.commit.committedOps             709004821                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     212979813                       # Number of memory references committed
system.cpu0.commit.loads                    128532654                       # Number of loads committed
system.cpu0.commit.membars                    3921678                       # Number of memory barriers committed
system.cpu0.commit.branches                 164749224                       # Number of branches committed
system.cpu0.commit.fp_insts                    407380                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                634275437                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            14942203                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       494636379     69.76%     69.76% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1291078      0.18%     69.95% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           60530      0.01%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        37021      0.01%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.96% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead      128532654     18.13%     88.09% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      84447159     11.91%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        709004821                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             14452571                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1579278211                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1527109253                       # The number of ROB writes
system.cpu0.timesIdled                        1033857                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       25288893                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 93894577230                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  622433451                       # Number of Instructions Simulated
system.cpu0.committedOps                    709004821                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.404368                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.404368                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.712064                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.712064                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               848778973                       # number of integer regfile reads
system.cpu0.int_regfile_writes              506977822                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   685984                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  317032                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                188384037                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               189031095                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1602344785                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              16401028                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          6409966                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          480.619482                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          199938758                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6410478                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            31.189368                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1908955000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.619482                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938710                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.938710                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          395                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        439216738                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       439216738                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data    121629785                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      121629785                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     73254039                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      73254039                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       225954                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       225954                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       195110                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       195110                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1865486                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1865486                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1919454                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1919454                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    195078934                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       195078934                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    195304888                       # number of overall hits
system.cpu0.dcache.overall_hits::total      195304888                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      7140435                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7140435                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      8024708                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      8024708                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       776369                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       776369                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       838591                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       838591                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       289464                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       289464                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       195968                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       195968                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     16003734                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      16003734                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     16780103                       # number of overall misses
system.cpu0.dcache.overall_misses::total     16780103                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108528058000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 108528058000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 153779451872                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 153779451872                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  31763636892                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  31763636892                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4317295000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4317295000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4927286000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4927286000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3123500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3123500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 294071146764                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 294071146764                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 294071146764                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 294071146764                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data    128770220                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    128770220                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     81278747                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     81278747                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data      1002323                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1002323                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1033701                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1033701                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2154950                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2154950                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2115422                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2115422                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    211082668                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    211082668                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    212084991                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    212084991                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.055451                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.055451                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.098731                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.098731                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.774570                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.774570                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.811251                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.811251                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.134325                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.134325                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.092638                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.092638                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.075817                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.075817                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.079120                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.079120                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15199.082129                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15199.082129                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19163.245799                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.245799                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37877.388252                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37877.388252                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14914.790786                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14914.790786                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25143.319317                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25143.319317                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18375.158370                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 18375.158370                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17524.990566                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17524.990566                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      9668545                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets     23532840                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           779892                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         794197                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    12.397287                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    29.630986                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      6410042                       # number of writebacks
system.cpu0.dcache.writebacks::total          6410042                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3690786                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      3690786                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6446005                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      6446005                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4347                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         4347                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       149571                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       149571                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data     10141138                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total     10141138                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data     10141138                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total     10141138                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3449649                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3449649                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1578703                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1578703                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       769355                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       769355                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       834244                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       834244                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       139893                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       139893                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       195965                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       195965                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5862596                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5862596                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      6631951                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      6631951                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31285                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31285                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        30958                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        30958                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        62243                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        62243                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  50416416500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50416416500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  33875543231                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33875543231                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17245260500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17245260500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  30759768392                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  30759768392                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1918237000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1918237000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4731380000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4731380000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3064500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3064500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 115051728123                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 115051728123                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132296988623                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 132296988623                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6062914000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6062914000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6062914000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6062914000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.026789                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026789                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019423                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019423                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.767572                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.767572                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.807046                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.807046                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064917                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064917                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.092636                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.092636                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027774                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027774                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031270                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.031270                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14614.940969                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14614.940969                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21457.831670                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21457.831670                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22415.218592                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22415.218592                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36871.428973                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36871.428973                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13712.172875                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13712.172875                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24144.005307                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24144.005307                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19624.706891                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19624.706891                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19948.426733                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19948.426733                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193796.196260                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193796.196260                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97407.162251                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97407.162251                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          6234341                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.962382                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          276007197                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          6234853                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            44.268437                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      12884658000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.962382                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999927                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999927                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          339                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        571449747                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       571449747                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    276007197                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      276007197                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    276007197                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       276007197                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    276007197                       # number of overall hits
system.cpu0.icache.overall_hits::total      276007197                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6600102                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      6600102                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6600102                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       6600102                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6600102                       # number of overall misses
system.cpu0.icache.overall_misses::total      6600102                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  71550800576                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  71550800576                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  71550800576                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  71550800576                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  71550800576                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  71550800576                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    282607299                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    282607299                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    282607299                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    282607299                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    282607299                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    282607299                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.023354                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.023354                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.023354                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.023354                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.023354                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.023354                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10840.862850                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10840.862850                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10840.862850                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10840.862850                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10840.862850                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10840.862850                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs     10420482                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1138                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           752268                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             11                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.852087                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets   103.454545                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      6234341                       # number of writebacks
system.cpu0.icache.writebacks::total          6234341                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       364953                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       364953                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       364953                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       364953                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       364953                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       364953                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6235149                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      6235149                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6235149                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      6235149                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6235149                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      6235149                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  64720811973                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  64720811973                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  64720811973                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  64720811973                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  64720811973                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  64720811973                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1885677498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1885677498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1885677498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1885677498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.022063                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.022063                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.022063                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.022063                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.022063                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.022063                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10379.994443                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10379.994443                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10379.994443                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10379.994443                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10379.994443                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10379.994443                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      8818791                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      8829534                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         9675                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1134314                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements         2939155                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16147.226336                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          18219506                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2955258                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.165115                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      2212473000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15244.220202                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    58.043386                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    62.165258                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data     0.000002                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   782.797489                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.930433                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003543                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003794                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.000000                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.047778                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.985548                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1151                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           81                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14871                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           14                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          189                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          576                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          372                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           48                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           14                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1385                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         6005                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4408                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2945                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.070251                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004944                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.907654                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       433411639                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      433411639                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       616680                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       198735                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        815415                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      4206029                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      4206029                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      8435953                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      8435953                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          888                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total          888                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            2                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data      1016467                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total      1016467                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5621992                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      5621992                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3255070                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      3255070                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       189931                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       189931                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       616680                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       198735                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      5621992                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      4271537                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       10708944                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       616680                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       198735                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      5621992                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      4271537                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      10708944                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        13303                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10046                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        23349                       # number of ReadReq misses
system.cpu0.l2cache.WritebackDirty_misses::writebacks            5                       # number of WritebackDirty misses
system.cpu0.l2cache.WritebackDirty_misses::total            5                       # number of WritebackDirty misses
system.cpu0.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
system.cpu0.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       270883                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       270883                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       195959                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       195959                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       300699                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       300699                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       612692                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       612692                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1101459                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1101459                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       642386                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       642386                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        13303                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker        10046                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       612692                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1402158                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2038199                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        13303                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker        10046                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       612692                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1402158                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2038199                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    571435000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    478645000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   1050080000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2108781500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2108781500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1542924500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1542924500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2975499                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2975499                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16979785000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  16979785000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  21306863000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  21306863000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  41322461986                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  41322461986                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    313374000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    313374000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    571435000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    478645000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  21306863000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  58302246986                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  80659189986                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    571435000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    478645000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  21306863000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  58302246986                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  80659189986                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       629983                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       208781                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       838764                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4206034                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      4206034                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      8435954                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      8435954                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       271771                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       271771                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       195961                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       195961                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1317166                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1317166                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6234684                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      6234684                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4356529                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      4356529                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       832317                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       832317                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       629983                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       208781                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      6234684                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5673695                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     12747143                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       629983                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       208781                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      6234684                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5673695                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     12747143                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021116                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.048117                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.027837                       # miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.996733                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.996733                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999990                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999990                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.228292                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.228292                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.098272                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.098272                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.252829                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.252829                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.771804                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.771804                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021116                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.048117                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.098272                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.247133                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.159895                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021116                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.048117                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.098272                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.247133                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.159895                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42955.348418                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47645.331475                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44973.232258                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  7784.842533                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  7784.842533                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  7873.710827                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  7873.710827                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 743874.750000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 743874.750000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56467.713561                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56467.713561                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34775.813949                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34775.813949                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37516.114523                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37516.114523                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   487.828191                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   487.828191                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42955.348418                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47645.331475                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34775.813949                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41580.368964                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39573.756040                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42955.348418                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47645.331475                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34775.813949                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41580.368964                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39573.756040                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          834                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs              18                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    46.333333                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           51227                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks      1850658                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1850658                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            4                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            8                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        18696                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total        18696                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            3                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5802                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5802                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           11                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total           11                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            8                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            3                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        24498                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        24513                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            4                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            8                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            3                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        24498                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        24513                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13299                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10038                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        23337                       # number of ReadReq MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            5                       # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::total            5                       # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       927770                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       927770                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       270883                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       270883                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       195959                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       195959                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       282003                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       282003                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       612689                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       612689                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1095657                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1095657                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       642375                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       642375                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13299                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10038                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       612689                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1377660                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      2013686                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        13299                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10038                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       612689                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1377660                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       927770                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2941456                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31285                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        52578                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        30958                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        30958                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        62243                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        83536                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    491572000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    418271000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    909843000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  52503366783                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  52503366783                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   5568283996                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   5568283996                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3258361996                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3258361996                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2621499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2621499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  12639099000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  12639099000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17630608000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17630608000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  34375466986                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  34375466986                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  23514926497                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  23514926497                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    491572000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    418271000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17630608000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  47014565986                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  65555016986                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    491572000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    418271000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17630608000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  47014565986                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  52503366783                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 118058383769                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1725979000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5812178000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7538157000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1725979000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5812178000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7538157000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021110                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.048079                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027823                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.996733                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.996733                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999990                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999990                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.214098                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.214098                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.098271                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.098271                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.251498                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.251498                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.771791                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.771791                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021110                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.048079                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.098271                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.242815                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.157972                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021110                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.048079                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.098271                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.242815                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.230754                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38987.144877                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56590.929630                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20556.048168                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20556.048168                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16627.774157                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16627.774157                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 655374.750000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 655374.750000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 44819.023202                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 44819.023202                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28775.786737                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28775.786737                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31374.295958                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31374.295958                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36606.229223                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36606.229223                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28775.786737                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34126.392569                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32554.736432                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28775.786737                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34126.392569                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40136.035953                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185781.620585                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143370.934611                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93378.821715                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90238.424152                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests     26220064                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     13479100                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2657                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops      2182451                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2181920                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          531                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        979416                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     11666319                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        30958                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        30958                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      6060800                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      8438347                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2860883                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1184490                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       488552                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       348527                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       533031                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           69                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          124                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1347603                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1325056                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6235149                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5307790                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       891051                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       832317                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18746760                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20650560                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       436622                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1328978                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         41162920                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    798358288                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    780155262                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1670248                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5039864                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1585223662                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    7567060                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic            126041936                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples     21529267                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.118569                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.323357                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          18977100     88.15%     88.15% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           2551636     11.85%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               531      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      21529267                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   26091722433                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    187623310                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   9380939070                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   9216328089                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    228203766                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    699632706                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              194671556                       # Number of BP lookups
system.cpu1.branchPred.condPredicted        153305610                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          6254288                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups           157865267                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               88709282                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            56.193033                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               16475486                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            172497                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        3896881                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           2381021                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses         1515860                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted       389837                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   533309                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               533309                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10503                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        81680                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       248509                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       284800                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2470.932233                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 13518.648671                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-32767       279405     98.11%     98.11% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-65535         3083      1.08%     99.19% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-98303          908      0.32%     99.51% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-131071          713      0.25%     99.76% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-163839          284      0.10%     99.86% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::163840-196607          163      0.06%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-229375          124      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::229376-262143           32      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-294911           13      0.00%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::294912-327679           40      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-360447           32      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       284800                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       268382                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 19517.668845                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17136.373439                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 13227.910444                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767       250971     93.51%     93.51% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535        15361      5.72%     99.24% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303          757      0.28%     99.52% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071          835      0.31%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839           87      0.03%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607          116      0.04%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375          116      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143           51      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911           29      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679           31      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447            7      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215           15      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       268382                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 466126532996                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.617043                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.546089                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 464998520496     99.76%     99.76% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3    569195000      0.12%     99.88% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5    249472000      0.05%     99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7    122508000      0.03%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9     91886000      0.02%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11     55274500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13     15901500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15     23390500      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       385000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 466126532996                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        81681     88.61%     88.61% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        10503     11.39%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        92184                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       533309                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       533309                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        92184                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        92184                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       625493                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                   161844710                       # DTB read hits
system.cpu1.dtb.read_misses                    366883                       # DTB read misses
system.cpu1.dtb.write_hits                   74184112                       # DTB write hits
system.cpu1.dtb.write_misses                   166426                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              44490                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   34599                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      386                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  6272                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    37354                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses               162211593                       # DTB read accesses
system.cpu1.dtb.write_accesses               74350538                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        236028822                       # DTB hits
system.cpu1.dtb.misses                         533309                       # DTB misses
system.cpu1.dtb.accesses                    236562131                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    80718                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                80718                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          768                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        57037                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore        10137                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        70581                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean   996.309205                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  6981.449622                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767        70036     99.23%     99.23% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535          380      0.54%     99.77% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303           60      0.09%     99.85% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071           83      0.12%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        70581                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        67942                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 24162.219246                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 22142.693859                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 15015.121608                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        66991     98.60%     98.60% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          778      1.15%     99.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          100      0.15%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           45      0.07%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           20      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        67942                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 397380257260                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.877039                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.328570                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    48883602860     12.30%     12.30% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   348476867900     87.69%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       18158500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        1572000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4          56000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 397380257260                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        57037     98.67%     98.67% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          768      1.33%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        57805                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        80718                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        80718                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        57805                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        57805                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       138523                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   264777096                       # ITB inst hits
system.cpu1.itb.inst_misses                     80718                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              44490                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   24684                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   195163                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               264857814                       # ITB inst accesses
system.cpu1.itb.hits                        264777096                       # DTB hits
system.cpu1.itb.misses                          80718                       # DTB misses
system.cpu1.itb.accesses                    264857814                       # DTB accesses
system.cpu1.numPwrStateTransitions               9670                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         4835                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    9724953244.725336                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   147881742434.863098                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3183     65.83%     65.83% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         1626     33.63%     99.46% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.04%     99.50% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            5      0.10%     99.61% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            2      0.04%     99.65% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11            1      0.02%     99.67% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11            1      0.02%     99.69% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12            1      0.02%     99.71% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           14      0.29%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 7390881470984                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           4835                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   364202361753                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 47020148938247                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       728406370                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          83192103                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     724269312                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  194671556                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches         107565789                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    610871186                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               13439122                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   1719504                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles              273339                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles      5608482                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       704978                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles       774415                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                264561727                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              1602178                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  26700                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         709863568                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.153991                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.257090                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               331851103     46.75%     46.75% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1               119648081     16.86%     63.60% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                75565351     10.65%     74.25% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3               182799033     25.75%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           709863568                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.267257                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.994320                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                98062054                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            297890044                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                275618841                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             33512378                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               4780251                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            17247911                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1977266                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             743961992                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts             21656856                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               4780251                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               130238128                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               40363481                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     204147620                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                276602035                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             53732053                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             728176206                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts              5626727                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents              9082967                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                240191                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                268836                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              22296515                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents           11543                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          630286495                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups           1024905330                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       827525539                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           801877                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            577128327                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                53158158                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          14384532                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      12638476                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 67737488                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads           162372694                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           77181222                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          8520193                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         7294637                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 707349171                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           14663402                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                711466322                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued          2509310                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       50084332                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     32217686                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        252969                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    709863568                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.002258                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.141899                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          346424684     48.80%     48.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1          123916139     17.46%     66.26% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2          138092978     19.45%     85.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           94358537     13.29%     99.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            7067534      1.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               3696      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      709863568                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu               53419887     27.72%     27.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 53191      0.03%     27.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                  19037      0.01%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc              15      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     27.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead             103986379     53.96%     81.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite             35231745     18.28%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               25      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            469996066     66.06%     66.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1210560      0.17%     66.23% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                70927      0.01%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         81598      0.01%     66.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.25% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead           164776620     23.16%     89.41% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           75330478     10.59%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             711466322                       # Type of FU issued
system.cpu1.iq.rate                          0.976744                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                  192710254                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.270863                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        2326678945                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        771690256                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    695698465                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1336829                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            536159                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       497637                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             903350253                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 826298                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         2394067                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     11654320                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        15948                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       130447                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      5130974                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      2399995                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      3738162                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               4780251                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                5901245                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1355404                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          722138785                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts            162372694                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            77181222                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          12419825                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 58724                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              1239916                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        130447                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       1767111                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2862185                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4629296                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            704121990                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts            161840669                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          6820718                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       126212                       # number of nop insts executed
system.cpu1.iew.exec_refs                   236024480                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               169760384                       # Number of branches executed
system.cpu1.iew.exec_stores                  74183811                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.966661                       # Inst execution rate
system.cpu1.iew.wb_sent                     696881354                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    696196102                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                357262878                       # num instructions producing a value
system.cpu1.iew.wb_consumers                517340824                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.955780                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.690575                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       43732145                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       14410433                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4314978                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    701540457                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.957790                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.589997                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    413092247     58.88%     58.88% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1    113176092     16.13%     75.02% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     83530992     11.91%     86.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     51841229      7.39%     94.31% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     11508500      1.64%     95.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      7726725      1.10%     97.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5343630      0.76%     97.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3131269      0.45%     98.26% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     12189773      1.74%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    701540457                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           597176554                       # Number of instructions committed
system.cpu1.commit.committedOps             671928235                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     222768619                       # Number of memory references committed
system.cpu1.commit.loads                    150718371                       # Number of loads committed
system.cpu1.commit.membars                   39196572                       # Number of memory barriers committed
system.cpu1.commit.branches                 164739467                       # Number of branches committed
system.cpu1.commit.fp_insts                    488627                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                631392614                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            12167965                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       448043617     66.68%     66.68% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult         985154      0.15%     66.83% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           56630      0.01%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     66.84% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        74173      0.01%     66.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     66.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.85% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead      150718371     22.43%     89.28% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      72050248     10.72%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        671928235                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             12189773                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1401264531                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1439606443                       # The number of ROB writes
system.cpu1.timesIdled                         902579                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       18542802                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 94040296263                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  597176554                       # Number of Instructions Simulated
system.cpu1.committedOps                    671928235                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.219750                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.219750                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.819840                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.819840                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               799341399                       # number of integer regfile reads
system.cpu1.int_regfile_writes              475575163                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   787030                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  454812                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                112918659                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               113685571                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1436513215                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              14489141                       # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements          5047432                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          457.905792                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          212666270                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5047943                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            42.129293                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8477400492000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   457.905792                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.894347                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.894347                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          323                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        457080025                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       457080025                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data    145190780                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total      145190780                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     62993534                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      62993534                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       167629                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       167629                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       116242                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       116242                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1721505                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1721505                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1728884                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1728884                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    208300556                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       208300556                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    208468185                       # number of overall hits
system.cpu1.dcache.overall_hits::total      208468185                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      5993321                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      5993321                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      6604202                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      6604202                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       607895                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       607895                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       421696                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       421696                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       237246                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       237246                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       187668                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       187668                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data     13019219                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total      13019219                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data     13627114                       # number of overall misses
system.cpu1.dcache.overall_misses::total     13627114                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  89379669000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  89379669000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119695443135                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 119695443135                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  10488678921                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  10488678921                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3322992000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   3322992000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4669078500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4669078500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3521000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3521000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 219563791056                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 219563791056                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 219563791056                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 219563791056                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data    151184101                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total    151184101                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     69597736                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     69597736                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       775524                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       775524                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       537938                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       537938                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1958751                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1958751                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1916552                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1916552                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    221319775                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    221319775                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    222095299                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    222095299                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039643                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.039643                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.094891                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.094891                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.783851                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.783851                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.783912                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.783912                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.121121                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.121121                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097920                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097920                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.058825                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.058825                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.061357                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.061357                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14913.212391                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14913.212391                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18124.134170                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18124.134170                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24872.607094                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24872.607094                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14006.524873                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14006.524873                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24879.460004                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24879.460004                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16864.590038                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16864.590038                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16112.273740                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16112.273740                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs      2706631                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets     18960106                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs           351175                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets         660083                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     7.707357                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    28.723821                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      5047462                       # number of writebacks
system.cpu1.dcache.writebacks::total          5047462                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3052290                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total      3052290                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5325465                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      5325465                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3276                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total         3276                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       122610                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total       122610                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      8381031                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      8381031                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      8381031                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      8381031                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2941031                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2941031                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1278737                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1278737                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       607807                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       607807                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       418420                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       418420                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       114636                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       114636                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       187667                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       187667                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4638188                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4638188                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5245995                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5245995                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         7218                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         7218                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7480                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7480                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        14698                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        14698                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  39704145500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  39704145500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  24666220214                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  24666220214                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14600377000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14600377000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   9957787421                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total   9957787421                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1521960000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1521960000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4481476500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4481476500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3456000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3456000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  74328153135                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  74328153135                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  88928530135                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  88928530135                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    880126000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    880126000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    880126000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    880126000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.019453                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.019453                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018373                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018373                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.783737                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.783737                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.777822                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.777822                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058525                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.058525                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097919                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097919                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.020957                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.020957                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.023620                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.023620                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.077184                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13500.077184                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19289.517871                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19289.517871                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24021.403176                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24021.403176                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23798.545531                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23798.545531                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.457657                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.457657                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23879.938934                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23879.938934                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16025.256659                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16025.256659                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16951.699370                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16951.699370                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 121934.885010                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 121934.885010                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59880.664036                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59880.664036                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements          5706197                       # number of replacements
system.cpu1.icache.tags.tagsinuse          501.707809                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          258521982                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5706709                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            45.301413                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8517122288000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.707809                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979898                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.979898                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          307                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1           84                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          121                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        534817167                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       534817167                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst    258521982                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      258521982                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    258521982                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       258521982                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    258521982                       # number of overall hits
system.cpu1.icache.overall_hits::total      258521982                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      6033199                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      6033199                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      6033199                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       6033199                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      6033199                       # number of overall misses
system.cpu1.icache.overall_misses::total      6033199                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  64071626251                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  64071626251                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  64071626251                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  64071626251                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  64071626251                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  64071626251                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    264555181                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    264555181                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    264555181                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    264555181                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    264555181                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    264555181                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.022805                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.022805                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.022805                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.022805                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.022805                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.022805                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10619.843014                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10619.843014                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10619.843014                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10619.843014                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10619.843014                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10619.843014                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs      9429094                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          244                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs           708482                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              4                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.308869                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets           61                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      5706197                       # number of writebacks
system.cpu1.icache.writebacks::total          5706197                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       326394                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total       326394                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst       326394                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total       326394                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst       326394                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total       326394                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5706805                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5706805                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5706805                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5706805                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5706805                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5706805                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  58058775330                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  58058775330                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  58058775330                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  58058775330                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  58058775330                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  58058775330                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6679498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6679498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6679498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      6679498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.021571                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.021571                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.021571                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.021571                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.021571                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.021571                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10173.604202                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10173.604202                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10173.604202                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10173.604202                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10173.604202                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10173.604202                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        99694                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total        99694                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst        99694                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total        99694                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued      6901811                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      6907587                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit         5314                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       821749                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements         2026075                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13356.542127                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          16274118                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2041771                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            7.970589                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9992426830500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12440.422172                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    43.172118                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    33.879322                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data     0.000015                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   839.068499                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.759303                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002635                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.002068                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.000000                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.051213                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.815219                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1386                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           96                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14214                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           75                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          230                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          627                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          454                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           79                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            7                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          211                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          797                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4633                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4798                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3775                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.084595                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005859                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.867554                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       369100514                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      369100514                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       546957                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       179929                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        726886                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3170558                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3170558                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      7581614                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      7581614                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          544                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total          544                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            2                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       815108                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       815108                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5173102                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      5173102                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2742764                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2742764                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       184198                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       184198                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       546957                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       179929                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      5173102                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3557872                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        9457860                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       546957                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       179929                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      5173102                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3557872                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       9457860                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11826                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8080                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        19906                       # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks            4                       # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total            4                       # number of WritebackDirty misses
system.cpu1.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
system.cpu1.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       224180                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       224180                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       187653                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       187653                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           12                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total           12                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       246832                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       246832                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       533612                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       533612                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       917456                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       917456                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       232409                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       232409                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11826                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8080                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       533612                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1164288                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1717806                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11826                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8080                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       533612                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1164288                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1717806                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    438373000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    291991000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    730364000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2034074000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   2034074000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1455556000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1455556000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3356498                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3356498                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10810838997                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10810838997                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  18150969000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  18150969000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  32024307483                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  32024307483                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    362347000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    362347000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    438373000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    291991000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  18150969000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  42835146480                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  61716479480                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    438373000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    291991000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  18150969000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  42835146480                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  61716479480                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       558783                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       188009                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       746792                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3170562                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3170562                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      7581615                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      7581615                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       224724                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       224724                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       187655                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       187655                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           12                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           12                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1061940                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1061940                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5706714                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      5706714                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3660220                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3660220                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       416607                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       416607                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       558783                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       188009                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5706714                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4722160                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     11175666                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       558783                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       188009                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5706714                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4722160                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     11175666                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021164                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.042977                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.026655                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.997579                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.997579                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999989                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999989                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.232435                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.232435                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.093506                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.093506                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.250656                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.250656                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.557861                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.557861                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021164                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.042977                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.093506                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.246558                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.153709                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021164                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.042977                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.093506                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.246558                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.153709                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37068.577710                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36137.500000                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36690.646036                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  9073.396378                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  9073.396378                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  7756.635918                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  7756.635918                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 279708.166667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 279708.166667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43798.368919                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43798.368919                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34015.293884                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34015.293884                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34905.551310                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34905.551310                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1559.091946                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1559.091946                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37068.577710                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36137.500000                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34015.293884                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36790.851130                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 35927.502570                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37068.577710                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36137.500000                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34015.293884                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36790.851130                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 35927.502570                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs          264                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               5                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    52.800000                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches           40814                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks      1038265                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1038265                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            8                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total           11                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         9551                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         9551                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         4369                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         4369                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            8                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data        13920                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        13932                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            3                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            8                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data        13920                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        13932                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11823                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8072                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        19895                       # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            4                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::total            4                       # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       718321                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       718321                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       224180                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       224180                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       187653                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       187653                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           12                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           12                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       237281                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       237281                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       533611                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       533611                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       913087                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       913087                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       232409                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       232409                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11823                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8072                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       533611                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1150368                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1703874                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11823                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8072                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       533611                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1150368                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       718321                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2422195                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         7218                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         7285                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         7480                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         7480                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        14698                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        14765                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    367372500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    243371500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    610744000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  32165766903                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  32165766903                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4735558998                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4735558998                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3071141498                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3071141498                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2966498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2966498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8013535997                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8013535997                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  14949290000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  14949290000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  26287930983                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  26287930983                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6248930499                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6248930499                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    367372500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    243371500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  14949290000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34301466980                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  49861500980                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    367372500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    243371500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  14949290000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34301466980                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  32165766903                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  82027267883                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6176000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    822175500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    828351500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      6176000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    822175500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    828351500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021158                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.042934                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026641                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.997579                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.997579                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999989                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999989                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.223441                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.223441                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.093506                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.093506                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.249462                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249462                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.557861                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.557861                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021158                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.042934                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.093506                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.243611                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.152463                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021158                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.042934                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.093506                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.243611                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.216738                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30698.366424                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44779.098624                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21123.913810                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21123.913810                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16366.066612                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16366.066612                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247208.166667                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247208.166667                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33772.345856                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33772.345856                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28015.333267                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28015.333267                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28790.171126                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28790.171126                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26887.644192                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26887.644192                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28015.333267                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29817.820889                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29263.608095                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28015.333267                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29817.820889                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33864.848983                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 113906.275977                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113706.451613                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55937.916723                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56102.370471                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests     22350657                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11505244                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1543                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops      1883368                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1883027                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          341                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq        842183                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     10302833                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         7480                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         7480                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4215889                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      7583095                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      2514473                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       909607                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            6                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       430035                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       341692                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       476439                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           71                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          124                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1090279                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1068076                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5706805                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4656106                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       474602                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       416607                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     17119850                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16343111                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       395526                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1186164                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         35044651                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    730427376                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    631688689                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1504072                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4470264                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1368090401                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    6163170                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic             73999248                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples     18018661                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.123449                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.329009                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          15794619     87.66%     87.66% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           2223701     12.34%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               341      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      18018661                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   22188055468                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    182014003                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   8566090793                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7517136176                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    207825380                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    628033176                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40328                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40328                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136631                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136631                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47646                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122580                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353918                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47666                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155687                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339048                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7339048                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496821                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36938002                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               332000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               13500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            24205503                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36443500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569408550                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92680000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147954000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115626                       # number of replacements
system.iocache.tags.tagsinuse               11.305309                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115642                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9115830406000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.413187                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.892123                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.463324                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.243258                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706582                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1041018                       # Number of tag accesses
system.iocache.tags.data_accesses             1041018                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8901                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8938                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115629                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115669                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115629                       # number of overall misses
system.iocache.overall_misses::total           115669                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5198500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1667264523                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1672463023                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12925157527                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12925157527                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5567500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  14592422050                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  14597989550                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5567500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  14592422050                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  14597989550                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8901                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8938                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115629                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115669                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115629                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115669                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet       140500                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 187312.046175                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 187118.261692                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121103.717178                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 121103.717178                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 126200.365393                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126204.856530                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 126200.365393                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126204.856530                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         33241                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3524                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.432747                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106695                       # number of writebacks
system.iocache.writebacks::total               106695                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8901                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8938                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115629                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115669                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115629                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115669                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1222214523                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1225563023                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7580015931                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7580015931                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3567500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   8802230454                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8805797954                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3567500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   8802230454                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8805797954                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        90500                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137312.046175                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 137118.261692                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71021.811811                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71021.811811                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76124.765016                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76129.282297                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76124.765016                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76129.282297                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1557710                       # number of replacements
system.l2c.tags.tagsinuse                63573.891854                       # Cycle average of tags in use
system.l2c.tags.total_refs                    6243665                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1617388                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.860338                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               3022937500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   21119.731437                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   317.083055                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   501.157048                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4189.705266                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    12756.928607                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18825.078792                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    29.382680                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker    33.853586                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2676.679680                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1884.367858                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1239.923843                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.322262                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.004838                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.007647                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.063930                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.194655                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.287248                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000448                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000517                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.040843                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.028753                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.018920                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.970061                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        11464                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          277                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        47937                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2         1377                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          337                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9749                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          272                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          349                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3074                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5518                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        38948                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.174927                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.004227                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.731461                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 79574133                       # Number of tag accesses
system.l2c.tags.data_accesses                79574133                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks      2888931                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2888931                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total               1                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data          180891                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          129539                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              310430                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         43976                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         36797                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             80773                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            55787                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            50048                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               105835                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6797                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4576                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       551177                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       671308                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       325157                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6401                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4256                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       484948                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       535287                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       285618                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2875525                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       132882                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       123273                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           256155                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6797                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4576                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              551177                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              727095                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       325157                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6401                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4256                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              484948                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              585335                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       285618                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2981360                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6797                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4576                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             551177                       # number of overall hits
system.l2c.overall_hits::cpu0.data             727095                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       325157                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6401                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4256                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             484948                       # number of overall hits
system.l2c.overall_hits::cpu1.data             585335                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       285618                       # number of overall hits
system.l2c.overall_hits::total                2981360                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         62870                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         65353                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            128223                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        13472                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        11956                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           25428                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          91907                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          48160                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140067                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3207                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3170                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        61507                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       173115                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       339604                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1937                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1306                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        48662                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       111561                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       193805                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         937874                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       497642                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data        96113                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         593755                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         3207                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         3170                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             61507                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            265022                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       339604                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1937                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1306                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             48662                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            159721                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       193805                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1077941                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         3207                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         3170                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            61507                       # number of overall misses
system.l2c.overall_misses::cpu0.data           265022                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       339604                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1937                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1306                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            48662                       # number of overall misses
system.l2c.overall_misses::cpu1.data           159721                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       193805                       # number of overall misses
system.l2c.overall_misses::total              1077941                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    420802000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    429972500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    850774500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     88078000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     80352500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    168430500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8572942990                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4240159498                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  12813102488                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    292674000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    283861500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   5444535999                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  16594648743                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  46635334107                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    183709500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    124471000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   4269928000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  11202968996                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  26909035721                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 111941167566                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data     55164500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data     62218500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total    117383000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    292674000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    283861500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   5444535999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  25167591733                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  46635334107                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    183709500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    124471000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   4269928000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  15443128494                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  26909035721                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    124754270054                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    292674000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    283861500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   5444535999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  25167591733                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  46635334107                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    183709500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    124471000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   4269928000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  15443128494                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  26909035721                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   124754270054                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2888931                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2888931                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       243761                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       194892                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          438653                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        57448                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        48753                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        106201                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       147694                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        98208                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           245902                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        10004                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7746                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       612684                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       844423                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       664761                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8338                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5562                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       533610                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       646848                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       479423                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3813399                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       630524                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       219386                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       849910                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        10004                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7746                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          612684                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          992117                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       664761                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         8338                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5562                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          533610                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          745056                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       479423                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4059301                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        10004                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7746                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         612684                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         992117                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       664761                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         8338                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5562                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         533610                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         745056                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       479423                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4059301                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.257917                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.335329                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.292311                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.234508                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.245236                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.239433                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.622280                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.490388                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.569605                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.320572                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.409243                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.100389                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.205010                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.232310                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.234808                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.091194                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.172469                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.245942                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.789251                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.438100                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.698609                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.320572                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.409243                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.100389                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.267128                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.232310                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.234808                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.091194                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.214374                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.265548                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.320572                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.409243                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.100389                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.267128                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.232310                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.234808                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.091194                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.214374                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.265548                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6693.208207                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6579.231252                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6635.116165                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6537.856295                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  6720.684175                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  6623.820198                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93278.455286                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 88043.178945                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 91478.381689                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 91260.991581                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89546.214511                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 88518.965305                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 95859.103735                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 137322.687916                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 94842.281879                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 95307.044410                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 87746.660639                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 100420.119899                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138845.931328                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 119356.296865                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   110.851777                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   647.347393                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   197.696019                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91260.991581                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89546.214511                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 88518.965305                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 94964.160458                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 137322.687916                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 94842.281879                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 95307.044410                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 87746.660639                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 96688.153054                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138845.931328                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 115733.857469                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91260.991581                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89546.214511                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 88518.965305                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 94964.160458                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 137322.687916                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 94842.281879                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 95307.044410                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 87746.660639                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 96688.153054                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138845.931328                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 115733.857469                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              7857                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       97                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs            81                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1229961                       # number of writebacks
system.l2c.writebacks::total                  1229961                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           90                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           20                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           89                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           22                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          221                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             90                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             20                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             89                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             22                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                221                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            90                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            20                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            89                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            22                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               221                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        60565                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        60565                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        62870                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        65353                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total       128223                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        13472                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11956                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        25428                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        91907                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        48160                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140067                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3207                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3170                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        61417                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       173095                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       339604                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1937                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1306                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        48573                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       111539                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       193805                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       937653                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       497642                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data        96113                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       593755                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         3207                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         3170                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        61417                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       265002                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       339604                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1937                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1306                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        48573                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       159699                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       193805                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1077720                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         3207                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         3170                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        61417                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       265002                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       339604                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1937                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1306                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        48573                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       159699                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       193805                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1077720                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31285                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         7216                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        59861                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        30958                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         7480                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38438                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        62243                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        14696                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        98299                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1354983996                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1420163498                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   2775147494                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    332136996                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    293140999                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    625277995                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7653704832                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3758420781                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  11412125613                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    260603501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    252160502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   4822941587                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  14861591064                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  43239056127                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    164338502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    111409004                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3776950571                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  10085579883                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  24970706342                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 102545337083                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  12306862586                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2041559000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  14348421586                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    260603501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    252160502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   4822941587                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  22515295896                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  43239056127                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    164338502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    111409004                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   3776950571                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  13844000664                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  24970706342                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 113957462696                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    260603501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    252160502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   4822941587                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  22515295896                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  43239056127                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    164338502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    111409004                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   3776950571                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  13844000664                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  24970706342                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 113957462696                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1342704500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5248860501                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4969000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    692108006                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7288642007                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1342704500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5248860501                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4969000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    692108006                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   7288642007                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.257917                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.335329                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.292311                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.234508                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.245236                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.239433                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.622280                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.490388                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.569605                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.320572                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.409243                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.100243                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.204986                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.232310                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.234808                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.091027                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.172435                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.245884                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.789251                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.438100                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.698609                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.320572                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.409243                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.100243                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.267108                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.232310                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.234808                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.091027                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.214345                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.265494                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.320572                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.409243                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.100243                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.267108                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.232310                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.234808                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.091027                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.214345                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.265494                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21552.155177                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21730.655027                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21643.133400                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24653.874406                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24518.317079                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24590.136660                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83276.625632                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 78040.298609                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 81476.190773                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 78527.795024                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 85858.003201                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 77758.231343                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90422.003810                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109363.844709                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24730.353519                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 21241.236877                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24165.559172                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78527.795024                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84962.739511                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77758.231343                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86688.086112                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 105739.396778                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78527.795024                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84962.739511                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77758.231343                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86688.086112                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 105739.396778                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167775.627329                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 95912.972007                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121759.442826                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84328.526919                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 47094.992243                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 74147.671970                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       4190264                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2528993                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3019                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               59861                       # Transaction distribution
system.membus.trans_dist::ReadResp            1006452                       # Transaction distribution
system.membus.trans_dist::WriteReq              38438                       # Transaction distribution
system.membus.trans_dist::WriteResp             38438                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1336656                       # Transaction distribution
system.membus.trans_dist::CleanEvict           266935                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           438975                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         302731                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              22                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            150471                       # Transaction distribution
system.membus.trans_dist::ReadExResp           135365                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        946591                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        696687                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122580                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26078                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5027920                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5176654                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238145                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       238145                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5414799                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155687                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52156                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    147706944                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    147915343                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7266880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7266880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               155182223                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           597489                       # Total snoops (count)
system.membus.snoopTraffic                     179456                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2633759                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.013061                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.113535                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2599360     98.69%     98.69% # Request fanout histogram
system.membus.snoop_fanout::1                   34399      1.31%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2633759                       # Request fanout histogram
system.membus.reqLayer0.occupancy            98019495                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               52000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21931994                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9377704107                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5794716587                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45616715                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     12205642                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      6628070                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1941255                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         157740                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       142803                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        14937                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              59863                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4654836                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38438                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38438                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      4118892                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean            2                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2762121                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          740907                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        383504                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1124411                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          124                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          124                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           298356                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          298356                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4595571                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       881263                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       849910                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10458732                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7383011                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17841743                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    265418110                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    179948433                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              445366543                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3005080                       # Total snoops (count)
system.toL2Bus.snoopTraffic                 132103248                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples          8556754                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.351410                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.481053                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5564766     65.03%     65.03% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                2977051     34.79%     99.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  14937      0.17%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            8556754                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         9506782087                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2628899                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4728944566                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3692981173                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   14084                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    4835                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------