path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.309827                       # Number of seconds simulated
sim_ticks                                47309826639000                       # Number of ticks simulated
final_tick                               47309826639000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 115168                       # Simulator instruction rate (inst/s)
host_op_rate                                   135435                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5759542779                       # Simulator tick rate (ticks/s)
host_mem_usage                                 728780                       # Number of bytes of host memory used
host_seconds                                  8214.16                       # Real time elapsed on the host
sim_insts                                   946011818                       # Number of instructions simulated
sim_ops                                    1112485532                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       184448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       167936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          5084832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         44767048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     19339456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       176320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       161792                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2535456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         18891728                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     20722048                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        420544                       # Number of bytes read from this memory
system.physmem.bytes_read::total            112451608                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      5084832                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2535456                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7620288                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     93755328                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          93775912                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2882                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2624                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             95403                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            699498                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       302179                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2755                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2528                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             39660                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            295196                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       323782                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6571                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1773078                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1464927                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1467501                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3899                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          3550                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              107479                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              946253                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       408783                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          3727                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          3420                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               53593                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              399319                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       438007                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8889                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2376919                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         107479                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          53593                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             161072                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1981731                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1982166                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1981731                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3899                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         3550                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             107479                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             946688                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       408783                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         3727                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         3420                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              53593                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             399319                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       438007                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8889                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4359084                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1773078                       # Number of read requests accepted
system.physmem.writeReqs                      1467501                       # Number of write requests accepted
system.physmem.readBursts                     1773078                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1467501                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                113443520                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     33472                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  93774528                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 112451608                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               93775912                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      523                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         224875                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              113386                       # Per bank write bursts
system.physmem.perBankRdBursts::1              120644                       # Per bank write bursts
system.physmem.perBankRdBursts::2              108661                       # Per bank write bursts
system.physmem.perBankRdBursts::3              115173                       # Per bank write bursts
system.physmem.perBankRdBursts::4              103078                       # Per bank write bursts
system.physmem.perBankRdBursts::5              114921                       # Per bank write bursts
system.physmem.perBankRdBursts::6              108340                       # Per bank write bursts
system.physmem.perBankRdBursts::7              105879                       # Per bank write bursts
system.physmem.perBankRdBursts::8               98747                       # Per bank write bursts
system.physmem.perBankRdBursts::9              127278                       # Per bank write bursts
system.physmem.perBankRdBursts::10              99197                       # Per bank write bursts
system.physmem.perBankRdBursts::11             111650                       # Per bank write bursts
system.physmem.perBankRdBursts::12             107228                       # Per bank write bursts
system.physmem.perBankRdBursts::13             113583                       # Per bank write bursts
system.physmem.perBankRdBursts::14             112177                       # Per bank write bursts
system.physmem.perBankRdBursts::15             112613                       # Per bank write bursts
system.physmem.perBankWrBursts::0               94420                       # Per bank write bursts
system.physmem.perBankWrBursts::1               97266                       # Per bank write bursts
system.physmem.perBankWrBursts::2               90974                       # Per bank write bursts
system.physmem.perBankWrBursts::3               94616                       # Per bank write bursts
system.physmem.perBankWrBursts::4               87287                       # Per bank write bursts
system.physmem.perBankWrBursts::5               94599                       # Per bank write bursts
system.physmem.perBankWrBursts::6               89304                       # Per bank write bursts
system.physmem.perBankWrBursts::7               90590                       # Per bank write bursts
system.physmem.perBankWrBursts::8               84448                       # Per bank write bursts
system.physmem.perBankWrBursts::9               90113                       # Per bank write bursts
system.physmem.perBankWrBursts::10              85465                       # Per bank write bursts
system.physmem.perBankWrBursts::11              93225                       # Per bank write bursts
system.physmem.perBankWrBursts::12              88655                       # Per bank write bursts
system.physmem.perBankWrBursts::13              95246                       # Per bank write bursts
system.physmem.perBankWrBursts::14              93025                       # Per bank write bursts
system.physmem.perBankWrBursts::15              95994                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          83                       # Number of times write queue was full causing retry
system.physmem.totGap                    47309825190500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1751720                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1464927                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    608524                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    449703                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    194607                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    195607                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    116312                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     71048                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     40112                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     36551                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     32712                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     10303                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     5634                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     3467                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     2280                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1844                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1284                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      910                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      790                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      582                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      168                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       96                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    20153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    23447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    36691                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    44303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    53186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    62828                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    72210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    82749                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    88726                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    95528                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    97547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   101638                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   103246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   108748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   123417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   115282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   109625                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    98032                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     7953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     4632                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2879                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1860                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      995                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      720                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      440                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      311                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      242                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      316                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      296                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      281                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1119709                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      185.063798                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     114.156365                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     241.940793                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         674939     60.28%     60.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       219039     19.56%     79.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        70659      6.31%     86.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        37987      3.39%     89.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        28223      2.52%     92.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        14545      1.30%     93.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        15798      1.41%     94.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9595      0.86%     95.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        48924      4.37%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1119709                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         84177                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.057367                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      250.150754                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          84175    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::69632-73727            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           84177                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         84177                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.406501                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.998569                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.063432                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           78913     93.75%     93.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            2654      3.15%     96.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             594      0.71%     97.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             256      0.30%     97.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             356      0.42%     98.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             499      0.59%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             111      0.13%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              36      0.04%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              47      0.06%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              28      0.03%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              36      0.04%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              26      0.03%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             418      0.50%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              37      0.04%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              46      0.05%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              46      0.05%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              12      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            25      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             4      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-235             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           84177                       # Writes before turning the bus around for reads
system.physmem.totQLat                    95142418476                       # Total ticks spent queuing
system.physmem.totMemAccLat              128377824726                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   8862775000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       53675.30                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  72425.30                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.40                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.98                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.38                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.98                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.45                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1427545                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    690525                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.54                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  47.13                       # Row buffer hit rate for writes
system.physmem.avgGap                     14599188.97                       # Average gap between requests
system.physmem.pageHitRate                      65.42                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 4299372000                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2345887500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                6942631800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4789082880                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3090047684880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1174100419575                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27355981545000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31638506623635                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.751312                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45508743621503                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1579778980000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    221302763997                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 4165628040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2272912125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                6883242600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4705588080                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3090047684880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1168667714520                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27360747075750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31637489845995                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.729820                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45516677078545                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1579778980000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    213370138955                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           572                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          528                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             39                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           11                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              147637418                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         98315773                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          7247820                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups           103619610                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               67413734                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            65.058857                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               20080737                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            195189                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   596316                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               596316                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13005                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        90766                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       267964                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       328352                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  1967.306427                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 12140.663837                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       326191     99.34%     99.34% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         1511      0.46%     99.80% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          485      0.15%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143           70      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679           71      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           17      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       328352                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       293288                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 18414.921511                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 15494.626324                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16461.439983                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       290000     98.88%     98.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         2364      0.81%     99.68% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          368      0.13%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          346      0.12%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          119      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           72      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       293288                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 554812439744                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.594659                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.537153                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 553701545244     99.80%     99.80% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3    589103000      0.11%     99.91% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5    238633000      0.04%     99.95% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7    116174000      0.02%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9     85227000      0.02%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11     46829500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13     15433000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15     19112000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       363500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19        19500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 554812439744                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        90767     87.47%     87.47% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        13005     12.53%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       103772                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       596316                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       596316                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       103772                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       103772                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       700088                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   107674804                       # DTB read hits
system.cpu0.dtb.read_misses                    416109                       # DTB read misses
system.cpu0.dtb.write_hits                   89240851                       # DTB write hits
system.cpu0.dtb.write_misses                   180207                       # DTB write misses
system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   37572                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      168                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  7516                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    38101                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               108090913                       # DTB read accesses
system.cpu0.dtb.write_accesses               89421058                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        196915655                       # DTB hits
system.cpu0.dtb.misses                         596316                       # DTB misses
system.cpu0.dtb.accesses                    197511971                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    85428                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                85428                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          771                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61190                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        10178                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        75250                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1283.993355                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  9203.446829                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        74460     98.95%     98.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          428      0.57%     99.52% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303          166      0.22%     99.74% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071          158      0.21%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839           10      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607            5      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        75250                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        72139                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 23671.051720                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 20466.529400                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 20605.197168                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        70248     97.38%     97.38% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071         1514      2.10%     99.48% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          196      0.27%     99.75% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143          111      0.15%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           47      0.07%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        72139                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 421639244068                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.834946                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.371382                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    69614918048     16.51%     16.51% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   352004823020     83.48%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       17379000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        2056500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4          67500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 421639244068                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        61190     98.76%     98.76% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          771      1.24%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        61961                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        85428                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        85428                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        61961                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        61961                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       147389                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   231535487                       # ITB inst hits
system.cpu0.itb.inst_misses                     85428                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   26943                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   216195                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               231620915                       # ITB inst accesses
system.cpu0.itb.hits                        231535487                       # DTB hits
system.cpu0.itb.misses                          85428                       # DTB misses
system.cpu0.itb.accesses                    231620915                       # DTB accesses
system.cpu0.numCycles                       805724204                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          95731684                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     652075833                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  147637418                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          87494471                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    667504198                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               15546378                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   1866411                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles              305738                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      6228904                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       744813                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles       860245                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                231319013                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              1833472                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  28917                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         781015182                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.979576                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.220669                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               414945915     53.13%     53.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1               142136658     18.20%     71.33% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                48870776      6.26%     77.59% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3               175061833     22.41%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           781015182                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.183236                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.809304                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               113248081                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            377378437                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                245811555                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             39067395                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5509714                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            21219272                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              2308032                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             677494422                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts             25172258                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5509714                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               150635102                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               57564950                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     243777898                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                246916319                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             76611199                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             659282826                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              6463914                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents             10193503                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                302591                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                345572                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              40114273                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents           11761                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          627680154                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups           1013922393                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       779757811                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           794183                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            565536193                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                62143943                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          16063927                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      14023847                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 79290060                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           107984972                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           92881396                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          9789553                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         8248701                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 636103677                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           16216212                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                639991449                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued          2906968                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       58559234                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     38038909                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        288402                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    781015182                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.819435                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.071222                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          434056489     55.58%     55.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1          142602713     18.26%     73.83% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2          124298977     15.92%     89.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           71442121      9.15%     98.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            8609991      1.10%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5               4891      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      781015182                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               67040735     45.54%     45.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 53703      0.04%     45.58% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                  26002      0.02%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc              14      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead              38206404     25.96%     71.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite             41875543     28.45%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            436779538     68.25%     68.25% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1517289      0.24%     68.48% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                81855      0.01%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  5      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt             23      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         47604      0.01%     68.51% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.51% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.51% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.51% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           110932479     17.33%     85.84% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           90632632     14.16%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             639991449                       # Type of FU issued
system.cpu0.iq.rate                          0.794306                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                  147202401                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.230007                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        2209837146                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        710527601                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    621905864                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1270303                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            504170                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       467307                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             786402566                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 791283                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         2962367                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     13371443                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        16751                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       153989                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      6295959                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2934112                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      4671160                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5509714                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                7058035                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              5778589                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          652441938                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            107984972                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            92881396                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          13772451                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 68630                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              5639093                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        153989                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2201982                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      3098287                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             5300269                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            631633854                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            107665614                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          7773689                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       122049                       # number of nop insts executed
system.cpu0.iew.exec_refs                   196907522                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               119104624                       # Number of branches executed
system.cpu0.iew.exec_stores                  89241908                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.783933                       # Inst execution rate
system.cpu0.iew.wb_sent                     623170550                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    622373171                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                301982038                       # num instructions producing a value
system.cpu0.iew.wb_consumers                495557723                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.772439                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.609378                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       51133197                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       15927810                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4984345                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    771348242                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.769770                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.572751                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    513096769     66.52%     66.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1    132148168     17.13%     83.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     58179832      7.54%     91.19% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     19360594      2.51%     93.70% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     14004722      1.82%     95.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      9477117      1.23%     96.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      6473381      0.84%     97.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3935015      0.51%     98.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     14672644      1.90%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    771348242                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           504955538                       # Number of instructions committed
system.cpu0.commit.committedOps             593760630                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     181198957                       # Number of memory references committed
system.cpu0.commit.loads                     94613526                       # Number of loads committed
system.cpu0.commit.membars                    4060839                       # Number of memory barriers committed
system.cpu0.commit.branches                 113014510                       # Number of branches committed
system.cpu0.commit.fp_insts                    458000                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                545152087                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            14971844                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       411193864     69.25%     69.25% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1260833      0.21%     69.46% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           65173      0.01%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        41761      0.01%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       94613526     15.93%     85.42% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      86585431     14.58%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        593760630                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             14672644                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1397369391                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1299419087                       # The number of ROB writes
system.cpu0.timesIdled                        1071653                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       24709022                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 93813929115                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  504955538                       # Number of Instructions Simulated
system.cpu0.committedOps                    593760630                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.595634                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.595634                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.626710                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.626710                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               746722296                       # number of integer regfile reads
system.cpu0.int_regfile_writes              443322911                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   778801                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  335108                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                136612374                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               137527114                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1389482326                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              16167899                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements          6374252                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          504.525126                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          168612051                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6374762                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            26.449937                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1887138000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   504.525126                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.985401                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.985401                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        375986188                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       375986188                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     87724319                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       87724319                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     75477797                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      75477797                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       231729                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       231729                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       266468                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       266468                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2022541                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      2022541                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2052696                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      2052696                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    163202116                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       163202116                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    163433845                       # number of overall hits
system.cpu0.dcache.overall_hits::total      163433845                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      7197565                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7197565                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      7724152                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      7724152                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       724383                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       724383                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       844788                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       844788                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       278463                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       278463                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       208196                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       208196                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     14921717                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      14921717                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     15646100                       # number of overall misses
system.cpu0.dcache.overall_misses::total     15646100                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108620779500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 108620779500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 138974834179                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 138974834179                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  74732911806                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  74732911806                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4099802000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4099802000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4408839000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4408839000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3050500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3050500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 247595613679                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 247595613679                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 247595613679                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 247595613679                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     94921884                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     94921884                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     83201949                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     83201949                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       956112                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       956112                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1111256                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1111256                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2301004                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2301004                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2260892                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2260892                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    178123833                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    178123833                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    179079945                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    179079945                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.075826                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.075826                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.092836                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.092836                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.757634                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.757634                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.760210                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.760210                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.121018                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.121018                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.092086                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.092086                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.083772                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.083772                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.087369                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.087369                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15091.323177                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15091.323177                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17992.244868                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17992.244868                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88463.510142                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88463.510142                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14722.968581                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14722.968581                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21176.386674                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21176.386674                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16592.970747                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16592.970747                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15824.749534                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15824.749534                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     23148520                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets     20510394                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           766944                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         746852                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    30.182803                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    27.462461                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      4317679                       # number of writebacks
system.cpu0.dcache.writebacks::total          4317679                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3700903                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      3700903                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6185217                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      6185217                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         5102                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         5102                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       141775                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       141775                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      9886120                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      9886120                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      9886120                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      9886120                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3496662                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3496662                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1538935                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1538935                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       717217                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       717217                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       839686                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       839686                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       136688                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       136688                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       208181                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       208181                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5035597                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5035597                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5752814                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5752814                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        21352                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        21352                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        23308                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        23308                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        44660                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        44660                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  50025996500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50025996500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  29968345030                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  29968345030                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17752964500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17752964500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  73677446306                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  73677446306                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1889285500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1889285500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4200723000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4200723000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2985500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2985500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  79994341530                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  79994341530                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  97747306030                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  97747306030                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3896297500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3896297500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4053651000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4053651000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7949948500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7949948500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036837                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036837                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018496                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018496                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750139                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.750139                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.755619                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.755619                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059404                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059404                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.092079                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.092079                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028270                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028270                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032124                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032124                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14306.786444                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14306.786444                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19473.431321                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19473.431321                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24752.570700                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24752.570700                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87744.045162                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87744.045162                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.882682                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.882682                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20178.224718                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20178.224718                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15885.771147                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15885.771147                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16991.216130                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16991.216130                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182479.275946                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182479.275946                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173916.723872                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173916.723872                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 178010.490372                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178010.490372                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          6538162                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.955601                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          224372588                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          6538674                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            34.314693                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      17322639000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.955601                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999913                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999913                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          309                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        469120906                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       469120906                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    224372588                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      224372588                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    224372588                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       224372588                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    224372588                       # number of overall hits
system.cpu0.icache.overall_hits::total      224372588                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6918516                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      6918516                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6918516                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       6918516                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6918516                       # number of overall misses
system.cpu0.icache.overall_misses::total      6918516                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  73530599413                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  73530599413                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  73530599413                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  73530599413                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  73530599413                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  73530599413                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    231291104                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    231291104                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    231291104                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    231291104                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    231291104                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    231291104                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029913                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.029913                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029913                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.029913                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029913                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.029913                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10628.088366                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10628.088366                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10628.088366                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10628.088366                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10628.088366                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10628.088366                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs     10842770                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          750                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           802318                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.514305                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets           75                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       379817                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       379817                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       379817                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       379817                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       379817                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       379817                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6538699                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      6538699                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6538699                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      6538699                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6538699                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      6538699                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  66562536735                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  66562536735                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  66562536735                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  66562536735                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  66562536735                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  66562536735                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1863746498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1863746498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1863746498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1863746498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028270                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028270                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028270                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.028270                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028270                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.028270                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10179.782971                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10179.782971                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10179.782971                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10179.782971                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10179.782971                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10179.782971                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      8420678                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      8427841                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         6477                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1085415                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2879166                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16210.435264                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          21867253                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2894850                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            7.553847                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle     16000650500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  7399.715112                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    85.098490                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    94.687899                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4348.179928                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3389.288950                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   893.464886                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.451643                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.005194                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005779                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.265392                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.206866                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.054533                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.989406                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1404                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14188                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          100                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          251                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          619                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          434                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           68                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          213                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          757                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4744                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4803                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3671                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.085693                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005615                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.865967                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       440722520                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      440722520                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       580486                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       180915                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        761401                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      4317669                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      4317669                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       115526                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total       115526                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36643                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        36643                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       998559                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       998559                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5850201                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      5850201                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3218899                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      3218899                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       227084                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       227084                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       580486                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       180915                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      5850201                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      4217458                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       10829060                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       580486                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       180915                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      5850201                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      4217458                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      10829060                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        13187                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9856                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        23043                       # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks            5                       # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total            5                       # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       140809                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       140809                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       171530                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       171530                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       296756                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       296756                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       688482                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       688482                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1127441                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1127441                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       611195                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       611195                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        13187                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9856                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       688482                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1424197                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2135722                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        13187                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9856                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       688482                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1424197                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2135722                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    534558500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    449764500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    984323000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3072018500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   3072018500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3550746499                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3550746499                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2885498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2885498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16106273500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  16106273500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  21873259998                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  21873259998                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  41772472980                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  41772472980                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  70023878999                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total  70023878999                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    534558500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    449764500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  21873259998                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  57878746480                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  80736329478                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    534558500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    449764500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  21873259998                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  57878746480                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  80736329478                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       593673                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       190771                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       784444                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      4317674                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      4317674                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       256335                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       256335                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       208173                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       208173                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1295315                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1295315                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6538683                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      6538683                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4346340                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      4346340                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       838279                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       838279                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       593673                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       190771                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      6538683                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5641655                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     12964782                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       593673                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       190771                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      6538683                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5641655                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     12964782                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022213                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.051664                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.029375                       # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000001                       # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total     0.000001                       # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.549316                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.549316                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.823978                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.823978                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.229099                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.229099                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.105294                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.105294                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.259400                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.259400                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.729107                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.729107                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022213                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.051664                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.105294                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.252443                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.164733                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022213                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.051664                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.105294                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.252443                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.164733                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40536.778646                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 45633.573458                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 42716.790348                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21816.918663                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21816.918663                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20700.440150                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20700.440150                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 360687.250000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 360687.250000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54274.466228                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54274.466228                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 31770.271406                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 31770.271406                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37050.695318                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37050.695318                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 114568.802099                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 114568.802099                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40536.778646                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 45633.573458                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31770.271406                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40639.564948                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 37802.827090                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40536.778646                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 45633.573458                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31770.271406                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40639.564948                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 37802.827090                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs         1651                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   275.166667                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1533538                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1533538                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            3                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          198                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          201                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        18639                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total        18639                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            9                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         6125                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         6125                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          198                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            9                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        24764                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        24974                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            3                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          198                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            9                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        24764                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        24974                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13184                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9658                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        22842                       # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks            5                       # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total            5                       # number of Writeback MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       117912                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total       117912                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       787872                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       787872                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       140809                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       140809                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       171530                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       171530                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       278117                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       278117                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       688473                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       688473                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1121316                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1121316                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       611195                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       611195                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13184                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9658                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       688473                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1399433                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      2110748                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        13184                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         9658                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       688473                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1399433                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       787872                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2898620                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        21352                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        42646                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        23308                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        23308                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        44660                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        65954                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    455402500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    383158000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    838560500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  47401942947                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  47401942947                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2887874997                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2887874997                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2620767495                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2620767495                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2495498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2495498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  11968940000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  11968940000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17742237498                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17742237498                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  34600470980                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  34600470980                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  66356708999                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  66356708999                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    455402500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    383158000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17742237498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  46569410980                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  65150208978                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    455402500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    383158000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17742237498                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  46569410980                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  47401942947                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 112552151925                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1704040500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3725362000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5429402500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3873404967                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3873404967                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1704040500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7598766967                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9302807467                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022208                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.050626                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.029119                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000001                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.549316                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.549316                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.823978                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.823978                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.214710                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.214710                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.105292                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.105292                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.257991                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.257991                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.729107                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.729107                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022208                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.050626                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.105292                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248054                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.162806                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022208                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.050626                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.105292                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248054                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.223576                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 36711.343140                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60164.522850                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20509.164876                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20509.164876                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15278.770448                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15278.770448                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311937.250000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311937.250000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43035.628890                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43035.628890                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25770.418735                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25770.418735                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30857.020661                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30857.020661                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108568.802099                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108568.802099                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25770.418735                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33277.342309                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30865.934246                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25770.418735                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33277.342309                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38829.564388                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174473.679281                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127313.288468                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166183.497812                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166183.497812                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170147.043596                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 141049.935819                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq        984567                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     11961948                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        38204                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        23308                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      8463420                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict     11561533                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1016095                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       502894                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       380729                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       540434                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           79                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          136                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1691199                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1306018                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6538699                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      6804200                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       945007                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       838279                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     19656927                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20547872                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       414026                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1295337                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         41914162                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    418816352                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    645201790                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1526168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4749384                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1070293694                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                   11878703                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     38928585                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.320254                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.466574                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1          26461563     67.97%     67.97% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2          12467022     32.03%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      38928585                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   18022605428                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    218178978                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   9834328997                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   9151913574                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    223594319                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    702320680                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              127974219                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         85721226                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          6122377                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            91131353                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               60172902                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            66.028760                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               17085083                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            181731                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   610901                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               610901                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        15580                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3       103695                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       293448                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       317453                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2113.928676                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 12461.929670                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-32767       312797     98.53%     98.53% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-65535         2424      0.76%     99.30% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-98303          700      0.22%     99.52% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-131071          857      0.27%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-163839          351      0.11%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::163840-196607          153      0.05%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-229375           53      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::229376-262143           19      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-294911           21      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::294912-327679           57      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-360447           14      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       317453                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       338102                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 18568.539967                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 16066.889111                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 14911.003076                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       335377     99.19%     99.19% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1909      0.56%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          302      0.09%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143          312      0.09%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679          121      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           38      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       338102                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 438848021252                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.580073                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.553130                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 437543459752     99.70%     99.70% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3    782991500      0.18%     99.88% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5    243923500      0.06%     99.94% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7    110155500      0.03%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9     88476500      0.02%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11     41634500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13     16681500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15     20049000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       649500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 438848021252                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K       103695     86.94%     86.94% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        15580     13.06%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       119275                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       610901                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       610901                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       119275                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       119275                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       730176                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    94901630                       # DTB read hits
system.cpu1.dtb.read_misses                    438242                       # DTB read misses
system.cpu1.dtb.write_hits                   77470080                       # DTB write hits
system.cpu1.dtb.write_misses                   172659                       # DTB write misses
system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   42323                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      163                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  7630                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    42941                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                95339872                       # DTB read accesses
system.cpu1.dtb.write_accesses               77642739                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        172371710                       # DTB hits
system.cpu1.dtb.misses                         610901                       # DTB misses
system.cpu1.dtb.accesses                    172982611                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    86285                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                86285                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1166                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        62692                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore         9855                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        76430                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1337.426403                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 10105.936208                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767        75617     98.94%     98.94% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535          383      0.50%     99.44% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303          204      0.27%     99.70% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071          174      0.23%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839            8      0.01%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607           13      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        76430                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        73713                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 23336.867310                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 20402.005732                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 19525.264050                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        72001     97.68%     97.68% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071         1393      1.89%     99.57% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          144      0.20%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143          112      0.15%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           36      0.05%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        73713                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 417370190772                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.853526                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.353735                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    61155433348     14.65%     14.65% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   356194673424     85.34%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       18786000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        1262500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4          35500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 417370190772                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        62692     98.17%     98.17% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         1166      1.83%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        63858                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        86285                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        86285                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        63858                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        63858                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       150143                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   203133106                       # ITB inst hits
system.cpu1.itb.inst_misses                     86285                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   30560                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   224551                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               203219391                       # ITB inst accesses
system.cpu1.itb.hits                        203133106                       # DTB hits
system.cpu1.itb.misses                          86285                       # DTB misses
system.cpu1.itb.accesses                    203219391                       # DTB accesses
system.cpu1.numCycles                       708901373                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          79210227                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     569056404                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  127974219                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          77257985                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    596249525                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               13297978                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   1936888                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles              233747                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles      6483042                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       760521                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles       721953                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                202886748                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              1527721                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  28660                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         692244892                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.964370                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.215604                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               371999522     53.74%     53.74% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1               125145403     18.08%     71.82% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                42864856      6.19%     78.01% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3               152235111     21.99%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           692244892                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.180525                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.802730                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                98103528                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            343550458                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                207545620                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             38285921                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               4759365                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            18045337                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1925812                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             590182189                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts             20993149                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               4759365                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               132299037                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               44198902                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     235238981                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                211136719                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             64611888                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             574391592                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts              5359861                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents              9789729                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                401271                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                868513                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              28581746                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents           10968                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          549201958                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            896745625                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       678703153                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           702078                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            496570478                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                52631474                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          16637084                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      14688391                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 76542594                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            94434816                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           80595349                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          8923483                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         7689116                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 551758554                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           16802636                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                558923093                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued          2479703                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       49836281                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     32327580                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        272404                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    692244892                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.807407                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.056587                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          382813800     55.30%     55.30% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1          135617529     19.59%     74.89% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2          105540069     15.25%     90.14% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           60873310      8.79%     98.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            7395424      1.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               4760      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      692244892                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu               54751854     43.35%     43.35% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 59874      0.05%     43.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                   7206      0.01%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc              22      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead              34635726     27.43%     70.83% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite             36835867     29.17%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               22      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            381080184     68.18%     68.18% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1279374      0.23%     68.41% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                67457      0.01%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.42% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         77518      0.01%     68.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.44% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            97747450     17.49%     85.92% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           78671088     14.08%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             558923093                       # Type of FU issued
system.cpu1.iq.rate                          0.788436                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                  126290549                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.225953                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1937670345                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        618057050                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    542680096                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1190983                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            486822                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       443064                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             684478646                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 734974                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         2497447                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     11391566                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        16442                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       147287                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      5480411                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      2518337                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      4561530                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               4759365                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                7377288                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1779487                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          568686865                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             94434816                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            80595349                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          14436432                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 67561                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              1633321                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        147287                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       1861843                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2641662                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4503505                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            551808656                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             94901612                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          6513481                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       125675                       # number of nop insts executed
system.cpu1.iew.exec_refs                   172371354                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               103407043                       # Number of branches executed
system.cpu1.iew.exec_stores                  77469742                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.778400                       # Inst execution rate
system.cpu1.iew.wb_sent                     543849746                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    543123160                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                263131919                       # num instructions producing a value
system.cpu1.iew.wb_consumers                431737287                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.766148                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.609472                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       43653536                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       16530232                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4232753                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    683948716                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.758427                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.554925                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    453202569     66.26%     66.26% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1    123078137     18.00%     84.26% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     49564580      7.25%     91.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     16593049      2.43%     93.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     11718092      1.71%     95.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      8048900      1.18%     96.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5489767      0.80%     97.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3345988      0.49%     98.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     12907634      1.89%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    683948716                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           441056280                       # Number of instructions committed
system.cpu1.commit.committedOps             518724902                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     158158187                       # Number of memory references committed
system.cpu1.commit.loads                     83043249                       # Number of loads committed
system.cpu1.commit.membars                    3695786                       # Number of memory barriers committed
system.cpu1.commit.branches                  98284315                       # Number of branches committed
system.cpu1.commit.fp_insts                    431344                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                475340146                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            12767541                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       359393863     69.28%     69.28% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult        1051243      0.20%     69.49% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           53001      0.01%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.50% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        68608      0.01%     69.51% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.51% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.51% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.51% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       83043249     16.01%     85.52% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      75114938     14.48%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        518724902                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             12907634                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1229236643                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1133012460                       # The number of ROB writes
system.cpu1.timesIdled                         937113                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       16656481                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 93910751930                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  441056280                       # Number of Instructions Simulated
system.cpu1.committedOps                    518724902                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.607281                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.607281                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.622169                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.622169                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               651831389                       # number of integer regfile reads
system.cpu1.int_regfile_writes              384949596                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   687947                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  437000                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                121245693                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               121813302                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1231894475                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              16565900                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements          5500590                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          430.004525                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          146156295                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5501102                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            26.568548                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8485200468500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.004525                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.839853                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.839853                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          388                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        327866519                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       327866519                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     76697860                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       76697860                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     64975008                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      64975008                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       170492                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       170492                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data        54492                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total        54492                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1753772                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1753772                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1761808                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1761808                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    141672868                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       141672868                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    141843360                       # number of overall hits
system.cpu1.dcache.overall_hits::total      141843360                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      6400758                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      6400758                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      7699637                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      7699637                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       744836                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       744836                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       409878                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       409878                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       258549                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       258549                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       208576                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       208576                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data     14100395                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total      14100395                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data     14845231                       # number of overall misses
system.cpu1.dcache.overall_misses::total     14845231                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  92687894000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  92687894000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138325220262                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 138325220262                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20294196326                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  20294196326                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4013433500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   4013433500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4392601500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4392601500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3408500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3408500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 231013114262                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 231013114262                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 231013114262                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 231013114262                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     83098618                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     83098618                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     72674645                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     72674645                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       915328                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       915328                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       464370                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       464370                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2012321                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      2012321                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1970384                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1970384                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    155773263                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    155773263                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    156688591                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    156688591                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.077026                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.077026                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.105947                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.105947                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.813737                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.813737                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.882654                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.882654                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.128483                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.128483                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105856                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105856                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.090519                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.090519                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.094744                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.094744                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14480.768371                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14480.768371                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17965.161249                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17965.161249                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 49512.772889                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 49512.772889                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15522.912485                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15522.912485                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21059.956563                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21059.956563                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16383.449844                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16383.449844                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15561.436145                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15561.436145                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs      5682783                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets     23004045                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs           345925                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets         792691                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    16.427789                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    29.020192                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3566261                       # number of writebacks
system.cpu1.dcache.writebacks::total          3566261                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3293272                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total      3293272                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      6267237                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      6267237                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         2938                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total         2938                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       130878                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total       130878                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      9560509                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      9560509                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      9560509                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      9560509                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3107486                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      3107486                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1432400                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1432400                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       744751                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       744751                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       406940                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       406940                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       127671                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       127671                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       208566                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       208566                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4539886                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4539886                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5284637                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5284637                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        16935                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        16935                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14896                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14896                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31831                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31831                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  43040497000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  43040497000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26400232128                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26400232128                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  15655161500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  15655161500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  19798456326                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  19798456326                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1838541000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1838541000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4184106500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4184106500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3337500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3337500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  69440729128                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  69440729128                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  85095890628                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  85095890628                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2604403500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2604403500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2300537000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2300537000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4904940500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4904940500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037395                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037395                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019710                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019710                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.813644                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.813644                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.876327                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.876327                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063445                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.063445                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105850                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105850                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029144                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.029144                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033727                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033727                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13850.584363                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13850.584363                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18430.768031                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18430.768031                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21020.665296                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21020.665296                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 48652.028127                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 48652.028127                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14400.615645                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14400.615645                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20061.306733                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20061.306733                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15295.698863                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15295.698863                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16102.504416                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16102.504416                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 153788.219663                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 153788.219663                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154439.916756                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154439.916756                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 154093.195313                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 154093.195313                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          5403947                       # number of replacements
system.cpu1.icache.tags.tagsinuse          501.811782                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          197154720                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5404459                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            36.480010                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8495886874000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.811782                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980101                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.980101                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           66                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        411165528                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       411165528                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    197154720                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      197154720                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    197154720                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       197154720                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    197154720                       # number of overall hits
system.cpu1.icache.overall_hits::total      197154720                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      5725810                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      5725810                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      5725810                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       5725810                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      5725810                       # number of overall misses
system.cpu1.icache.overall_misses::total      5725810                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  59819230732                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  59819230732                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  59819230732                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  59819230732                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  59819230732                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  59819230732                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    202880530                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    202880530                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    202880530                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    202880530                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    202880530                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    202880530                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028223                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.028223                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028223                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.028223                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028223                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.028223                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10447.295794                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10447.295794                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10447.295794                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10447.295794                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10447.295794                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10447.295794                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs      8523796                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          288                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs           664103                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              3                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.835051                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets           96                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       321342                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total       321342                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst       321342                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total       321342                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst       321342                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total       321342                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5404468                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5404468                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5404468                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5404468                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5404468                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5404468                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  54260492010                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  54260492010                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  54260492010                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  54260492010                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  54260492010                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  54260492010                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5791998                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5791998                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5791998                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      5791998                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.026639                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.026639                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.026639                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.026639                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.026639                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.026639                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10039.932147                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10039.932147                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10039.932147                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10039.932147                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10039.932147                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10039.932147                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86447.731343                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86447.731343                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7840068                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7844426                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit         3981                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       944222                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2377748                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13486.772220                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          18876475                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2393818                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            7.885510                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    10140216096000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5055.984886                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    70.053821                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    84.713714                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3027.541847                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  4406.199695                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   842.278257                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.308593                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004276                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005171                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.184786                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.268933                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.051409                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.823167                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1281                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           69                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14720                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           30                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          223                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          628                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          392                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           34                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           14                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           19                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1431                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5385                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4653                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3120                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.078186                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004211                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.898438                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       375099508                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      375099508                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       592978                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       185889                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        778867                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3566243                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3566243                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        83253                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        83253                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35939                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        35939                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       957303                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       957303                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4781175                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4781175                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2910784                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2910784                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       147109                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       147109                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       592978                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       185889                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4781175                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3868087                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        9428129                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       592978                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       185889                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4781175                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3868087                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       9428129                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12789                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9475                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        22264                       # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks           18                       # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total           18                       # number of Writeback misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       144289                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       144289                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       172622                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       172622                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       255780                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       255780                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       623287                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       623287                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1065341                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total      1065341                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       258817                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       258817                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12789                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9475                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       623287                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1321121                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1966672                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12789                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9475                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       623287                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1321121                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1966672                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    512874500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    430496500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    943371000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3103492000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   3103492000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3553775999                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3553775999                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3230499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3230499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  13173602496                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  13173602496                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  17677681000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  17677681000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  35240864484                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  35240864484                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  17868215998                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total  17868215998                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    512874500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    430496500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  17677681000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  48414466980                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  67035518980                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    512874500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    430496500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  17677681000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  48414466980                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  67035518980                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       605767                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       195364                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       801131                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3566261                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3566261                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       227542                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       227542                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       208561                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       208561                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1213083                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1213083                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5404462                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      5404462                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3976125                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3976125                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       405926                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       405926                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       605767                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       195364                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5404462                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      5189208                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     11394801                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       605767                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       195364                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5404462                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      5189208                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     11394801                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021112                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.048499                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.027791                       # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000005                       # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total     0.000005                       # miss rate for Writeback accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.634120                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.634120                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.827681                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.827681                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.210851                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.210851                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.115328                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.115328                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.267934                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.267934                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.637597                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.637597                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021112                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.048499                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.115328                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.254590                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.172594                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021112                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.048499                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.115328                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.254590                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.172594                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 40102.783642                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45434.986807                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 42372.035573                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21508.860689                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21508.860689                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20587.039885                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20587.039885                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 646099.800000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 646099.800000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51503.645696                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51503.645696                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28362.024236                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28362.024236                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33079.421973                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33079.421973                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69038.030724                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69038.030724                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 40102.783642                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45434.986807                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28362.024236                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36646.504733                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 34085.764673                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 40102.783642                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45434.986807                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28362.024236                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36646.504733                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 34085.764673                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs         3889                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs              13                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs   299.153846                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1147174                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1147174                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          177                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          180                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        16460                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total        16460                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         3382                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         3382                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            3                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          177                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data        19842                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        20023                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            3                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          177                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data        19842                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        20023                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12786                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9298                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        22084                       # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks           18                       # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total           18                       # number of Writeback MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       111700                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total       111700                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       804888                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       804888                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       144289                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       144289                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       172622                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       172622                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       239320                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       239320                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       623286                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       623286                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data      1061959                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total      1061959                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       258814                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       258814                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12786                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9298                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       623286                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1301279                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1946649                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12786                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9298                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       623286                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1301279                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       804888                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2751537                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        16935                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17002                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        14896                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        14896                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        31831                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        31898                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    436116500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    365754500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    801871000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  50468745441                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  50468745441                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2875133996                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2875133996                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2601766497                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2601766497                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2804499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2804499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   9250303496                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   9250303496                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  13937951500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  13937951500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  28711604984                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  28711604984                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  16314942498                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  16314942498                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    436116500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    365754500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13937951500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  37961908480                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  52701730980                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    436116500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    365754500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13937951500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  37961908480                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  50468745441                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 103170476421                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5288500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2468909500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2474198000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2188801500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2188801500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5288500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   4657711000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   4662999500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021107                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.047593                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.027566                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000005                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000005                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.634120                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.634120                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.827681                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.827681                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.197282                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.197282                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.115328                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.115328                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.267084                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.267084                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.637589                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.637589                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021107                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.047593                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.115328                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.250766                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.170837                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021107                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.047593                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.115328                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.250766                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.241473                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 36310.043470                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62702.817586                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19926.217494                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19926.217494                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15072.044681                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15072.044681                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 560899.800000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 560899.800000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 38652.446498                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 38652.446498                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22362.048081                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22362.048081                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27036.453370                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27036.453370                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63037.326026                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63037.326026                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22362.048081                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29172.766547                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27073.052707                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22362.048081                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29172.766547                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37495.580260                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145787.392973                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 145523.938360                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146938.876208                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146938.876208                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 146326.254280                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 146184.698100                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq        997626                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     10426628                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        38204                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        14896                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      7712009                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict     10305258                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq      1022601                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp           10                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       482744                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       380034                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       500528                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           70                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          136                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1988029                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1220428                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5404468                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      6543941                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       512654                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       405926                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     16212466                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17789160                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       422162                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1316947                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         35740735                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    345886640                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    566771243                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1562912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4846136                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         919066931                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                   12378423                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     35388761                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.367817                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.482211                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1          22372180     63.22%     63.22% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2          13016581     36.78%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      35388761                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   15228808958                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    179948989                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   8110869278                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   8234240098                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    227095399                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    711723893                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40342                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40342                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136642                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136642                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47708                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122642                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231246                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231246                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353968                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47728                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155749                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339000                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7339000                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496835                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36238000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           569545477                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92731000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147942000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115612                       # number of replacements
system.iocache.tags.tagsinuse               11.307418                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115628                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9081354759000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.848836                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.458583                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.240552                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.466161                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706714                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040964                       # Number of tag accesses
system.iocache.tags.data_accesses             1040964                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8895                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8932                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8895                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8935                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8895                       # number of overall misses
system.iocache.overall_misses::total             8935                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1662593136                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1667788136                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12635360341                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12635360341                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1662593136                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1668157136                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1662593136                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1668157136                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8895                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8932                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8895                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8935                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8895                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8935                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 186913.224958                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 186720.570533                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118388.429850                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118388.429850                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 186913.224958                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 186699.175825                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 186913.224958                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 186699.175825                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         32654                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3383                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.652380                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106702                       # number of writebacks
system.iocache.writebacks::total               106702                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8895                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8932                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8895                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8935                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8895                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8935                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1217843136                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1221188136                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7298960341                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7298960341                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1217843136                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1221407136                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1217843136                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1221407136                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136913.224958                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 136720.570533                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68388.429850                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68388.429850                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 136913.224958                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 136699.175825                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 136913.224958                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 136699.175825                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1760747                       # number of replacements
system.l2c.tags.tagsinuse                63871.601453                       # Cycle average of tags in use
system.l2c.tags.total_refs                    6095006                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1821172                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.346749                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   18326.572985                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   182.034797                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   268.280441                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4619.393037                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     9002.087865                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11374.868707                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   179.474155                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   242.215899                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2745.232497                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     8268.941513                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  8662.499555                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.279641                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002778                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.004094                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.070486                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.137361                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.173567                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002739                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003696                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.041889                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.126174                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.132179                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.974603                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        11384                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          237                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        48804                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2         1357                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          826                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9193                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          233                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2623                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5288                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        40501                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.173706                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003616                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.744690                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 76795315                       # Number of tag accesses
system.l2c.tags.data_accesses                76795315                       # Number of data accesses
system.l2c.Writeback_hits::writebacks         2680735                       # number of Writeback hits
system.l2c.Writeback_hits::total              2680735                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           32943                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           31048                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               63991                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          6336                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          5767                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             12103                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           174506                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           154775                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               329281                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6806                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4586                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       614111                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       638498                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       286433                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6534                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4346                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       583459                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       618336                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       287570                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          3050679                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6806                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4586                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              614111                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              813004                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       286433                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6534                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4346                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              583459                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              773111                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       287570                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3379960                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6806                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4586                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             614111                       # number of overall hits
system.l2c.overall_hits::cpu0.data             813004                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       286433                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6534                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4346                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             583459                       # number of overall hits
system.l2c.overall_hits::cpu1.data             773111                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       287570                       # number of overall hits
system.l2c.overall_hits::total                3379960                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         48112                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         44467                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             92579                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        10023                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         8706                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           18729                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         523780                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         170521                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             694301                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2882                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2624                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        74362                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       179746                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       302363                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2755                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2528                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        39827                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       128012                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       323843                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total        1058942                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2882                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2624                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             74362                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            703526                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       302363                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2755                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2528                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             39827                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            298533                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       323843                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1753243                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2882                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2624                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            74362                       # number of overall misses
system.l2c.overall_misses::cpu0.data           703526                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       302363                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2755                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2528                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            39827                       # number of overall misses
system.l2c.overall_misses::cpu1.data           298533                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       323843                       # number of overall misses
system.l2c.overall_misses::total              1753243                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    280230500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    263754000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    543984500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     55711000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     50228500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    105939500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  68581440500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  18910817992                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  87492258492                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    268423000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    251208500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6463422502                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  17884384500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  42388472929                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    254889500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    239052000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3438315000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  12527996000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  45486797416                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 129202961347                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    268423000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    251208500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6463422502                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  86465825000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  42388472929                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    254889500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    239052000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3438315000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  31438813992                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  45486797416                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    216695219839                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    268423000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    251208500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6463422502                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  86465825000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  42388472929                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    254889500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    239052000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3438315000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  31438813992                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  45486797416                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   216695219839                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks      2680735                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2680735                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        81055                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        75515                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          156570                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        16359                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        14473                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         30832                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       698286                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       325296                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1023582                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         9688                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7210                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       688473                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       818244                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       588796                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         9289                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6874                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       623286                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       746348                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       611413                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      4109621                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         9688                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7210                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          688473                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1516530                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       588796                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         9289                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6874                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          623286                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1071644                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       611413                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             5133203                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         9688                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7210                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         688473                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1516530                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       588796                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         9289                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6874                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         623286                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1071644                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       611413                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            5133203                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.593572                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.588850                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.591295                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.612690                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.601534                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.607453                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.750094                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.524203                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.678305                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.297481                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.363939                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.108010                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.219673                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.296587                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.367763                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.063898                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.171518                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.257674                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.297481                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.363939                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.108010                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.463905                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.296587                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.367763                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.063898                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.278575                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.341550                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.297481                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.363939                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.108010                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.463905                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.296587                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.367763                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.063898                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.278575                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.341550                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5824.544812                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5931.454787                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5875.895181                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5558.315873                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5769.411900                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5656.441882                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 130935.584597                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 110900.229250                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 126014.881862                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 93137.751561                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 95734.946646                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86918.352142                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 99498.094533                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92518.874773                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 94561.708861                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86331.257690                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97865.793832                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 122011.367334                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93137.751561                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 95734.946646                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 86918.352142                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 122903.524532                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92518.874773                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 94561.708861                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 86331.257690                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 105311.017516                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 123596.797386                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93137.751561                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 95734.946646                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 86918.352142                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 122903.524532                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92518.874773                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 94561.708861                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 86331.257690                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 105311.017516                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 123596.797386                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             12094                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                      115                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs    105.165217                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1358225                       # number of writebacks
system.l2c.writebacks::total                  1358225                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          229                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           34                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          211                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           37                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          511                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            229                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             34                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            211                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             37                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                511                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           229                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            34                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           211                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            37                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               511                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        57055                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        57055                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        48112                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        44467                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        92579                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10023                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8706                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        18729                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       523780                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       170521                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        694301                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         2882                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         2624                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        74133                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       179712                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       302363                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2755                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2528                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        39616                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       127975                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       323843                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total      1058431                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2882                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2624                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        74133                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       703492                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       302363                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2755                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2528                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        39616                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       298496                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       323843                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1752732                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2882                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2624                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        74133                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       703492                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       302363                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2755                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2528                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        39616                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       298496                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       323843                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1752732                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        21352                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16933                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        59646                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        23308                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14896                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38204                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        44660                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31829                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        97850                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1000759503                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    924536001                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1925295504                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    208161502                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    180991502                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    389153004                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  63343640500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  17205607992                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  80549248492                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    239603000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    224968500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5703318002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  16083965000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  39364842929                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    227339500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    213772000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3027081000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  11244495000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  42248367416                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 118577752347                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    239603000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    224968500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   5703318002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  79427605500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  39364842929                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    227339500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    213772000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   3027081000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  28450102992                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  42248367416                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 199127000839                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    239603000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    224968500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   5703318002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  79427605500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  39364842929                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    227339500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    213772000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   3027081000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  28450102992                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  42248367416                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 199127000839                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1320748000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3340995000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4081500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2164071000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6829895500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3477095533                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1935550000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5412645533                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1320748000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6818090533                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4081500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4099621000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  12242541033                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.593572                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.588850                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.591295                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.612690                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.601534                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.607453                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.750094                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.524203                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.678305                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.297481                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.363939                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.107677                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.219631                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.296587                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.367763                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.063560                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.171468                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.257550                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.297481                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.363939                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.107677                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.463883                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.296587                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.367763                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.063560                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.278540                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.341450                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.297481                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.363939                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.107677                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.463883                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.296587                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.367763                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.063560                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.278540                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.341450                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20800.621529                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.508332                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20796.244332                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20768.382919                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20789.283483                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20778.098350                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120935.584597                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 100900.229250                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 116014.881862                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76933.592354                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 89498.558805                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76410.566438                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87864.778277                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112031.632054                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76933.592354                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112904.774326                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76410.566438                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95311.504985                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 113609.496968                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76933.592354                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112904.774326                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76410.566438                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95311.504985                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 113609.496968                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156472.227426                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127801.984291                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114507.184053                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149180.347220                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 129937.567132                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141677.456104                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152666.603963                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 128801.438939                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 125115.391242                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               59646                       # Transaction distribution
system.membus.trans_dist::ReadResp            1127009                       # Transaction distribution
system.membus.trans_dist::WriteReq              38204                       # Transaction distribution
system.membus.trans_dist::WriteResp             38204                       # Transaction distribution
system.membus.trans_dist::Writeback           1464927                       # Transaction distribution
system.membus.trans_dist::CleanEvict           280718                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           444619                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         331926                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          118163                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
system.membus.trans_dist::ReadExReq            708914                       # Transaction distribution
system.membus.trans_dist::ReadExResp           687449                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       1067363                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122642                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25116                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6087631                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      6235467                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342027                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342027                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6577494                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155749                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50232                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    198978048                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    199184601                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7249472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7249472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               206434073                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           682959                       # Total snoops (count)
system.membus.snoop_fanout::samples           4505681                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4505681    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4505681                       # Request fanout histogram
system.membus.reqLayer0.occupancy            98301494                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21116985                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         10136025529                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         9507659574                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          229108938                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.trans_dist::ReadReq              59648                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           5069827                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38204                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38204                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          4145743                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1638680                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          501758                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        344029                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         845787                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          136                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          136                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1170821                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1170821                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      5017419                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9001938                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7449274                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              16451212                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    278573838                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    222195147                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              500768985                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3698425                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         14333755                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.138980                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.345926                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               12341651     86.10%     86.10% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                1992104     13.90%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           14333755                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         9346036195                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2541000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        5271518855                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4504542320                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    4738                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   14252                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------