path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.309771                       # Number of seconds simulated
sim_ticks                                47309771277000                       # Number of ticks simulated
final_tick                               47309771277000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 108265                       # Simulator instruction rate (inst/s)
host_op_rate                                   127309                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5527040503                       # Simulator tick rate (ticks/s)
host_mem_usage                                 775928                       # Number of bytes of host memory used
host_seconds                                  8559.69                       # Real time elapsed on the host
sim_insts                                   926711685                       # Number of instructions simulated
sim_ops                                    1089722710                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       238272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       235456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          4799840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         48757000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     23433152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       111936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        80000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2674208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         14294352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     12912064                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        433024                       # Number of bytes read from this memory
system.physmem.bytes_read::total            107969304                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      4799840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2674208                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7474048                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     89515968                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          89536552                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         3723                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         3679                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             90950                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            761841                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       366143                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1749                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1250                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             41828                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            223362                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       201751                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6766                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1703042                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1398687                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1401261                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          5036                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          4977                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              101456                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1030590                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       495313                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2366                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          1691                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               56525                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              302144                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       272926                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9153                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2282178                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         101456                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          56525                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             157981                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1892124                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1892559                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1892124                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         5036                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         4977                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             101456                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1031025                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       495313                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2366                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         1691                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              56525                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             302144                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       272926                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9153                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4174737                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1703042                       # Number of read requests accepted
system.physmem.writeReqs                      1401261                       # Number of write requests accepted
system.physmem.readBursts                     1703042                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1401261                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                108957568                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     37120                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  89535296                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 107969304                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               89536552                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      580                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         222271                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              104244                       # Per bank write bursts
system.physmem.perBankRdBursts::1              111881                       # Per bank write bursts
system.physmem.perBankRdBursts::2              106230                       # Per bank write bursts
system.physmem.perBankRdBursts::3              103315                       # Per bank write bursts
system.physmem.perBankRdBursts::4              101355                       # Per bank write bursts
system.physmem.perBankRdBursts::5              106401                       # Per bank write bursts
system.physmem.perBankRdBursts::6              102755                       # Per bank write bursts
system.physmem.perBankRdBursts::7              105565                       # Per bank write bursts
system.physmem.perBankRdBursts::8              101297                       # Per bank write bursts
system.physmem.perBankRdBursts::9              131029                       # Per bank write bursts
system.physmem.perBankRdBursts::10             105406                       # Per bank write bursts
system.physmem.perBankRdBursts::11             116947                       # Per bank write bursts
system.physmem.perBankRdBursts::12              96908                       # Per bank write bursts
system.physmem.perBankRdBursts::13             102973                       # Per bank write bursts
system.physmem.perBankRdBursts::14             100156                       # Per bank write bursts
system.physmem.perBankRdBursts::15             106000                       # Per bank write bursts
system.physmem.perBankWrBursts::0               86649                       # Per bank write bursts
system.physmem.perBankWrBursts::1               91854                       # Per bank write bursts
system.physmem.perBankWrBursts::2               85255                       # Per bank write bursts
system.physmem.perBankWrBursts::3               87156                       # Per bank write bursts
system.physmem.perBankWrBursts::4               84624                       # Per bank write bursts
system.physmem.perBankWrBursts::5               89053                       # Per bank write bursts
system.physmem.perBankWrBursts::6               87549                       # Per bank write bursts
system.physmem.perBankWrBursts::7               90107                       # Per bank write bursts
system.physmem.perBankWrBursts::8               85432                       # Per bank write bursts
system.physmem.perBankWrBursts::9               90372                       # Per bank write bursts
system.physmem.perBankWrBursts::10              86508                       # Per bank write bursts
system.physmem.perBankWrBursts::11              91779                       # Per bank write bursts
system.physmem.perBankWrBursts::12              81073                       # Per bank write bursts
system.physmem.perBankWrBursts::13              87139                       # Per bank write bursts
system.physmem.perBankWrBursts::14              84132                       # Per bank write bursts
system.physmem.perBankWrBursts::15              90307                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          40                       # Number of times write queue was full causing retry
system.physmem.totGap                    47309769886500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1681684                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1398687                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    611880                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    417253                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    192449                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    184576                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    110779                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     65725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     35828                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     32285                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     29054                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      9028                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     4622                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2923                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1841                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1436                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      897                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      648                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      540                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      418                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      167                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       98                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    19662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    22634                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35927                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    42991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    51483                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    60587                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    69980                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    79960                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    85124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    91378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    92978                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    97068                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    98211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   103646                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   116678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   108732                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   103454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    92841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     7303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     3997                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2565                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1572                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      925                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      663                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      482                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      104                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1072258                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      185.116224                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     114.248094                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     242.173437                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         644445     60.10%     60.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       212244     19.79%     79.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        67795      6.32%     86.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        36826      3.43%     89.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        25524      2.38%     92.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        13957      1.30%     93.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        14880      1.39%     94.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9207      0.86%     95.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        47380      4.42%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1072258                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         80097                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.254829                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      256.467221                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          80095    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::69632-73727            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           80097                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         80097                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.466185                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.028138                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.338596                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           75079     93.74%     93.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            2441      3.05%     96.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             604      0.75%     97.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             241      0.30%     97.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             302      0.38%     98.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             483      0.60%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             119      0.15%     98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              48      0.06%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              45      0.06%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              27      0.03%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              34      0.04%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              20      0.02%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             420      0.52%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              48      0.06%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              47      0.06%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              52      0.06%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              14      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               6      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             6      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             3      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            26      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             7      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::252-255             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           80097                       # Writes before turning the bus around for reads
system.physmem.totQLat                    88359532056                       # Total ticks spent queuing
system.physmem.totMemAccLat              120280694556                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   8512310000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       51901.03                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  70651.03                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.30                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.89                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.28                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.89                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.78                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1368420                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    660769                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.38                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  47.23                       # Row buffer hit rate for writes
system.physmem.avgGap                     15240061.90                       # Average gap between requests
system.physmem.pageHitRate                      65.43                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 4037576760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2203042875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                6565556400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4550560560                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3090044124960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1167667097760                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27361592107500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31636660066815                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.713051                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45518112024303                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1579777160000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    211880830197                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 4068693720                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2220021375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                6713584800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4514888160                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3090044124960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1175652112905                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27354587708250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31637801134170                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.737170                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45506397156129                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1579777160000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    223594850121                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           572                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          528                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             39                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           11                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              148829565                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         98586451                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          7318222                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups           104779817                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               69383898                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            66.218762                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               20536581                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            208145                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   633176                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               633176                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        15593                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3       103829                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       293482                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       339694                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2057.107279                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 12691.149268                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-32767       334819     98.56%     98.56% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-65535         2369      0.70%     99.26% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-98303          775      0.23%     99.49% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-131071         1050      0.31%     99.80% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-163839          325      0.10%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::163840-196607          166      0.05%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-229375           47      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::229376-262143           24      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-294911           28      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::294912-327679           54      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-360447           18      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::360448-393215           11      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-491519            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       339694                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       334006                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 19047.289570                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 15950.264710                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 18217.957975                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       329273     98.58%     98.58% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         3345      1.00%     99.58% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          501      0.15%     99.73% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          607      0.18%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          176      0.05%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           53      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           23      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           15      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       334006                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 554756829244                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.612373                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.535164                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 553440790244     99.76%     99.76% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3    774310500      0.14%     99.90% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5    264675000      0.05%     99.95% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7    116251500      0.02%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9     83135500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11     43553500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13     14917000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15     18677500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       518500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 554756829244                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K       103830     86.94%     86.94% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        15593     13.06%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       119423                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       633176                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       633176                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       119423                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       119423                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       752599                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   108615139                       # DTB read hits
system.cpu0.dtb.read_misses                    465587                       # DTB read misses
system.cpu0.dtb.write_hits                   88878639                       # DTB write hits
system.cpu0.dtb.write_misses                   167589                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   45162                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      301                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  7481                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    44285                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               109080726                       # DTB read accesses
system.cpu0.dtb.write_accesses               89046228                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        197493778                       # DTB hits
system.cpu0.dtb.misses                         633176                       # DTB misses
system.cpu0.dtb.accesses                    198126954                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    92658                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                92658                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1215                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        67279                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        10404                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        82254                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1278.472779                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  8944.038924                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        81396     98.96%     98.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          425      0.52%     99.47% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303          229      0.28%     99.75% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071          180      0.22%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        82254                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        78898                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 24333.924814                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 20592.654972                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 23297.887242                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        76185     96.56%     96.56% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071         2219      2.81%     99.37% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          249      0.32%     99.69% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143          140      0.18%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           58      0.07%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           30      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        78898                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 417288840772                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.850626                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.356648                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    62357623096     14.94%     14.94% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   354908424176     85.05%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       20580000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        1826000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         387500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 417288840772                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        67279     98.23%     98.23% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         1215      1.77%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        68494                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        92658                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        92658                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        68494                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        68494                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       161152                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   234838704                       # ITB inst hits
system.cpu0.itb.inst_misses                     92658                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   33056                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   232539                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               234931362                       # ITB inst accesses
system.cpu0.itb.hits                        234838704                       # DTB hits
system.cpu0.itb.misses                          92658                       # DTB misses
system.cpu0.itb.accesses                    234931362                       # DTB accesses
system.cpu0.numCycles                       826354541                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          96417195                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     658349874                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  148829565                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          89920479                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    686511551                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               15731276                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   2082372                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles              301509                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      6642770                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       777478                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles       876995                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                234604466                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              1859928                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  30773                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         801475508                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.962394                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.215680                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               432057914     53.91%     53.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1               143320091     17.88%     71.79% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                50277190      6.27%     78.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3               175820313     21.94%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           801475508                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.180104                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.796692                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               115405888                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            393574581                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                246061591                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             40857295                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5576153                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            21574429                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              2334934                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             682682220                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts             25205347                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5576153                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               153705251                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               60022582                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     253017805                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                248013590                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             81140127                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             664288996                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              6473093                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents             10525488                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                404111                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                973821                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              42702914                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents           12474                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          634198397                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups           1026536806                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       783997445                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           728382                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            571881769                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                62316623                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          17028830                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      14786866                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 82376276                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           108687128                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           92520441                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          9956675                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         8516242                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 640223835                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           17051325                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                645202743                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued          2940745                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       58459841                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     38213470                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        295844                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    801475508                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.805019                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.062618                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          449210773     56.05%     56.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1          147559174     18.41%     74.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2          124891919     15.58%     90.04% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           71400363      8.91%     98.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            8407753      1.05%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5               5526      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      801475508                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               66711662     45.46%     45.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 70956      0.05%     45.50% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                  22678      0.02%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc              31      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead              38740309     26.40%     71.92% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite             41215825     28.08%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            441248281     68.39%     68.39% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1607382      0.25%     68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                84016      0.01%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                 12      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         46433      0.01%     68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.66% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           111952136     17.35%     86.01% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           90264483     13.99%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             645202743                       # Type of FU issued
system.cpu0.iq.rate                          0.780782                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                  146761461                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.227466                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        2240404538                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        715416173                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    626754280                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1178660                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            474470                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       433754                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             791232333                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 731871                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         3009936                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     13422485                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        18059                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       156652                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      6220264                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2933130                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      5035754                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5576153                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                8424043                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              6068776                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          657405938                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            108687128                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            92520441                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          14528017                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 62220                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              5930416                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        156652                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2211475                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      3142674                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             5354149                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            636790575                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            108609704                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          7786358                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       130778                       # number of nop insts executed
system.cpu0.iew.exec_refs                   197486892                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               120113448                       # Number of branches executed
system.cpu0.iew.exec_stores                  88877188                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.770602                       # Inst execution rate
system.cpu0.iew.wb_sent                     628006707                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    627188034                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                305309945                       # num instructions producing a value
system.cpu0.iew.wb_consumers                500537218                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.758982                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.609965                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       51032011                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       16755481                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          5028737                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    791775198                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.756295                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.558039                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    529474510     66.87%     66.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1    135713871     17.14%     84.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     58480062      7.39%     91.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     19506672      2.46%     93.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     13859320      1.75%     95.61% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      9636766      1.22%     96.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      6431343      0.81%     97.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3969096      0.50%     98.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     14703558      1.86%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    791775198                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           510225692                       # Number of instructions committed
system.cpu0.commit.committedOps             598815315                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     181564818                       # Number of memory references committed
system.cpu0.commit.loads                     95264643                       # Number of loads committed
system.cpu0.commit.membars                    4026241                       # Number of memory barriers committed
system.cpu0.commit.branches                 114090927                       # Number of branches committed
system.cpu0.commit.fp_insts                    424114                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                549390032                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            15322892                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       415791168     69.44%     69.44% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1352857      0.23%     69.66% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           66520      0.01%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.67% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        39952      0.01%     69.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.68% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.68% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       95264643     15.91%     85.59% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      86300175     14.41%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        598815315                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             14703558                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1422522153                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1309355495                       # The number of ROB writes
system.cpu0.timesIdled                        1107002                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       24879033                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 93793188049                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  510225692                       # Number of Instructions Simulated
system.cpu0.committedOps                    598815315                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.619586                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.619586                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.617442                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.617442                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               751256572                       # number of integer regfile reads
system.cpu0.int_regfile_writes              446675945                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   709287                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  346140                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                138932349                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               139558794                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1422736351                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              16846265                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements          6557508                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          508.746857                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          168230159                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6558019                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            25.652588                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1887096000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   508.746857                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.993646                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.993646                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        376736198                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       376736198                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     88222232                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       88222232                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     74841943                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      74841943                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       232729                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       232729                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       258353                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       258353                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1906592                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1906592                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1977838                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1977838                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    163064175                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       163064175                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    163296904                       # number of overall hits
system.cpu0.dcache.overall_hits::total      163296904                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      7298679                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7298679                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      8186484                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      8186484                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       785305                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       785305                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       832077                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       832077                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       303324                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       303324                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       192936                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       192936                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     15485163                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      15485163                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     16270468                       # number of overall misses
system.cpu0.dcache.overall_misses::total     16270468                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 111692276000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 111692276000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 148685242611                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 148685242611                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  79029404267                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  79029404267                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4531612500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4531612500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4045324000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4045324000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3600000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3600000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 260377518611                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 260377518611                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 260377518611                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 260377518611                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     95520911                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     95520911                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     83028427                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     83028427                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data      1018034                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1018034                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1090430                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1090430                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2209916                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2209916                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2170774                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2170774                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    178549338                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    178549338                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    179567372                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    179567372                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.076409                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.076409                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.098599                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.098599                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771394                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.771394                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.763072                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.763072                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.137256                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.137256                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.088879                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.088879                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086728                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.086728                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.090609                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.090609                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15303.081010                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15303.081010                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18162.283419                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 18162.283419                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 94978.474669                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 94978.474669                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14939.841556                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14939.841556                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20967.180827                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20967.180827                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16814.645000                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16814.645000                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16003.074934                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16003.074934                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     24592023                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets     22766928                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           764014                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         809850                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    32.187922                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    28.112525                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      4422416                       # number of writebacks
system.cpu0.dcache.writebacks::total          4422416                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3749707                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      3749707                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6590276                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      6590276                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4547                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         4547                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       153940                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       153940                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data     10339983                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total     10339983                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data     10339983                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total     10339983                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3548972                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3548972                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1596208                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1596208                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       778051                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       778051                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       827530                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       827530                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       149384                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       149384                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       192928                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       192928                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5145180                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5145180                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5923231                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5923231                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20289                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20289                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        22269                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        22269                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        42558                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        42558                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  52135719000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  52135719000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  31476098425                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  31476098425                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17784168000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17784168000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  78021331267                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  78021331267                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   2035314000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2035314000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3852473000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3852473000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3523000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3523000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83611817425                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  83611817425                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 101395985425                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 101395985425                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3695888000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3695888000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3839366000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3839366000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7535254000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7535254000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037154                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037154                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019225                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019225                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.764268                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.764268                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.758902                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.758902                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.067597                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.067597                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.088875                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.088875                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028817                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028817                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032986                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032986                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14690.372029                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14690.372029                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.296248                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.296248                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.329404                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.329404                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94282.178612                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94282.178612                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13624.712151                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13624.712151                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19968.449370                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19968.449370                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16250.513573                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16250.513573                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17118.357434                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17118.357434                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182162.156834                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182162.156834                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172408.550002                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172408.550002                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177058.461394                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177058.461394                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          6585231                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.955630                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          227602766                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          6585743                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            34.559922                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      17287340000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.955630                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999913                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999913                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          310                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        475737897                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       475737897                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    227602766                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      227602766                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    227602766                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       227602766                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    227602766                       # number of overall hits
system.cpu0.icache.overall_hits::total      227602766                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6973294                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      6973294                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6973294                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       6973294                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6973294                       # number of overall misses
system.cpu0.icache.overall_misses::total      6973294                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  74030582287                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  74030582287                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  74030582287                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  74030582287                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  74030582287                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  74030582287                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    234576060                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    234576060                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    234576060                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    234576060                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    234576060                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    234576060                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029727                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.029727                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029727                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.029727                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029727                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.029727                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10616.300171                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10616.300171                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10616.300171                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10616.300171                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10616.300171                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10616.300171                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs     10890869                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          530                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           815898                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.348322                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets           53                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       387516                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       387516                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       387516                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       387516                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       387516                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       387516                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6585778                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      6585778                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6585778                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      6585778                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6585778                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      6585778                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  67014306188                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  67014306188                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  67014306188                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  67014306188                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  67014306188                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  67014306188                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1863746498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1863746498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1863746498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1863746498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028075                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028075                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028075                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.028075                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028075                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.028075                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10175.609653                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10175.609653                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10175.609653                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10175.609653                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10175.609653                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10175.609653                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      8598962                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      8934370                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit       290328                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1159342                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         3030105                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16246.172494                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          22237347                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         3045780                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            7.301035                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle     15974403000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  7087.125273                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    75.689704                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker   100.487660                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4186.697540                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3865.106436                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   931.065881                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.432564                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004620                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.006133                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.255536                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.235907                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.056828                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.991588                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1420                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023          100                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14155                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           86                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          252                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          649                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          433                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           77                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          206                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          782                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4799                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4726                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3642                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.086670                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006104                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.863953                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       448543088                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      448543088                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       611768                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       192592                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        804360                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      4422408                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      4422408                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       116889                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total       116889                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        39729                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        39729                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data      1062033                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total      1062033                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5870980                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      5870980                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3339122                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      3339122                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       194533                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       194533                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       611768                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       192592                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      5870980                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      4401155                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       11076495                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       611768                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       192592                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      5870980                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      4401155                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      11076495                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        14162                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        11237                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        25399                       # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks            6                       # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total            6                       # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       131236                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       131236                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       153191                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       153191                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       296814                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       296814                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       714775                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       714775                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1134930                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1134930                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       631728                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       631728                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        14162                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker        11237                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       714775                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1431744                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2171918                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        14162                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker        11237                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       714775                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1431744                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2171918                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    627635500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    557924000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   1185559500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2881179498                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2881179498                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3211389999                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3211389999                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      3406498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      3406498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  17257972999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  17257972999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22144079998                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22144079998                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  43103483484                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  43103483484                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  74596156500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total  74596156500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    627635500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    557924000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22144079998                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  60361456483                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  83691095981                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    627635500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    557924000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22144079998                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  60361456483                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  83691095981                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       625930                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       203829                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       829759                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      4422414                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      4422414                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       248125                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       248125                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       192920                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       192920                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1358847                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1358847                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6585755                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      6585755                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4474052                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      4474052                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       826261                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       826261                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       625930                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       203829                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      6585755                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5832899                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     13248413                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       625930                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       203829                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      6585755                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5832899                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     13248413                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022626                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.055130                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.030610                       # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000001                       # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total     0.000001                       # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.528911                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.528911                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.794065                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.794065                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.218431                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.218431                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.108533                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.108533                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.253669                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.253669                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.764562                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.764562                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022626                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.055130                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.108533                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.245460                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.163938                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022626                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.055130                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.108533                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.245460                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.163938                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 44318.281316                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 49650.618492                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46677.408559                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21954.185574                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21954.185574                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20963.307237                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20963.307237                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 425812.250000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 425812.250000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 58144.066651                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 58144.066651                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30980.490361                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30980.490361                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37978.979747                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37978.979747                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 118082.713605                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 118082.713605                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 44318.281316                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 49650.618492                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30980.490361                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42159.391960                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 38533.266901                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 44318.281316                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 49650.618492                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30980.490361                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42159.391960                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 38533.266901                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          232                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    77.333333                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1656758                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1656758                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            4                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          144                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          148                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        25414                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total        25414                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            4                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            4                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5426                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5426                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           23                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total           23                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          144                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            4                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        30840                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        30992                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            4                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          144                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            4                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        30840                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        30992                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        14158                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        11093                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        25251                       # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks            6                       # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total            6                       # number of Writeback MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       124422                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total       124422                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       859401                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       859401                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       131236                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       131236                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       153191                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       153191                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       271400                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       271400                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       714771                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       714771                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1129504                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1129504                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       631705                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       631705                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        14158                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        11093                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       714771                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1400904                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      2140926                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        14158                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        11093                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       714771                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1400904                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       859401                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      3000327                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20289                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        41583                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        22269                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        22269                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        42558                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63852                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    542595500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    483807000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1026402500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  56082760333                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  56082760333                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2730207494                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2730207494                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2385366995                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2385366995                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2944498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2944498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  12497558999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  12497558999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17855117998                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17855117998                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  35928472484                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  35928472484                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  70805243000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  70805243000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    542595500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    483807000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17855117998                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  48426031483                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  67307551981                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    542595500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    483807000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17855117998                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  48426031483                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  56082760333                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 123390312314                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1704040500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3533504500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5237545000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3666920967                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3666920967                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1704040500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7200425467                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8904465967                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022619                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.054423                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.030432                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000001                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.528911                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.528911                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.794065                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.794065                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.199728                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.199728                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.108533                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.108533                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.252457                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.252457                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.764534                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.764534                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022619                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.054423                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.108533                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240173                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.161599                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022619                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.054423                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.108533                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240173                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.226467                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40647.994139                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65257.964947                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65257.964947                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20803.799979                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20803.799979                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15571.195403                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15571.195403                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 368062.250000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 368062.250000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 46048.485626                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 46048.485626                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24980.193654                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24980.193654                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31809.070604                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31809.070604                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 112085.930933                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 112085.930933                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24980.193654                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34567.701629                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31438.523322                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24980.193654                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34567.701629                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65257.964947                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41125.621412                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174158.632757                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125953.995623                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164664.824060                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164664.824060                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169190.879905                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 139454.769890                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       1048889                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     12194005                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        38264                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        22269                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      8425423                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict     11622390                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1249461                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       495211                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       344893                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       512947                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           79                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          148                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1710859                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1368930                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6585778                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      6660291                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       932989                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       826261                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     19798041                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     21027852                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       446745                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1372185                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         42644823                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    421828960                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    663719558                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1630632                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5007440                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1092186590                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                   11579815                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     39116658                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.312501                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.463513                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1          26892655     68.75%     68.75% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2          12224003     31.25%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      39116658                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   18374497429                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    206346476                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   9904865164                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   9419389746                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    243194937                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    746720066                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              121710225                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         81714662                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5979961                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            85476181                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               55576245                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            65.019570                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               16076930                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            165894                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   527361                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               527361                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10839                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        84415                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       237711                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       289650                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2083.972035                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 12311.346834                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       287768     99.35%     99.35% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1260      0.44%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607          464      0.16%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143           78      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679           55      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           21      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       289650                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       263786                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 17712.334999                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 15356.267972                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 12186.421874                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       262356     99.46%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1127      0.43%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          155      0.06%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           73      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           35      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           26      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       263786                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 425904638364                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.594204                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.544845                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 424921434364     99.77%     99.77% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3    524417000      0.12%     99.89% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5    206354500      0.05%     99.94% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7    102255000      0.02%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9     73118500      0.02%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11     43959500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13     13868000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15     18884000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       347500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 425904638364                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        84415     88.62%     88.62% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        10839     11.38%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        95254                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       527361                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       527361                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        95254                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        95254                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       622615                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    90076123                       # DTB read hits
system.cpu1.dtb.read_misses                    364024                       # DTB read misses
system.cpu1.dtb.write_hits                   74326349                       # DTB write hits
system.cpu1.dtb.write_misses                   163337                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   33241                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      185                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  5418                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    36861                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                90440147                       # DTB read accesses
system.cpu1.dtb.write_accesses               74489686                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        164402472                       # DTB hits
system.cpu1.dtb.misses                         527361                       # DTB misses
system.cpu1.dtb.accesses                    164929833                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    77446                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                77446                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          594                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        55102                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore         9325                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        68121                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1127.809339                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  8184.124599                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-65535        67907     99.69%     99.69% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-131071          190      0.28%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-196607            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-262143           12      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-327679            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        68121                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        65021                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 21947.540026                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 19801.580238                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 14876.528667                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        64283     98.86%     98.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          594      0.91%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607           78      0.12%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           35      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           16      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        65021                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 387249857200                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.854665                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.352569                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    56297043096     14.54%     14.54% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   330938122104     85.46%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       13360500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        1244000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4          37500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5          50000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 387249857200                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        55102     98.93%     98.93% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          594      1.07%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        55696                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        77446                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        77446                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55696                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55696                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       133142                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   191622824                       # ITB inst hits
system.cpu1.itb.inst_misses                     77446                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              45077                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1071                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   23450                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   204512                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               191700270                       # ITB inst accesses
system.cpu1.itb.hits                        191622824                       # DTB hits
system.cpu1.itb.misses                          77446                       # DTB misses
system.cpu1.itb.accesses                    191700270                       # DTB accesses
system.cpu1.numCycles                       652098782                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          77581821                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     539946872                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  121710225                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          71653175                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    543040637                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               12931684                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   1632229                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles              244335                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles      5898534                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       685251                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles       721414                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                191398691                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              1512045                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  26398                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         636270063                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.997205                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.224602                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               332513921     52.26%     52.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1               118489139     18.62%     70.88% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                39798398      6.25%     77.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3               145468605     22.86%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           636270063                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.186644                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.828014                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                93717841                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            303303779                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                200797968                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             33854734                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               4595741                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            17115460                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1907562                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             560589350                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts             20699594                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               4595741                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               125431952                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               39494252                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     209485809                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                202527049                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             54735260                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             545352444                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts              5255771                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents              8923159                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                236326                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                251378                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              23064401                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents           10277                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          518904030                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            842346329                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       645518990                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           772636                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            467533188                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                51370836                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          14457491                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      12765800                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 68374020                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            90157460                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           77360116                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          8411660                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         7288721                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 524903956                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           14739695                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                529653671                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued          2395600                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       48736249                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     31414673                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        252865                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    636270063                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.832435                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.069985                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          346386206     54.44%     54.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1          123009687     19.33%     73.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2          101156259     15.90%     89.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           58544050      9.20%     98.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            7169989      1.13%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               3872      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      636270063                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu               53039712     43.72%     43.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 43863      0.04%     43.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                  10928      0.01%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc              13      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead              32632716     26.90%     70.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite             35589452     29.34%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                2      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            360085884     67.99%     67.99% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1163863      0.22%     68.20% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                64768      0.01%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         79405      0.01%     68.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.23% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.23% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            92781248     17.52%     85.75% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           75478453     14.25%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             529653671                       # Type of FU issued
system.cpu1.iq.rate                          0.812229                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                  121316684                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.229049                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1818002123                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        587994704                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    514426397                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1287564                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            520666                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       480327                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             650175074                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 795279                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         2341712                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     11071583                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        15258                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       136605                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      5366212                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      2403910                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      3823950                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               4595741                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                5738657                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1529256                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          539757610                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             90157460                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            77360116                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          12526602                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 63879                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              1404906                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        136605                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       1813433                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2553447                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4366880                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            522753556                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             90069669                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          6385743                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       113959                       # number of nop insts executed
system.cpu1.iew.exec_refs                   164397082                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                97927466                       # Number of branches executed
system.cpu1.iew.exec_stores                  74327413                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.801648                       # Inst execution rate
system.cpu1.iew.wb_sent                     515591253                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    514906724                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                248837648                       # num instructions producing a value
system.cpu1.iew.wb_consumers                408235008                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.789615                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.609545                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       42654937                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       14486830                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4109860                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    628197112                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.781454                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.577369                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    412381395     65.65%     65.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1    112703002     17.94%     83.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     47448288      7.55%     91.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     15899123      2.53%     93.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     11433065      1.82%     95.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      7648889      1.22%     96.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5327937      0.85%     97.56% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3177183      0.51%     98.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     12178230      1.94%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    628197112                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           416485993                       # Number of instructions committed
system.cpu1.commit.committedOps             490907395                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     151079780                       # Number of memory references committed
system.cpu1.commit.loads                     79085876                       # Number of loads committed
system.cpu1.commit.membars                    3553216                       # Number of memory barriers committed
system.cpu1.commit.branches                  92889165                       # Number of branches committed
system.cpu1.commit.fp_insts                    468052                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                450541794                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            11963242                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       338771351     69.01%     69.01% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult         933774      0.19%     69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           51484      0.01%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        70964      0.01%     69.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.22% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       79085876     16.11%     85.33% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      71993904     14.67%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        490907395                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             12178230                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1145716069                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1075160501                       # The number of ROB writes
system.cpu1.timesIdled                         888623                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       15828719                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 93967443806                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  416485993                       # Number of Instructions Simulated
system.cpu1.committedOps                    490907395                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.565716                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.565716                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.638685                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.638685                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               618570567                       # number of integer regfile reads
system.cpu1.int_regfile_writes              365658107                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   762313                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  433520                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                112664520                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               113502103                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1139246007                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              14605610                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements          5006870                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          430.966811                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          140806906                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5007379                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            28.119882                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8489665359000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.966811                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.841732                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.841732                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        313329932                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       313329932                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     73478112                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       73478112                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     62922278                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      62922278                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       161792                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       161792                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data        60224                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total        60224                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1740937                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1740937                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1748633                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1748633                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    136400390                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       136400390                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    136562182                       # number of overall hits
system.cpu1.dcache.overall_hits::total      136562182                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      5886586                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      5886586                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      6650181                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      6650181                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       625497                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       625497                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       420972                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       420972                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       235563                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       235563                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       185045                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       185045                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data     12536767                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total      12536767                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data     13162264                       # number of overall misses
system.cpu1.dcache.overall_misses::total     13162264                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  84434005000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  84434005000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 115550287907                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 115550287907                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  14693527706                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  14693527706                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3280765000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   3280765000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3888950500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   3888950500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3327000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3327000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 199984292907                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 199984292907                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 199984292907                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 199984292907                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     79364698                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     79364698                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     69572459                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     69572459                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       787289                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       787289                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       481196                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       481196                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1976500                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1976500                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1933678                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1933678                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    148937157                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    148937157                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    149724446                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    149724446                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.074171                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.074171                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.095586                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.095586                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.794495                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.794495                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.874845                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.874845                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119182                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119182                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095696                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095696                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.084175                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.084175                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.087910                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.087910                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14343.459010                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14343.459010                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17375.510216                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17375.510216                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 34903.812382                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 34903.812382                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13927.335787                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13927.335787                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21016.241995                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21016.241995                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15951.823377                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15951.823377                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.760960                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15193.760960                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs      3842918                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets     18319630                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs           344375                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets         666302                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    11.159109                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    27.494484                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3252895                       # number of writebacks
system.cpu1.dcache.writebacks::total          3252895                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3007786                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total      3007786                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5379273                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      5379273                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3474                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total         3474                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       121870                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total       121870                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      8387059                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      8387059                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      8387059                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      8387059                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2878800                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2878800                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1270908                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1270908                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       625447                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       625447                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       417498                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       417498                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       113693                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       113693                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       185035                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       185035                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4149708                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4149708                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4775155                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4775155                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        18068                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        18068                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        15995                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        15995                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        34063                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        34063                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38840223500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38840223500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  22606708667                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  22606708667                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13883914500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13883914500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  14151578206                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  14151578206                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1521353000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1521353000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3703986500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3703986500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3256000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3256000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  61446932167                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  61446932167                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  75330846667                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  75330846667                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2814873000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2814873000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2522981000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2522981000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5337854000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5337854000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036273                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036273                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018267                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018267                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.794431                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.794431                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.867626                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.867626                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.057522                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.057522                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095691                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095691                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027862                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027862                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031893                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031893                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13491.810303                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13491.810303                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17787.840400                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17787.840400                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22198.386914                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22198.386914                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 33896.158080                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 33896.158080                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13381.237191                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13381.237191                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20017.761505                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20017.761505                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14807.531558                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14807.531558                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15775.581456                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15775.581456                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155793.280939                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 155793.280939                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157735.604877                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157735.604877                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156705.340105                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156705.340105                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          5324088                       # number of replacements
system.cpu1.icache.tags.tagsinuse          501.812989                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          185755475                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5324600                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            34.886278                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8495816906000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.812989                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980103                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.980103                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        388109731                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       388109731                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    185755475                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      185755475                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    185755475                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       185755475                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    185755475                       # number of overall hits
system.cpu1.icache.overall_hits::total      185755475                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      5637082                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      5637082                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      5637082                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       5637082                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      5637082                       # number of overall misses
system.cpu1.icache.overall_misses::total      5637082                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  58647080384                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  58647080384                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  58647080384                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  58647080384                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  58647080384                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  58647080384                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    191392557                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    191392557                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    191392557                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    191392557                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    191392557                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    191392557                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029453                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.029453                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029453                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.029453                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029453                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.029453                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10403.801184                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10403.801184                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10403.801184                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10403.801184                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10403.801184                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10403.801184                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs      8439613                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets           34                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs           658051                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.825166                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets           34                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       312465                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total       312465                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst       312465                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total       312465                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst       312465                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total       312465                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5324617                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5324617                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5324617                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5324617                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5324617                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5324617                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  53161463126                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  53161463126                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  53161463126                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  53161463126                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  53161463126                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  53161463126                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6100998                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6100998                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6100998                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      6100998                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027820                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027820                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027820                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.027820                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027820                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.027820                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9984.091462                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9984.091462                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9984.091462                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  9984.091462                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9984.091462                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  9984.091462                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91059.671642                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91059.671642                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91059.671642                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91059.671642                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      6690086                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      6848412                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit       136895                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       833652                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2101281                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13129.737314                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          17962799                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2117240                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            8.484064                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    10109948263500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  3719.638298                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    30.194019                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    18.354708                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4841.731410                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3496.437967                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1023.380912                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.227029                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001843                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001120                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.295516                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.213406                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.062462                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.801376                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1215                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           80                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14664                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           26                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          222                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          606                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          357                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           15                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           24                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1327                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5436                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4651                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3112                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074158                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004883                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.895020                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       353923766                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      353923766                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       516145                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       163709                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        679854                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3252875                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3252875                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        76096                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        76096                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        32991                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        32991                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       823499                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       823499                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4739467                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4739467                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2648300                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2648300                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       186015                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       186015                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       516145                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       163709                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4739467                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3471799                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8891120                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       516145                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       163709                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4739467                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3471799                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8891120                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10986                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7768                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        18754                       # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks           19                       # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total           19                       # number of Writeback misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       135316                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       135316                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       152038                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       152038                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       244643                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       244643                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       585139                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       585139                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       965514                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       965514                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       230258                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       230258                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10986                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7768                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       585139                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1210157                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1814050                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10986                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7768                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       585139                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1210157                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1814050                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    393593000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    283804000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    677397000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2923492500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   2923492500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3131932000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3131932000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3149000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3149000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10851172997                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10851172997                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  16931159000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  16931159000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  31232900488                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  31232900488                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  11958390500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total  11958390500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    393593000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    283804000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  16931159000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  42084073485                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  59692629485                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    393593000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    283804000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  16931159000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  42084073485                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  59692629485                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       527131                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       171477                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       698608                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3252894                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3252894                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       211412                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       211412                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       185029                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       185029                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1068142                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1068142                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5324606                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      5324606                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3613814                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3613814                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       416273                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       416273                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       527131                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       171477                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5324606                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4681956                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10705170                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       527131                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       171477                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5324606                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4681956                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10705170                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020841                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.045301                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.026845                       # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000006                       # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total     0.000006                       # miss rate for Writeback accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.640058                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.640058                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.821698                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.821698                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.229036                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.229036                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.109893                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.109893                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.267173                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.267173                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.553142                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.553142                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020841                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.045301                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.109893                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.258473                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.169456                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020841                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.045301                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.109893                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.258473                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.169456                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35826.779538                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36535.015448                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36120.134371                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21604.928464                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21604.928464                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20599.665873                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20599.665873                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 524833.333333                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 524833.333333                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44355.133795                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44355.133795                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28935.276917                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28935.276917                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32348.469818                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32348.469818                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 51934.744938                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 51934.744938                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35826.779538                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36535.015448                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28935.276917                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34775.713800                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 32905.724476                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35826.779538                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36535.015448                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28935.276917                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34775.713800                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 32905.724476                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks       947503                       # number of writebacks
system.cpu1.l2cache.writebacks::total          947503                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            7                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          197                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          204                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        11124                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total        11124                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         2294                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         2294                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data           25                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total           25                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            7                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          197                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data        13418                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        13623                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            7                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          197                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data        13418                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        13623                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10979                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7571                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        18550                       # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks           19                       # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total           19                       # number of Writeback MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks        99449                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total        99449                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       669869                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       669869                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       135316                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       135316                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       152038                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       152038                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       233519                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       233519                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       585138                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       585138                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       963220                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       963220                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       230233                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       230233                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10979                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7571                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       585138                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1196739                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1800427                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10979                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7571                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       585138                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1196739                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       669869                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2470296                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        18068                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        18135                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        15995                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        15995                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        34063                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        34130                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    327529500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    230470000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    557999500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  32826022044                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  32826022044                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2716564991                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2716564991                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2299520000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2299520000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2723000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2723000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8060381997                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8060381997                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  13420310000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  13420310000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  25345446988                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  25345446988                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  10575798500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  10575798500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    327529500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    230470000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13420310000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  33405828985                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  47384138485                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    327529500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    230470000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13420310000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  33405828985                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  32826022044                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  80210160529                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5597500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2670265000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2675862500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2403001000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2403001000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5597500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5073266000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5078863500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020828                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.044152                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026553                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000006                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000006                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.640058                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.640058                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.821698                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.821698                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.218622                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.218622                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.109893                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.109893                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.266538                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.266538                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.553082                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.553082                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020828                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.044152                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.109893                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.255607                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.168183                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020828                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.044152                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.109893                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.255607                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.230757                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30080.835580                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 49003.644062                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 49003.644062                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20075.711601                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20075.711601                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15124.639893                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.639893                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 453833.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 453833.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34517.028580                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34517.028580                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22935.290478                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22935.290478                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26313.248259                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26313.248259                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45935.198256                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45935.198256                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22935.290478                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27914.047244                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26318.278100                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22935.290478                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27914.047244                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 49003.644062                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32469.858077                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83544.776119                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147789.738765                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147552.384891                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150234.510785                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150234.510785                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83544.776119                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 148937.733024                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148809.361266                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq        892292                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9878632                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        38264                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        15995                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      7255897                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      9976246                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       974296                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       447021                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       338151                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       459645                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           83                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          148                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1866908                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1075363                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5324617                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      6289738                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       523001                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       416273                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15972735                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16223776                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       373937                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1157245                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         33727693                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    340775856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    514151471                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1371816                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4217048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         860516191                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                   12204948                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     33927884                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.375605                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.484279                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1          21184404     62.44%     62.44% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2          12743480     37.56%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      33927884                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   14269396468                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    176820981                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7990923619                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7460231410                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    202704009                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    630714293                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40336                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40336                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136670                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136670                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47832                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122766                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231166                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231166                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354012                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47852                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155873                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338680                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338680                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496639                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36328000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           569486466                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92827000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147862000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115572                       # number of replacements
system.iocache.tags.tagsinuse               11.309139                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115588                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9081185715000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.844632                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.464507                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.240289                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.466532                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706821                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040604                       # Number of tag accesses
system.iocache.tags.data_accesses             1040604                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8855                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8892                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8855                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8895                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8855                       # number of overall misses
system.iocache.overall_misses::total             8895                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1639991052                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1645186052                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       373000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       373000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12624663414                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12624663414                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5568000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1639991052                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1645559052                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5568000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1639991052                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1645559052                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8855                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8892                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8855                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8895                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8855                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8895                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 185205.087747                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 185018.674314                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 124333.333333                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 124333.333333                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118288.203789                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118288.203789                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139200                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 185205.087747                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 184998.207083                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139200                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 185205.087747                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 184998.207083                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         32135                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3455                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.301013                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106702                       # number of writebacks
system.iocache.writebacks::total               106702                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8855                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8892                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8855                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8895                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8855                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8895                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1197241052                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1200586052                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       223000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       223000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7288263414                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7288263414                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3568000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1197241052                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1200809052                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3568000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1197241052                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1200809052                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135205.087747                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 135018.674314                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 74333.333333                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 74333.333333                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68288.203789                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68288.203789                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89200                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 135205.087747                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 134998.207083                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89200                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 135205.087747                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 134998.207083                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1677022                       # number of replacements
system.l2c.tags.tagsinuse                63960.007157                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5998379                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1737036                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.453227                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   15741.839802                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   357.273948                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   484.122298                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4874.372847                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    16502.292162                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20727.343192                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.818696                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     7.376448                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2388.813179                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1821.049873                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1043.704711                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.240201                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.005452                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.007387                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.074377                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.251805                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.316274                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000180                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000113                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.036450                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.027787                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.015926                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.975952                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10260                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          258                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        49496                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          879                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          504                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         8874                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          254                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2439                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4866                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        41821                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.156555                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003937                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.755249                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 75068652                       # Number of tag accesses
system.l2c.tags.data_accesses                75068652                       # Number of data accesses
system.l2c.Writeback_hits::writebacks         2604285                       # number of Writeback hits
system.l2c.Writeback_hits::total              2604285                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           28546                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           29320                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               57866                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          6394                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          5412                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             11806                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           161030                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           157813                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               318843                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6923                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4910                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       644950                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       656166                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       305817                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5910                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4051                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       543185                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       555453                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       279182                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          3006547                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6923                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4910                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              644950                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              817196                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       305817                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5910                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4051                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              543185                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              713266                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       279182                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3325390                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6923                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4910                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             644950                       # number of overall hits
system.l2c.overall_hits::cpu0.data             817196                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       305817                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5910                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4051                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             543185                       # number of overall hits
system.l2c.overall_hits::cpu1.data             713266                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       279182                       # number of overall hits
system.l2c.overall_hits::total                3325390                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         46522                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         43915                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             90437                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        10622                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         7888                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           18510                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         567822                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         117808                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             685630                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3723                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3679                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        69821                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       197538                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       366356                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1749                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1250                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        41953                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       109150                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       201783                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         997002                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker         3723                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         3679                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             69821                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            765360                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       366356                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1749                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1250                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             41953                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            226958                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       201783                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1682632                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         3723                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         3679                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            69821                       # number of overall misses
system.l2c.overall_misses::cpu0.data           765360                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       366356                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1749                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1250                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            41953                       # number of overall misses
system.l2c.overall_misses::cpu1.data           226958                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       201783                       # number of overall misses
system.l2c.overall_misses::total              1682632                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    264342500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    275145500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    539488000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     60602000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     45349000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    105951000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  73693634000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  12026393499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  85720027499                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    347505000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    338090000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6068374002                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  19146364498                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  50780119067                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    166591000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    119960500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3610747500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  10634037494                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  27957366963                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 119169156024                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    347505000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    338090000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6068374002                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  92839998498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  50780119067                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    166591000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    119960500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3610747500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  22660430993                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  27957366963                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    204889183523                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    347505000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    338090000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6068374002                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  92839998498                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  50780119067                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    166591000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    119960500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3610747500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  22660430993                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  27957366963                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   204889183523                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks      2604285                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2604285                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        75068                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        73235                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          148303                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        17016                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        13300                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         30316                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       728852                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       275621                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1004473                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        10646                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         8589                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       714771                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       853704                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       672173                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         7659                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5301                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       585138                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       664603                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       480965                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      4003549                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        10646                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         8589                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          714771                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1582556                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       672173                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         7659                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5301                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          585138                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          940224                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       480965                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             5008022                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        10646                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         8589                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         714771                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1582556                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       672173                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         7659                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5301                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         585138                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         940224                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       480965                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            5008022                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.619731                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.599645                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.609812                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.624236                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.593083                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.610569                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.779064                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.427428                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.682577                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.349709                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.428339                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.097683                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.231389                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.228359                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.235805                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.071698                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.164233                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.249030                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.349709                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.428339                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.097683                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.483623                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.228359                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.235805                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.071698                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.241387                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.335987                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.349709                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.428339                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.097683                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.483623                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.228359                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.235805                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.071698                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.241387                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.335987                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5682.096642                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6265.410452                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5965.346042                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5705.328563                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5749.112576                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5723.987034                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 129782.984809                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102084.692882                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 125023.740938                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 93340.048348                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 91897.254689                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86913.306913                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 96924.968857                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 138608.673168                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 95249.285306                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 95968.400000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86066.491073                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97425.904663                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 119527.499467                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93340.048348                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91897.254689                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 86913.306913                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 121302.391682                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 138608.673168                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 95249.285306                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 95968.400000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 86066.491073                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 99844.160563                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 121767.078911                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93340.048348                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91897.254689                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 86913.306913                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 121302.391682                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 138608.673168                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 95249.285306                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 95968.400000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 86066.491073                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 99844.160563                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138551.646883                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 121767.078911                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              9470                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                      105                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     90.190476                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1291985                       # number of writebacks
system.l2c.writebacks::total                  1291985                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          127                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           25                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          183                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           37                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          372                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            127                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             25                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            183                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             37                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                372                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           127                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            25                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           183                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            37                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               372                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        57543                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        57543                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        46522                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        43915                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        90437                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10622                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         7888                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        18510                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       567822                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       117808                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        685630                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3723                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3679                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        69694                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       197513                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       366356                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1749                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1250                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        41770                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       109113                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       201783                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       996630                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         3723                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         3679                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        69694                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       765335                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       366356                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1749                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1250                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        41770                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       226921                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       201783                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1682260                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         3723                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         3679                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        69694                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       765335                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       366356                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1749                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1250                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        41770                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       226921                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       201783                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1682260                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20289                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        18066                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        59716                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        22269                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        15995                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38264                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        42558                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        34061                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        97980                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    967860505                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    912939509                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1880800014                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    220678503                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    163861499                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    384540002                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  68015414000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  10848313499                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  78863727499                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    310275000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    301300000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5361144002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17169186498                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  47116559067                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    149101000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    107460500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3179316500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   9539742994                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  25939536963                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 109173622524                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    310275000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    301300000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   5361144002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  85184600498                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  47116559067                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    149101000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    107460500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   3179316500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  20388056493                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  25939536963                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 188037350023                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    310275000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    301300000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   5361144002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  85184600498                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  47116559067                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    149101000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    107460500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   3179316500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  20388056493                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  25939536963                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 188037350023                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1320748000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3168263000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4391000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2345032500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6838434500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3288254533                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2131065000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5419319533                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1320748000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6456517533                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4391000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4476097500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  12257754033                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.619731                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.599645                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.609812                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.624236                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.593083                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.610569                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.779064                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.427428                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.682577                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.349709                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.428339                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.097505                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.231360                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.228359                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.235805                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.071385                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.164178                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.248937                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.349709                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.428339                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.097505                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.483607                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.228359                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.235805                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.071385                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.241348                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.335913                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.349709                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.428339                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.097505                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.483607                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.545032                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.228359                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.235805                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.071385                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.241348                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.419538                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.335913                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20804.361485                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20788.785358                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20796.797926                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20775.607513                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20773.516608                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20774.716478                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 119782.984809                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92084.692882                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 115023.740938                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 83340.048348                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 81897.254689                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76924.039401                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 86926.868095                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 128608.673168                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 85249.285306                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 85968.400000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76114.831219                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87429.939549                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128551.646883                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109542.781698                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83340.048348                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 81897.254689                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76924.039401                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 111303.678125                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 128608.673168                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 85249.285306                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 85968.400000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76114.831219                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89846.495005                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128551.646883                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 111776.627883                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83340.048348                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 81897.254689                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76924.039401                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 111303.678125                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 128608.673168                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 85249.285306                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 85968.400000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76114.831219                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89846.495005                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128551.646883                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 111776.627883                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156156.685889                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65537.313433                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 129803.636666                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114515.950499                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147660.628362                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133233.197874                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141629.718090                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151711.018680                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65537.313433                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 131414.154018                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 125104.654348                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               59716                       # Transaction distribution
system.membus.trans_dist::ReadResp            1065238                       # Transaction distribution
system.membus.trans_dist::WriteReq              38264                       # Transaction distribution
system.membus.trans_dist::WriteResp             38264                       # Transaction distribution
system.membus.trans_dist::Writeback           1398687                       # Transaction distribution
system.membus.trans_dist::CleanEvict           273545                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           431435                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         293289                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          115559                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            699678                       # Transaction distribution
system.membus.trans_dist::ReadExResp           679021                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       1005522                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122766                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25252                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5818316                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5966412                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342390                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342390                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6308802                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155873                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    190243904                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    190450853                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7261952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7261952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               197712805                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           632700                       # Total snoops (count)
system.membus.snoop_fanout::samples           4309210                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4309210    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4309210                       # Request fanout histogram
system.membus.reqLayer0.occupancy            98315494                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21255984                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9692600374                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         9139212712                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          229129958                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq              59718                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4906213                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38264                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38264                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          4003012                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1629651                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          482692                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        305095                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         787787                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          148                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          148                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1150777                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1150777                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4853770                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9404841                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6602998                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              16007839                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    297836822                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    190023375                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              487860197                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3506825                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         13882904                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.137454                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.344326                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               11974647     86.25%     86.25% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                1908257     13.75%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           13882904                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8939333587                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2427000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        5448458649                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4022349362                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    4812                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   13871                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------