summaryrefslogtreecommitdiff
path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
blob: e3c32f3fbda77d317e0cda61b228c929ada22e14 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.216814                       # Number of seconds simulated
sim_ticks                                47216814145000                       # Number of ticks simulated
final_tick                               47216814145000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1096625                       # Simulator instruction rate (inst/s)
host_op_rate                                  1290081                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            53081906922                       # Simulator tick rate (ticks/s)
host_mem_usage                                 734248                       # Number of bytes of host memory used
host_seconds                                   889.51                       # Real time elapsed on the host
sim_insts                                   975457230                       # Number of instructions simulated
sim_ops                                    1147538415                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       152640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       127168                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3766772                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         62976200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       221312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       220864                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2509128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         46395632                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        419264                       # Number of bytes read from this memory
system.physmem.bytes_read::total            116788980                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3766772                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2509128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6275900                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    100984448                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total         101005032                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2385                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1987                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             99263                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            984016                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         3458                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         3451                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             39312                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            724948                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6551                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1865371                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1577882                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1580456                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3233                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2693                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               79776                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1333766                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          4687                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          4678                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               53141                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              982608                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8880                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2473462                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          79776                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          53141                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             132917                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2138739                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                436                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2139175                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2138739                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3233                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2693                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              79776                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1334202                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         4687                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         4678                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              53141                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             982608                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8880                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4612637                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   125229                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               125229                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples       125229                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         125229    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       125229                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0       22846000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        96746     89.71%     89.71% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        11103     10.29%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       107849                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       125229                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       125229                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       107849                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       107849                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       233078                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    92662773                       # DTB read hits
system.cpu0.dtb.read_misses                     88786                       # DTB read misses
system.cpu0.dtb.write_hits                   85694958                       # DTB write hits
system.cpu0.dtb.write_misses                    36443                       # DTB write misses
system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              49427                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   36354                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  5600                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10503                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                92751559                       # DTB read accesses
system.cpu0.dtb.write_accesses               85731401                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        178357731                       # DTB hits
system.cpu0.dtb.misses                         125229                       # DTB misses
system.cpu0.dtb.accesses                    178482960                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    61377                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                61377                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        61377                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          61377    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        61377                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0       22844500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        55424     98.80%     98.80% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          672      1.20%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        56096                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        61377                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        61377                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        56096                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        56096                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       117473                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   497696393                       # ITB inst hits
system.cpu0.itb.inst_misses                     61377                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              49427                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   25032                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               497757770                       # ITB inst accesses
system.cpu0.itb.hits                        497696393                       # DTB hits
system.cpu0.itb.misses                          61377                       # DTB misses
system.cpu0.itb.accesses                    497757770                       # DTB accesses
system.cpu0.numCycles                     94433643486                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  497466384                       # Number of instructions committed
system.cpu0.committedOps                    584970773                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            536103359                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                526132                       # Number of float alu accesses
system.cpu0.num_func_calls                   28869117                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     76496594                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   536103359                       # number of integer instructions
system.cpu0.num_fp_insts                       526132                       # number of float instructions
system.cpu0.num_int_register_reads          784958858                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         425337843                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              849923                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             443780                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           133878831                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          133531045                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    178459396                       # number of memory refs
system.cpu0.num_load_insts                   92737001                       # Number of load instructions
system.cpu0.num_store_insts                  85722395                       # Number of store instructions
system.cpu0.num_idle_cycles              93848339121.288452                       # Number of idle cycles
system.cpu0.num_busy_cycles              585304364.711543                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.006198                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.993802                       # Percentage of idle cycles
system.cpu0.Branches                        111287587                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                405476023     69.28%     69.28% # Class of executed instruction
system.cpu0.op_class::IntMult                 1232194      0.21%     69.49% # Class of executed instruction
system.cpu0.op_class::IntDiv                    59840      0.01%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                 21      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             72507      0.01%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::MemRead                92737001     15.84%     85.35% # Class of executed instruction
system.cpu0.op_class::MemWrite               85722395     14.65%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 585300003                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   15195                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          6272771                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          500.885315                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          172015771                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6273283                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.420375                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.885315                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.978292                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.978292                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        363162248                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       363162248                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     86214911                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       86214911                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     80919852                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      80919852                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       215654                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       215654                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       262009                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       262009                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2076466                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      2076466                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2036568                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      2036568                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    167134763                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       167134763                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    167350417                       # number of overall hits
system.cpu0.dcache.overall_hits::total      167350417                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3309382                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3309382                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1475590                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1475590                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       772139                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       772139                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       831711                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       831711                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       119816                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       119816                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       158575                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       158575                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4784972                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4784972                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5557111                       # number of overall misses
system.cpu0.dcache.overall_misses::total      5557111                       # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data     89524293                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     89524293                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     82395442                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     82395442                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       987793                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       987793                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1093720                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1093720                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2196282                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2196282                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2195143                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2195143                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    171919735                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    171919735                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    172907528                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    172907528                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036966                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036966                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017909                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017909                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.781681                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.781681                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.760442                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.760442                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054554                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054554                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.072239                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.072239                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027833                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.027833                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032139                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.032139                       # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      4465852                       # number of writebacks
system.cpu0.dcache.writebacks::total          4465852                       # number of writebacks
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          5539081                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.989005                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          492212891                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5539593                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            88.853620                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       5759896500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.989005                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           64                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses       1001044576                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses      1001044576                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    492212891                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      492212891                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    492212891                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       492212891                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    492212891                       # number of overall hits
system.cpu0.icache.overall_hits::total      492212891                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5539598                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5539598                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5539598                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5539598                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5539598                       # number of overall misses
system.cpu0.icache.overall_misses::total      5539598                       # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst    497752489                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    497752489                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    497752489                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    497752489                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    497752489                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    497752489                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011129                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011129                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011129                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011129                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011129                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011129                       # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2711851                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16210.481258                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          18787660                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2727832                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.887396                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle       290949000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  5681.130997                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    53.077110                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    57.001745                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4560.666382                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  5858.605025                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.346749                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003240                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003479                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.278361                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.357581                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.989409                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           46                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15935                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           35                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          229                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1157                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4616                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5323                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4610                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.002808                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.972595                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       396153496                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      396153496                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       271024                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       142798                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        413822                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      4465852                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      4465852                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data         3520                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total         3520                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       634528                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       634528                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4971317                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      4971317                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2943098                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2943098                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       222986                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       222986                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       271024                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       142798                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4971317                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3577626                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8962765                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       271024                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       142798                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4971317                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3577626                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8962765                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11253                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8486                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        19739                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       128216                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       128216                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       158575                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       158575                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       709702                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       709702                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       568281                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       568281                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1258239                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1258239                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       608349                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       608349                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        11253                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8486                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       568281                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1967941                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2555961                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11253                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8486                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       568281                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1967941                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2555961                       # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       282277                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       151284                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       433561                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      4465852                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      4465852                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       131736                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       131736                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       158575                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       158575                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1344230                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1344230                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5539598                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      5539598                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4201337                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      4201337                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       831335                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       831335                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       282277                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       151284                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5539598                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5545567                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     11518726                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       282277                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       151284                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5539598                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5545567                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     11518726                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.039865                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.056093                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.045528                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.973280                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.973280                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.527962                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.527962                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.102585                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.102585                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.299485                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.299485                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.731774                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.731774                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.039865                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.056093                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.102585                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.354867                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.221896                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.039865                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.056093                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.102585                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.354867                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.221896                       # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1571493                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1571493                       # number of writebacks
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests     24275029                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12358536                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1399                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       471082                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       471076                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        623009                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     10363944                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        32419                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        32419                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      4465852                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      7344601                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       131736                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       158575                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       290311                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1344230                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1344230                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5539598                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4201337                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       831335                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       831335                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     16703618                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19736583                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       366654                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       728076                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         37534931                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    354706772                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    640924169                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1466616                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2912304                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1000009861                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    4846239                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     29334646                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.024894                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.155804                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          28604393     97.51%     97.51% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            730247      2.49%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 6      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      29334646                       # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   144041                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               144041                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples       144041                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         144041    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       144041                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples   -274403872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -274403872    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   -274403872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K       111414     88.97%     88.97% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        13807     11.03%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       125221                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       144041                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       144041                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       125221                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       125221                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       269262                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    90153061                       # DTB read hits
system.cpu1.dtb.read_misses                    111753                       # DTB read misses
system.cpu1.dtb.write_hits                   81132787                       # DTB write hits
system.cpu1.dtb.write_misses                    32288                       # DTB write misses
system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              49427                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   44587                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4554                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    11374                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                90264814                       # DTB read accesses
system.cpu1.dtb.write_accesses               81165075                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        171285848                       # DTB hits
system.cpu1.dtb.misses                         144041                       # DTB misses
system.cpu1.dtb.accesses                    171429889                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    60885                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                60885                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples        60885                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          60885    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        60885                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples   -274404872                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -274404872    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -274404872                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        53790     99.07%     99.07% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          505      0.93%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        54295                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60885                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60885                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        54295                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        54295                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       115180                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   478248118                       # ITB inst hits
system.cpu1.itb.inst_misses                     60885                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              49427                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   31530                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               478309003                       # ITB inst accesses
system.cpu1.itb.hits                        478248118                       # DTB hits
system.cpu1.itb.misses                          60885                       # DTB misses
system.cpu1.itb.accesses                    478309003                       # DTB accesses
system.cpu1.numCycles                     94433635490                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  477990846                       # Number of instructions committed
system.cpu1.committedOps                    562567642                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            516282159                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                374678                       # Number of float alu accesses
system.cpu1.num_func_calls                   28237407                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     73185792                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   516282159                       # number of integer instructions
system.cpu1.num_fp_insts                       374678                       # number of float instructions
system.cpu1.num_int_register_reads          763231058                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         411079626                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              608455                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             306456                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           126379788                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          126112608                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    171406825                       # number of memory refs
system.cpu1.num_load_insts                   90251973                       # Number of load instructions
system.cpu1.num_store_insts                  81154852                       # Number of store instructions
system.cpu1.num_idle_cycles              93870751219.397461                       # Number of idle cycles
system.cpu1.num_busy_cycles              562884270.602548                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.005961                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.994039                       # Percentage of idle cycles
system.cpu1.Branches                        106497601                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                390236864     69.33%     69.33% # Class of executed instruction
system.cpu1.op_class::IntMult                 1137629      0.20%     69.53% # Class of executed instruction
system.cpu1.op_class::IntDiv                    60962      0.01%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             37059      0.01%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::MemRead                90251973     16.03%     85.58% # Class of executed instruction
system.cpu1.op_class::MemWrite               81154852     14.42%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 562879339                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    7199                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements          5945049                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          438.290639                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          165346662                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5945561                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            27.810103                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8470277778500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   438.290639                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.856036                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.856036                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          368                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        348813711                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       348813711                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     83697564                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       83697564                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     76990146                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      76990146                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       187854                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       187854                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data        63440                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total        63440                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2062256                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      2062256                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2048851                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      2048851                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    160687710                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       160687710                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    160875564                       # number of overall hits
system.cpu1.dcache.overall_hits::total      160875564                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3358222                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3358222                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1453330                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1453330                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       792351                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       792351                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       427059                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       427059                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       146820                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       146820                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       158898                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       158898                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4811552                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4811552                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      5603903                       # number of overall misses
system.cpu1.dcache.overall_misses::total      5603903                       # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data     87055786                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     87055786                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     78443476                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     78443476                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       980205                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       980205                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       490499                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       490499                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2209076                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      2209076                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2207749                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      2207749                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    165499262                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    165499262                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    166479467                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    166479467                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038576                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.038576                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018527                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018527                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.808352                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.808352                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.870662                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.870662                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.066462                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.066462                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.071973                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.071973                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029073                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.029073                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033661                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.033661                       # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      4029235                       # number of writebacks
system.cpu1.dcache.writebacks::total          4029235                       # number of writebacks
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          4741297                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.426080                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          473560604                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4741809                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            99.869186                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8470205816000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.426080                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969582                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969582                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        961346635                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       961346635                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    473560604                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      473560604                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    473560604                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       473560604                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    473560604                       # number of overall hits
system.cpu1.icache.overall_hits::total      473560604                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4741809                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4741809                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4741809                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4741809                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4741809                       # number of overall misses
system.cpu1.icache.overall_misses::total      4741809                       # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst    478302413                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    478302413                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    478302413                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    478302413                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    478302413                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    478302413                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009914                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.009914                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009914                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.009914                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.009914                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.009914                       # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2280083                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13449.950084                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          17410791                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2296131                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            7.582664                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9726491516500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5225.723861                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    68.459971                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    87.577044                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2849.184130                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  5219.005079                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.318953                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004178                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005345                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.173900                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.318543                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.820920                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023          105                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15943                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           68                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1612                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5944                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4501                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3801                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.006409                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.973083                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       360471879                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      360471879                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       324612                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       139654                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        464266                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      4029235                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      4029235                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         3866                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         3866                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       614223                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       614223                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4216163                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4216163                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3057520                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      3057520                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       161092                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       161092                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       324612                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       139654                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4216163                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3671743                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8352172                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       324612                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       139654                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4216163                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3671743                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8352172                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12357                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9710                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        22067                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       133787                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       133787                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       158898                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       158898                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       701667                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       701667                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       525646                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       525646                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1239873                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total      1239873                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       265754                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       265754                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12357                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9710                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       525646                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1941540                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      2489253                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12357                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9710                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       525646                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1941540                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      2489253                       # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       336969                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       149364                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       486333                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      4029235                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      4029235                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       137653                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       137653                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       158898                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       158898                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1315890                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1315890                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4741809                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      4741809                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4297393                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      4297393                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       426846                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       426846                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       336969                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       149364                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4741809                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      5613283                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10841425                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       336969                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       149364                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4741809                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      5613283                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10841425                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.036671                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.065009                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.045374                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.971915                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.971915                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.533226                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.533226                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.110853                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.110853                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.288517                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.288517                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.622599                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.622599                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.036671                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.065009                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.110853                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.345883                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.229606                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.036671                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.065009                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.110853                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.345883                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.229606                       # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1182496                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1182496                       # number of writebacks
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests     22040452                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11258515                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          368                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       465210                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       465207                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq        606211                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9645413                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         6383                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         6383                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      4029235                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      6656743                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       137653                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       158898                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       296551                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1315890                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1315890                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4741809                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4297393                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       426846                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       426846                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14225112                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18643588                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       364008                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       835436                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         34068144                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    303476296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    617159548                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1456032                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3341744                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         925433620                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    4444908                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     26656221                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.027820                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.164457                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          25914657     97.22%     97.22% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            741561      2.78%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 3      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      26656221                       # Request fanout histogram
system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136634                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136634                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47636                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122570                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231208                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231208                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353858                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47656                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155677                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338848                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338848                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496611                       # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements               115585                       # number of replacements
system.iocache.tags.tagsinuse               11.290896                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115601                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9107775783009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.851982                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.438915                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.240749                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.464932                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.705681                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040793                       # Number of tag accesses
system.iocache.tags.data_accesses             1040793                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8876                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8913                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8876                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8916                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8876                       # number of overall misses
system.iocache.overall_misses::total             8916                       # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8876                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8913                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8876                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8916                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8876                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8916                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1756378                       # number of replacements
system.l2c.tags.tagsinuse                62298.874763                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4716146                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1814465                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.599194                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   34280.883889                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    45.238820                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker    58.953050                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3333.891398                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6982.835280                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   308.005625                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   424.754545                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2990.314104                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    13873.998053                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.523085                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000690                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000900                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.050871                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.106550                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004700                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.006481                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.045629                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.211700                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.950605                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          228                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        57859                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          227                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          548                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3455                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5562                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        48240                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.003479                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.882858                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 74820318                       # Number of tag accesses
system.l2c.tags.data_accesses                74820318                       # Number of data accesses
system.l2c.Writeback_hits::writebacks         2753989                       # number of Writeback hits
system.l2c.Writeback_hits::total              2753989                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           13132                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           10939                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               24071                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          1512                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          1301                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              2813                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           319600                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           264468                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               584068                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6283                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4584                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       512119                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       747634                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5445                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         3568                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       486435                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       695595                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2461663                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6283                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4584                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              512119                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             1067234                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5445                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3568                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              486435                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              960063                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3045731                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6283                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4584                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             512119                       # number of overall hits
system.l2c.overall_hits::cpu0.data            1067234                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5445                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3568                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             486435                       # number of overall hits
system.l2c.overall_hits::cpu1.data             960063                       # number of overall hits
system.l2c.overall_hits::total                3045731                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         58697                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         54120                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            112817                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         7808                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         7401                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           15209                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         816140                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         547219                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total            1363359                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2385                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1987                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        56162                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       181808                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         3458                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         3451                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        39211                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       186749                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         475211                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2385                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1987                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             56162                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            997948                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         3458                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         3451                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             39211                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            733968                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1838570                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2385                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1987                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            56162                       # number of overall misses
system.l2c.overall_misses::cpu0.data           997948                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         3458                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         3451                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            39211                       # number of overall misses
system.l2c.overall_misses::cpu1.data           733968                       # number of overall misses
system.l2c.overall_misses::total              1838570                       # number of overall misses
system.l2c.Writeback_accesses::writebacks      2753989                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2753989                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        71829                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        65059                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          136888                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         9320                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         8702                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         18022                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1135740                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       811687                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1947427                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         8668                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6571                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       568281                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       929442                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8903                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7019                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       525646                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       882344                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      2936874                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8668                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6571                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          568281                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         2065182                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         8903                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7019                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          525646                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1694031                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4884301                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8668                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6571                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         568281                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        2065182                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         8903                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7019                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         525646                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1694031                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4884301                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.817177                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.831860                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.824156                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.837768                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.850494                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.843913                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.718598                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.674175                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.700082                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.275150                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.302389                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.098828                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.195610                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.388408                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.491665                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.074596                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.211651                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.161808                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.275150                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.302389                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.098828                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.483225                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.388408                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.491665                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.074596                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.433267                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.376424                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.275150                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.302389                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.098828                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.483225                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.388408                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.491665                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.074596                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.433267                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.376424                       # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1471188                       # number of writebacks
system.l2c.writebacks::total                  1471188                       # number of writebacks
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               82131                       # Transaction distribution
system.membus.trans_dist::ReadResp             566255                       # Transaction distribution
system.membus.trans_dist::WriteReq              38802                       # Transaction distribution
system.membus.trans_dist::WriteResp             38802                       # Transaction distribution
system.membus.trans_dist::Writeback           1577882                       # Transaction distribution
system.membus.trans_dist::CleanEvict           244930                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           328773                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         314660                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          150374                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1610566                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1341014                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        484124                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122570                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27558                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6497230                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      6647450                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       344319                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       344319                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6991769                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155677                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        55116                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    210588188                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    210799185                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7398848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7398848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               218198033                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples           4791150                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4791150    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4791150                       # Request fanout histogram
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             164                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              164                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     11435399                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      5875226                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1762842                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         121928                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       112531                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops         9397                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              82133                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           3715978                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38802                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38802                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          2753989                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1064741                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          330496                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        317473                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         647969                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2216979                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2216979                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      3633845                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9232436                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7825750                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17058186                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    301171869                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    249940932                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              551112801                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1989284                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         13543939                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.291452                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.455956                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                9605923     70.92%     70.92% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                3928619     29.01%     99.93% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                   9397      0.07%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           13543939                       # Request fanout histogram

---------- End Simulation Statistics   ----------