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|
---------- Begin Simulation Statistics ----------
sim_seconds 47.216815 # Number of seconds simulated
sim_ticks 47216814802000 # Number of ticks simulated
final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1112312 # Simulator instruction rate (inst/s)
host_op_rate 1308465 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 53753255119 # Simulator tick rate (ticks/s)
host_mem_usage 687512 # Number of bytes of host memory used
host_seconds 878.40 # Real time elapsed on the host
sim_insts 977053655 # Number of instructions simulated
sim_ops 1149354696 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 34948936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 222656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2668232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 38725552 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 417728 # Number of bytes read from this memory
system.physmem.bytes_read::total 81375732 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3895860 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2668232 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6564092 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 101375872 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 101396456 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2349 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1944 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 101280 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 546090 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 3479 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 41798 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 605103 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6527 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1312039 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1583998 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1586572 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3184 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2635 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 82510 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 740180 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 4716 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 56510 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 820164 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8847 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1723448 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 82510 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 56510 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 139020 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2147029 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2147465 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2147029 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3184 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2635 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 82510 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 740616 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 4716 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 56510 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 124420 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 124420 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 124420 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 95857 89.92% 89.92% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 10751 10.08% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 106608 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124420 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124420 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106608 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106608 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 231028 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 91801710 # DTB read hits
system.cpu0.dtb.read_misses 88193 # DTB read misses
system.cpu0.dtb.write_hits 84999619 # DTB write hits
system.cpu0.dtb.write_misses 36227 # DTB write misses
system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 36369 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 91889903 # DTB read accesses
system.cpu0.dtb.write_accesses 85035846 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 176801329 # DTB hits
system.cpu0.dtb.misses 124420 # DTB misses
system.cpu0.dtb.accesses 176925749 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 60852 # Table walker walks requested
system.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 60852 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 60852 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 54793 98.83% 98.83% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 650 1.17% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 55443 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60852 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60852 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55443 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55443 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 116295 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 493637993 # ITB inst hits
system.cpu0.itb.inst_misses 60852 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 25117 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 493698845 # ITB inst accesses
system.cpu0.itb.hits 493637993 # DTB hits
system.cpu0.itb.misses 60852 # DTB misses
system.cpu0.itb.accesses 493698845 # DTB accesses
system.cpu0.numCycles 94433642835 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 13230 # number of quiesce instructions executed
system.cpu0.committedInsts 493402150 # Number of instructions committed
system.cpu0.committedOps 580232432 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 531778274 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 521057 # Number of float alu accesses
system.cpu0.num_func_calls 28738017 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 75812609 # number of instructions that are conditional controls
system.cpu0.num_int_insts 531778274 # number of integer instructions
system.cpu0.num_fp_insts 521057 # number of float instructions
system.cpu0.num_int_register_reads 778807297 # number of times the integer registers were read
system.cpu0.num_int_register_writes 421918818 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 841474 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 439940 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 132610797 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 132275173 # number of times the CC registers were written
system.cpu0.num_mem_refs 176902115 # number of memory refs
system.cpu0.num_load_insts 91875039 # Number of load instructions
system.cpu0.num_store_insts 85027076 # Number of store instructions
system.cpu0.num_idle_cycles 93853071494.060760 # Number of idle cycles
system.cpu0.num_busy_cycles 580571340.939238 # Number of busy cycles
system.cpu0.not_idle_fraction 0.006148 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.993852 # Percentage of idle cycles
system.cpu0.Branches 110403926 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 402310075 69.30% 69.30% # Class of executed instruction
system.cpu0.op_class::IntMult 1222689 0.21% 69.51% # Class of executed instruction
system.cpu0.op_class::IntDiv 59704 0.01% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 72217 0.01% 69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction
system.cpu0.op_class::MemRead 91875039 15.83% 85.35% # Class of executed instruction
system.cpu0.op_class::MemWrite 85027076 14.65% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 580566843 # Class of executed instruction
system.cpu0.dcache.tags.replacements 6218107 # number of replacements
system.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 6218619 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.419706 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.352532 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983110 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.983110 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 80242803 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214677 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 214677 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 260385 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 260385 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076595 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 2076595 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2038168 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 2038168 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 165891148 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 165891148 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 166105825 # number of overall hits
system.cpu0.dcache.overall_hits::total 166105825 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 3280646 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3280646 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1472125 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1472125 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768471 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 768471 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 819890 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 819890 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 117360 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 117360 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154684 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 154684 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 5572661 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 5572661 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 6341132 # number of overall misses
system.cpu0.dcache.overall_misses::total 6341132 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 88668606 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 88668606 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 81714928 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 81714928 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 983148 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 983148 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1080275 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1080275 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193955 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2193955 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2192852 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2192852 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 171463809 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 171463809 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 172446957 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 172446957 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036999 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.036999 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018015 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.018015 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781643 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781643 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758964 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.758964 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053492 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053492 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070540 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070540 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032501 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.032501 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036771 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.036771 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks
system.cpu0.dcache.writebacks::total 6218107 # number of writebacks
system.cpu0.icache.tags.replacements 5488502 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 5489014 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 88.942097 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 488204417 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 488204417 # number of overall hits
system.cpu0.icache.overall_hits::total 488204417 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5489019 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 5489019 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5489019 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 5489019 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5489019 # number of overall misses
system.cpu0.icache.overall_misses::total 5489019 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 493693436 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 493693436 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 493693436 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 493693436 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 493693436 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 493693436 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011118 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.011118 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011118 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.011118 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011118 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.011118 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks
system.cpu0.icache.writebacks::total 5488502 # number of writebacks
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 2643580 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2659582 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 5.807038 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 16070.787170 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.567916 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 37.515300 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.980883 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002415 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002290 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.985588 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15949 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1503 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4323 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5407 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4485 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 4423360 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 4423360 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 7281875 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 7281875 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 738 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 738 # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 633298 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 633298 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4991790 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 4991790 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937635 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 2937635 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218374 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 218374 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 293436 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155846 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 4991790 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3570933 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 9012005 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 293436 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155846 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 4991790 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 3570933 # number of overall hits
system.cpu0.l2cache.overall_hits::total 9012005 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11306 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8709 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 20015 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136695 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 136695 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154684 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 154684 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 701772 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 701772 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1228842 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 1228842 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601138 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 601138 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11306 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8709 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1930614 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 2447858 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11306 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8709 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1930614 # number of overall misses
system.cpu0.l2cache.overall_misses::total 2447858 # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 304742 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164555 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 469297 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4423360 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 4423360 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 7281875 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 7281875 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137433 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 137433 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154684 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 154684 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1335070 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1335070 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5489019 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 5489019 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4166477 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 4166477 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819512 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total 819512 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 304742 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164555 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 5489019 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 5501547 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 11459863 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 304742 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164555 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 5489019 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 5501547 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 11459863 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052925 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.042649 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994630 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994630 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525644 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.525644 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090586 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090586 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294936 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294936 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733532 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733532 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052925 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090586 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350922 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.213603 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052925 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090586 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350922 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.213603 # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.writebacks::writebacks 1554149 # number of writebacks
system.cpu0.l2cache.writebacks::total 1554149 # number of writebacks
system.cpu0.toL2Bus.snoop_filter.tot_requests 24067586 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12257514 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1374 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 33238 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 4423360 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 7283249 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 137433 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154684 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 292117 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1335070 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1335070 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5489019 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4166477 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 819512 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 819512 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16552790 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19577101 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 363556 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 723958 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 37217405 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 702733844 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 750256336 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1454224 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2895832 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1457340236 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 6073545 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 30354370 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.066939 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.249960 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 28322817 93.31% 93.31% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 2031217 6.69% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 336 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 144355 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 144355 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 144355 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 111959 88.88% 88.88% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 14012 11.12% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 125971 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144355 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144355 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125971 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125971 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 270326 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 91325952 # DTB read hits
system.cpu1.dtb.read_misses 111931 # DTB read misses
system.cpu1.dtb.write_hits 82141676 # DTB write hits
system.cpu1.dtb.write_misses 32424 # DTB write misses
system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 44858 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 91437883 # DTB read accesses
system.cpu1.dtb.write_accesses 82174100 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 173467628 # DTB hits
system.cpu1.dtb.misses 144355 # DTB misses
system.cpu1.dtb.accesses 173611983 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 61638 # Table walker walks requested
system.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 61638 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 61638 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 54650 99.05% 99.05% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 526 0.95% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 55176 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61638 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61638 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55176 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55176 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 116814 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 483902380 # ITB inst hits
system.cpu1.itb.inst_misses 61638 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 31512 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 483964018 # ITB inst accesses
system.cpu1.itb.hits 483902380 # DTB hits
system.cpu1.itb.misses 61638 # DTB misses
system.cpu1.itb.accesses 483964018 # DTB accesses
system.cpu1.numCycles 94433635768 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 6163 # number of quiesce instructions executed
system.cpu1.committedInsts 483651505 # Number of instructions committed
system.cpu1.committedOps 569122264 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 522328734 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 379089 # Number of float alu accesses
system.cpu1.num_func_calls 28525698 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 74077236 # number of instructions that are conditional controls
system.cpu1.num_int_insts 522328734 # number of integer instructions
system.cpu1.num_fp_insts 379089 # number of float instructions
system.cpu1.num_int_register_reads 771436981 # number of times the integer registers were read
system.cpu1.num_int_register_writes 415765246 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 615128 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 311192 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 127876698 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 127597836 # number of times the CC registers were written
system.cpu1.num_mem_refs 173588529 # number of memory refs
system.cpu1.num_load_insts 91424864 # Number of load instructions
system.cpu1.num_store_insts 82163665 # Number of store instructions
system.cpu1.num_idle_cycles 93864202487.047195 # Number of idle cycles
system.cpu1.num_busy_cycles 569433280.952807 # Number of busy cycles
system.cpu1.not_idle_fraction 0.006030 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.993970 # Percentage of idle cycles
system.cpu1.Branches 107756231 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 394594292 69.30% 69.30% # Class of executed instruction
system.cpu1.op_class::IntMult 1146816 0.20% 69.50% # Class of executed instruction
system.cpu1.op_class::IntDiv 61459 0.01% 69.51% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 37349 0.01% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::MemRead 91424864 16.06% 85.57% # Class of executed instruction
system.cpu1.op_class::MemWrite 82163665 14.43% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 569428445 # Class of executed instruction
system.cpu1.dcache.tags.replacements 6003966 # number of replacements
system.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 6004478 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 27.891759 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.687505 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.827515 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.827515 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 77963660 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187526 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 187526 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 65427 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 65427 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2067288 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 2067288 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2056969 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 2056969 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 162861135 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 162861135 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 163048661 # number of overall hits
system.cpu1.dcache.overall_hits::total 163048661 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 3388721 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3388721 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 1469364 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1469364 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 795051 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 795051 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 438458 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 438458 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 148516 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 148516 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 157576 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 157576 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 5296543 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 5296543 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 6091594 # number of overall misses
system.cpu1.dcache.overall_misses::total 6091594 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 88220769 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 88220769 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 79433024 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 79433024 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 982577 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 982577 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 503885 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 503885 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2215804 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 2215804 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2214545 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 2214545 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 168157678 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 168157678 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 169140255 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 169140255 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038412 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.038412 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018498 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.018498 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809149 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809149 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870155 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870155 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067026 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067026 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071155 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071155 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031497 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.031497 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036015 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.036015 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks
system.cpu1.dcache.writebacks::total 6003966 # number of writebacks
system.cpu1.icache.tags.replacements 4799154 # number of replacements
system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 4799666 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 99.831507 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 479157890 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 479157890 # number of overall hits
system.cpu1.icache.overall_hits::total 479157890 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 4799666 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 4799666 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 4799666 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 4799666 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 4799666 # number of overall misses
system.cpu1.icache.overall_misses::total 4799666 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 483957556 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 483957556 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 483957556 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 483957556 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 483957556 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 483957556 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009918 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.009918 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009918 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.009918 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009918 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.009918 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 4799154 # number of writebacks
system.cpu1.icache.writebacks::total 4799154 # number of writebacks
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 2283161 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13345.955021 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 14389871 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2299207 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 6.258624 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 10262240501000 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 13228.741418 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.265537 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.948066 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.807418 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003129 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004025 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.814572 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1511 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4384 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3784 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 365657601 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 365657601 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 347777 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155733 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 503510 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 4070389 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 4070389 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 6732353 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 6732353 # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1054 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 1054 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 615614 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 615614 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4333068 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 4333068 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3106952 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 3106952 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 166128 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 166128 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 347777 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155733 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 4333068 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3722566 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 8559144 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 347777 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155733 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 4333068 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3722566 # number of overall hits
system.cpu1.l2cache.overall_hits::total 8559144 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12333 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9620 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 21953 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 143903 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 143903 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157576 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 157576 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 709038 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 709038 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 466598 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 466598 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1225336 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 1225336 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272085 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 272085 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12333 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9620 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 466598 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1934374 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 2422925 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12333 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9620 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 466598 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1934374 # number of overall misses
system.cpu1.l2cache.overall_misses::total 2422925 # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360110 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165353 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 525463 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4070389 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 4070389 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 6732353 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 6732353 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 144957 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 144957 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 157576 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 157576 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1324652 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1324652 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4799666 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 4799666 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4332288 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 4332288 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 438213 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 438213 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360110 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165353 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 4799666 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 5656940 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 10982069 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360110 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165353 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 4799666 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 5656940 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 10982069 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058179 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.041778 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992729 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992729 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535264 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.535264 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097215 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097215 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.282838 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.282838 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620897 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620897 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058179 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097215 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341947 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.220626 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058179 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097215 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341947 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.220626 # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.writebacks::writebacks 1211269 # number of writebacks
system.cpu1.l2cache.writebacks::total 1211269 # number of writebacks
system.cpu1.toL2Bus.snoop_filter.tot_requests 22276444 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11381625 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 5562 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4070389 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 6732731 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 144957 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157576 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 302533 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1324652 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1324652 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4799666 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4332288 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 438213 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 438213 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14398746 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18822028 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368476 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836878 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 34426128 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614325000 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 746331191 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1473904 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3347512 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1365477607 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 5687998 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 28144557 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.072239 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.258905 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 26111598 92.78% 92.78% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 2032793 7.22% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 166 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram
system.iobus.trans_dist::ReadReq 40301 # Transaction distribution
system.iobus.trans_dist::ReadResp 40301 # Transaction distribution
system.iobus.trans_dist::WriteReq 136636 # Transaction distribution
system.iobus.trans_dist::WriteResp 136636 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353874 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47662 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements 115590 # number of replacements
system.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9107775784009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.856196 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.433018 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.241012 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.464564 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.705576 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040838 # Number of tag accesses
system.iocache.tags.data_accesses 1040838 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 115609 # number of demand (read+write) misses
system.iocache.demand_misses::total 115649 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 115609 # number of overall misses
system.iocache.overall_misses::total 115649 # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 115609 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115649 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 115609 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115649 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
system.l2c.tags.replacements 1772279 # number of replacements
system.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use
system.l2c.tags.total_refs 4630026 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1831889 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.527460 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 34852.259954 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 35.728290 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 43.277467 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3264.617227 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 6940.607740 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 274.307726 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 426.439632 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2871.138387 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 14482.680343 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.531803 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000545 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000660 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.049814 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.105905 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004186 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.006507 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.043810 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.220988 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.964219 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 206 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 59404 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3390 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5782 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 49679 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.906433 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 73419992 # Number of tag accesses
system.l2c.tags.data_accesses 73419992 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 2765418 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2765418 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 17779 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 15575 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 33354 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 2588 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 2404 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 4992 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 200286 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 176214 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 376500 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6410 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4846 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 439050 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 727042 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5703 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3689 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 424901 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 685160 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2296801 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 115689 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 102800 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 218489 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 6410 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 4846 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 439050 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 927328 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5703 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 3689 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 424901 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 861374 # number of demand (read+write) hits
system.l2c.demand_hits::total 2673301 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 6410 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 4846 # number of overall hits
system.l2c.overall_hits::cpu0.inst 439050 # number of overall hits
system.l2c.overall_hits::cpu0.data 927328 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5703 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 3689 # number of overall hits
system.l2c.overall_hits::cpu1.inst 424901 # number of overall hits
system.l2c.overall_hits::cpu1.data 861374 # number of overall hits
system.l2c.overall_hits::total 2673301 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 64906 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 60031 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 124937 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 6479 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 6386 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 12865 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 376689 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 423433 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 800122 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2349 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1944 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 58179 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 178934 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3469 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3479 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 41697 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 188396 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 478447 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 477304 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 163191 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 640495 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2349 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1944 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 58179 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 555623 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 3479 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 41697 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 611829 # number of demand (read+write) misses
system.l2c.demand_misses::total 1278569 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2349 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1944 # number of overall misses
system.l2c.overall_misses::cpu0.inst 58179 # number of overall misses
system.l2c.overall_misses::cpu0.data 555623 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 3479 # number of overall misses
system.l2c.overall_misses::cpu1.inst 41697 # number of overall misses
system.l2c.overall_misses::cpu1.data 611829 # number of overall misses
system.l2c.overall_misses::total 1278569 # number of overall misses
system.l2c.WritebackDirty_accesses::writebacks 2765418 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 2765418 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 82685 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 75606 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 158291 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 9067 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 8790 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 17857 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 576975 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 599647 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 1176622 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8759 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6790 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 905976 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9172 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7168 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 466598 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 873556 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 2775248 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 592993 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 265991 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 858984 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 8759 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 6790 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1482951 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 9172 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 7168 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 466598 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 1473203 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3951870 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 8759 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 6790 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1482951 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 9172 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 7168 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 466598 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 1473203 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3951870 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784979 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793998 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.789287 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.714569 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726507 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.720446 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.652869 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.706137 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.680016 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286303 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.117006 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.197504 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485352 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089364 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.215666 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.172398 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804907 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.613521 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.745643 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.286303 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.117006 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.374674 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.485352 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.089364 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.415305 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.323535 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.286303 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.117006 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.374674 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.485352 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.089364 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.415305 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.323535 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.writebacks::writebacks 1477304 # number of writebacks
system.l2c.writebacks::total 1477304 # number of writebacks
system.membus.snoop_filter.tot_requests 4491425 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2595543 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq 82119 # Transaction distribution
system.membus.trans_dist::ReadResp 569484 # Transaction distribution
system.membus.trans_dist::WriteReq 38800 # Transaction distribution
system.membus.trans_dist::WriteResp 38800 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1583998 # Transaction distribution
system.membus.trans_dist::CleanEvict 246737 # Transaction distribution
system.membus.trans_dist::UpgradeReq 335468 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 307268 # Transaction distribution
system.membus.trans_dist::UpgradeResp 157952 # Transaction distribution
system.membus.trans_dist::ReadExReq 787861 # Transaction distribution
system.membus.trans_dist::ReadExResp 784470 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 487365 # Transaction distribution
system.membus.trans_dist::InvalidateReq 742728 # Transaction distribution
system.membus.trans_dist::InvalidateResp 742728 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27524 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6408698 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 6558890 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6905778 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55048 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175567900 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 175778835 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 183178003 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 4612344 # Request fanout histogram
system.membus.snoop_fanout::mean 0.007156 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.084293 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 4579336 99.28% 99.28% # Request fanout histogram
system.membus.snoop_fanout::1 33008 0.72% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 4612344 # Request fanout histogram
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38800 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 2765418 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2011530 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 348672 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 312260 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 660932 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1356975 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1356975 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 3459973 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 858984 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 858984 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9470177 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8222341 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 17692518 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254644772 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231031359 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 485676131 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1806287 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 13039342 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.283997 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.453251 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 9349855 71.70% 71.70% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 3675839 28.19% 99.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 13648 0.10% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 13039342 # Request fanout histogram
---------- End Simulation Statistics ----------
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