path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.474700                       # Number of seconds simulated
sim_ticks                                47474700369500                       # Number of ticks simulated
final_tick                               47474700369500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 631720                       # Simulator instruction rate (inst/s)
host_op_rate                                   743100                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            34016391858                       # Simulator tick rate (ticks/s)
host_mem_usage                                 766400                       # Number of bytes of host memory used
host_seconds                                  1395.64                       # Real time elapsed on the host
sim_insts                                   881655060                       # Number of instructions simulated
sim_ops                                    1037101350                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       127360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       143744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3459124                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         40376840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     12078528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        91584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        86464                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2488056                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         17058000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     14991744                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        410816                       # Number of bytes read from this memory
system.physmem.bytes_read::total             91312260                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3459124                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2488056                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5947180                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     77042688                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          77063272                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1990                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2246                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             94456                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            630901                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       188727                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1431                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1351                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             38964                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            266544                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       234246                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6419                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1467275                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1203792                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1206366                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2683                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          3028                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               72862                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              850492                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       254420                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1929                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          1821                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               52408                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              359307                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       315784                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8653                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1923388                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          72862                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          52408                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             125271                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1622816                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1623249                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1622816                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2683                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         3028                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              72862                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             850925                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       254420                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1929                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         1821                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              52408                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             359307                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       315784                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8653                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3546637                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1467275                       # Number of read requests accepted
system.physmem.writeReqs                      1206366                       # Number of write requests accepted
system.physmem.readBursts                     1467275                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1206366                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 93873920                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     31680                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  77062336                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  91312260                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               77063272                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      495                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         220616                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               87562                       # Per bank write bursts
system.physmem.perBankRdBursts::1               88840                       # Per bank write bursts
system.physmem.perBankRdBursts::2               82797                       # Per bank write bursts
system.physmem.perBankRdBursts::3               92927                       # Per bank write bursts
system.physmem.perBankRdBursts::4               90148                       # Per bank write bursts
system.physmem.perBankRdBursts::5               93986                       # Per bank write bursts
system.physmem.perBankRdBursts::6               87799                       # Per bank write bursts
system.physmem.perBankRdBursts::7               94269                       # Per bank write bursts
system.physmem.perBankRdBursts::8               90753                       # Per bank write bursts
system.physmem.perBankRdBursts::9              132105                       # Per bank write bursts
system.physmem.perBankRdBursts::10              81290                       # Per bank write bursts
system.physmem.perBankRdBursts::11              92144                       # Per bank write bursts
system.physmem.perBankRdBursts::12              81361                       # Per bank write bursts
system.physmem.perBankRdBursts::13              87555                       # Per bank write bursts
system.physmem.perBankRdBursts::14              92182                       # Per bank write bursts
system.physmem.perBankRdBursts::15              91062                       # Per bank write bursts
system.physmem.perBankWrBursts::0               71771                       # Per bank write bursts
system.physmem.perBankWrBursts::1               74672                       # Per bank write bursts
system.physmem.perBankWrBursts::2               72652                       # Per bank write bursts
system.physmem.perBankWrBursts::3               78055                       # Per bank write bursts
system.physmem.perBankWrBursts::4               74620                       # Per bank write bursts
system.physmem.perBankWrBursts::5               78875                       # Per bank write bursts
system.physmem.perBankWrBursts::6               73591                       # Per bank write bursts
system.physmem.perBankWrBursts::7               76891                       # Per bank write bursts
system.physmem.perBankWrBursts::8               77107                       # Per bank write bursts
system.physmem.perBankWrBursts::9               78277                       # Per bank write bursts
system.physmem.perBankWrBursts::10              71128                       # Per bank write bursts
system.physmem.perBankWrBursts::11              78119                       # Per bank write bursts
system.physmem.perBankWrBursts::12              70456                       # Per bank write bursts
system.physmem.perBankWrBursts::13              74533                       # Per bank write bursts
system.physmem.perBankWrBursts::14              76600                       # Per bank write bursts
system.physmem.perBankWrBursts::15              76752                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          39                       # Number of times write queue was full causing retry
system.physmem.totGap                    47474697259000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1424050                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1203792                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1195881                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     91231                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     37643                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     32050                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     26760                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     23675                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     20974                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     18326                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     14619                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2367                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      941                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      584                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      447                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      348                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      253                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      224                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      179                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       76                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       51                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    18047                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    20216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    49731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    58137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    63836                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    67727                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    72112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    73557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    75338                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    76158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    77610                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    81366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    78544                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    78356                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    81800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    76571                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    72953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    70532                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1899                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1287                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      892                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      376                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      370                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      359                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      107                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       940579                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      181.734800                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     113.091903                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     237.596263                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         569137     60.51%     60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       185879     19.76%     80.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        61156      6.50%     86.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        31438      3.34%     90.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        21576      2.29%     92.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        13250      1.41%     93.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         9973      1.06%     94.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9805      1.04%     95.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        38365      4.08%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         940579                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         68336                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.464104                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      309.922160                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          68334    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           68336                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         68336                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.620273                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.104093                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.841865                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           64690     94.66%     94.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            1540      2.25%     96.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             239      0.35%     97.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             282      0.41%     97.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              82      0.12%     97.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             291      0.43%     98.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             162      0.24%     98.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              86      0.13%     98.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              81      0.12%     98.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             117      0.17%     98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              30      0.04%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              46      0.07%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             391      0.57%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              42      0.06%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              42      0.06%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             142      0.21%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              21      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             7      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            20      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             4      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           68336                       # Writes before turning the bus around for reads
system.physmem.totQLat                    37142962355                       # Total ticks spent queuing
system.physmem.totMemAccLat               64645087355                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   7333900000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25322.79                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44072.79                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.98                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.62                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.92                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.62                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.94                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1168360                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    561939                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   79.65                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  46.67                       # Row buffer hit rate for writes
system.physmem.avgGap                     17756571.38                       # Average gap between requests
system.physmem.pageHitRate                      64.78                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3585949920                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1956619500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                5602958400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3895302960                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3100816442880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1230768339570                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27405197149500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31751822762730                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.815694                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45589938065590                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1585284480000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    299474968160                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3524827320                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1923268875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                5837886600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3907258560                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3100816442880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1224297828675                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27410873036250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31751180549160                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.802167                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45599398366763                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1585284480000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    290016828237                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   101051                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               101051                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8300                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        78014                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore            7                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       101044                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         101044    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       101044                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        86321                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22610.900013                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 19675.452020                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 23315.454382                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        84871     98.32%     98.32% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          161      0.19%     98.51% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1103      1.28%     99.78% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           41      0.05%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           57      0.07%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           25      0.03%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           42      0.05%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           13      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        86321                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1368339312                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean    -0.519630                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     2079369704    151.96%    151.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     -711030392    -51.96%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1368339312                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        78015     90.38%     90.38% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M         8300      9.62%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        86315                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       101051                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       101051                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        86315                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        86315                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       187366                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    83039604                       # DTB read hits
system.cpu0.dtb.read_misses                     74585                       # DTB read misses
system.cpu0.dtb.write_hits                   76137695                       # DTB write hits
system.cpu0.dtb.write_misses                    26466                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              42668                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   37690                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4076                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10173                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                83114189                       # DTB read accesses
system.cpu0.dtb.write_accesses               76164161                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        159177299                       # DTB hits
system.cpu0.dtb.misses                         101051                       # DTB misses
system.cpu0.dtb.accesses                    159278350                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    61250                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                61250                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          499                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        55525                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        61250                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          61250    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        61250                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        56024                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26762.682065                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 22405.547992                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 30987.782128                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        54387     97.08%     97.08% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071           41      0.07%     97.15% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607         1384      2.47%     99.62% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           41      0.07%     99.69% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           72      0.13%     99.82% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           22      0.04%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           55      0.10%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287           10      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        56024                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1978837204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1978837204    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1978837204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        55525     99.11%     99.11% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          499      0.89%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        56024                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        61250                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        61250                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        56024                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        56024                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       117274                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   441205116                       # ITB inst hits
system.cpu0.itb.inst_misses                     61250                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              42668                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   26202                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               441266366                       # ITB inst accesses
system.cpu0.itb.hits                        441205116                       # DTB hits
system.cpu0.itb.misses                          61250                       # DTB misses
system.cpu0.itb.accesses                    441266366                       # DTB accesses
system.cpu0.numCycles                     94949400739                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  440958495                       # Number of instructions committed
system.cpu0.committedOps                    519578987                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            478066113                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                531836                       # Number of float alu accesses
system.cpu0.num_func_calls                   26928397                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     66358328                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   478066113                       # number of integer instructions
system.cpu0.num_fp_insts                       531836                       # number of float instructions
system.cpu0.num_int_register_reads          691558601                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         378884875                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              853461                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             460304                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           113354931                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          113143261                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    159167445                       # number of memory refs
system.cpu0.num_load_insts                   83034076                       # Number of load instructions
system.cpu0.num_store_insts                  76133369                       # Number of store instructions
system.cpu0.num_idle_cycles              93735186324.296036                       # Number of idle cycles
system.cpu0.num_busy_cycles              1214214414.703974                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.012788                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.987212                       # Percentage of idle cycles
system.cpu0.Branches                         98314010                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                359396375     69.13%     69.13% # Class of executed instruction
system.cpu0.op_class::IntMult                 1169846      0.23%     69.36% # Class of executed instruction
system.cpu0.op_class::IntDiv                    59621      0.01%     69.37% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                 21      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.37% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             75402      0.01%     69.38% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.38% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.38% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.38% # Class of executed instruction
system.cpu0.op_class::MemRead                83034076     15.97%     85.36% # Class of executed instruction
system.cpu0.op_class::MemWrite               76133369     14.64%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 519868732                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    7168                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          5565465                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          503.695844                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          153367622                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5565977                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.554484                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       6293402000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   503.695844                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.983781                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.983781                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          429                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        323920102                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       323920102                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     77284320                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       77284320                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     71935312                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      71935312                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       189585                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       189585                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       125588                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       125588                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1730584                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1730584                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1699772                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1699772                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    149219632                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       149219632                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    149409217                       # number of overall hits
system.cpu0.dcache.overall_hits::total      149409217                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3014242                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3014242                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1370827                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1370827                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       635540                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       635540                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       782263                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       782263                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       168057                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       168057                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       197269                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       197269                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4385069                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4385069                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5020609                       # number of overall misses
system.cpu0.dcache.overall_misses::total      5020609                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  52298763500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  52298763500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33070874000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  33070874000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  65701301500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  65701301500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2847254500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2847254500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4866222000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4866222000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3481500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3481500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  85369637500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  85369637500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  85369637500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  85369637500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     80298562                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     80298562                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     73306139                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     73306139                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       825125                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       825125                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       907851                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       907851                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1898641                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1898641                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1897041                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1897041                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    153604701                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    153604701                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    154429826                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    154429826                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037538                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.037538                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018700                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018700                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.770235                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.770235                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.861665                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.861665                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088514                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088514                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.103988                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.103988                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028548                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.028548                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032511                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.032511                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17350.552311                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17350.552311                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 24124.761184                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 24124.761184                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83988.762731                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83988.762731                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16942.195208                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16942.195208                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24667.950869                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24667.950869                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19468.254091                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19468.254091                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17003.841068                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17003.841068                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      3771246                       # number of writebacks
system.cpu0.dcache.writebacks::total          3771246                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        38597                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        38597                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21414                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21414                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        46766                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        46766                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        60011                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        60011                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        60011                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        60011                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2975645                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2975645                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1349413                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1349413                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       629920                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       629920                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       782263                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       782263                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       121291                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       121291                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       197269                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       197269                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4325058                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4325058                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4954978                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4954978                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17296                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17296                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18619                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18619                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        35915                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        35915                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  46589316500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  46589316500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  30941514500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  30941514500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17872150500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17872150500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  64919038500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  64919038500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1795061500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1795061500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4668993000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4668993000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3441500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3441500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  77530831000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  77530831000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  95402981500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  95402981500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2879350000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2879350000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3091479000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3091479000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5970829000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5970829000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037057                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037057                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018408                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018408                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.763424                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.763424                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.861665                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.861665                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.063883                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.063883                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.103988                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.103988                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028157                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028157                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032086                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032086                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15656.879937                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15656.879937                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22929.610505                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22929.610505                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 28372.095663                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 28372.095663                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82988.762731                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82988.762731                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14799.626518                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14799.626518                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23668.153638                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23668.153638                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17925.963305                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17925.963305                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19253.966718                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19253.966718                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166474.907493                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166474.907493                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166038.938719                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166038.938719                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 166248.893220                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 166248.893220                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          5319178                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.824621                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          435885421                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5319690                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            81.938124                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      59948153000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.824621                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999657                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999657                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          132                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        887729927                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       887729927                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    435885421                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      435885421                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    435885421                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       435885421                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    435885421                       # number of overall hits
system.cpu0.icache.overall_hits::total      435885421                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5319695                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5319695                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5319695                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5319695                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5319695                       # number of overall misses
system.cpu0.icache.overall_misses::total      5319695                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  59521353000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  59521353000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  59521353000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  59521353000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  59521353000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  59521353000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    441205116                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    441205116                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    441205116                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    441205116                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    441205116                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    441205116                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012057                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.012057                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012057                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.012057                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012057                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.012057                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11188.865715                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11188.865715                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11188.865715                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11188.865715                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11188.865715                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11188.865715                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5319695                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      5319695                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      5319695                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      5319695                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      5319695                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      5319695                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  56861505500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  56861505500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  56861505500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  56861505500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  56861505500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  56861505500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5953877000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5953877000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   5953877000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   5953877000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.012057                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012057                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.012057                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.012057                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.012057                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.012057                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10688.865715                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10688.865715                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10688.865715                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10688.865715                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10688.865715                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10688.865715                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138060.915942                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138060.915942                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7344223                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7344239                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       976449                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2329725                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16186.065873                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          18053337                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2345760                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            7.696157                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle     55834398000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  6981.301122                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    64.056568                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    81.620115                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4075.206909                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  4054.876060                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   929.005098                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.426105                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003910                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004982                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.248731                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.247490                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.056702                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.987919                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1345                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           47                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14643                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          280                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          619                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          442                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           20                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          806                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4474                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5446                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3835                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.082092                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.002869                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.893738                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       367456425                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      367456425                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       210868                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       144785                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        355653                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      3771244                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      3771244                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        99488                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        99488                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        31647                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        31647                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       896733                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       896733                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4806679                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      4806679                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2773726                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2773726                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       232290                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       232290                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       210868                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       144785                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4806679                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3670459                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8832791                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       210868                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       144785                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4806679                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3670459                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8832791                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10391                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9054                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        19445                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       121662                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       121662                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       165610                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       165610                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           12                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total           12                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       248725                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       248725                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       513016                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       513016                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       953130                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       953130                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       548738                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       548738                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10391                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9054                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       513016                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1201855                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1734316                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10391                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9054                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       513016                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1201855                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1734316                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    495108500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    493404500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    988513000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3820404000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   3820404000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3956624500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3956624500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      3380498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      3380498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16864079500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  16864079500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  20224946500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  20224946500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  42635415000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  42635415000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  62221144000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total  62221144000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    495108500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    493404500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  20224946500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  59499494500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  80712954000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    495108500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    493404500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  20224946500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  59499494500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  80712954000                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       221259                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       153839                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       375098                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      3771244                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      3771244                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       221150                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       221150                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       197257                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       197257                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           12                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           12                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1145458                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1145458                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5319695                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      5319695                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3726856                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3726856                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       781028                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       781028                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       221259                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       153839                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5319695                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4872314                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     10567107                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       221259                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       153839                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5319695                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4872314                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     10567107                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.046963                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.058854                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.051840                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.550133                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.550133                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.839565                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.839565                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.217140                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.217140                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.096437                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.096437                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.255746                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.255746                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.702584                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.702584                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.046963                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.058854                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.096437                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.246670                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.164124                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.046963                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.058854                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.096437                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.246670                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.164124                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47647.820229                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 54495.747736                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 50836.358961                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 31401.785274                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 31401.785274                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23891.217318                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23891.217318                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 281708.166667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 281708.166667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67802.108755                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67802.108755                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39423.617392                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39423.617392                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44732.004029                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44732.004029                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 113389.530158                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 113389.530158                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47647.820229                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 54495.747736                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39423.617392                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 49506.383466                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 46538.781860                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47647.820229                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 54495.747736                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39423.617392                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 49506.383466                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 46538.781860                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1299353                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1299353                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         4520                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         4520                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          530                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          530                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5050                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         5050                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5050                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         5050                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10391                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9054                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        19445                       # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks        93813                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total        93813                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       630880                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       630880                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       121662                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       121662                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       165610                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       165610                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           12                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           12                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       244205                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       244205                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       513016                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       513016                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       952600                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       952600                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       548738                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       548738                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10391                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9054                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       513016                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1196805                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1729266                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10391                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         9054                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       513016                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1196805                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       630880                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2360146                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        17296                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        60421                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        18619                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        18619                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        35915                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        79040                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    432762500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    439080500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    871843000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  35559655965                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  35559655965                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4486256000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4486256000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3173949000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3173949000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      3140498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3140498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  14883734000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  14883734000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17146850500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17146850500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  36873595000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  36873595000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  58928716000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  58928716000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    432762500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    439080500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17146850500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  51757329000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  69776022500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    432762500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    439080500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17146850500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  51757329000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  35559655965                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 105335678465                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5630439500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2740982000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8371421500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2951836500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2951836500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   5630439500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5692818500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11323258000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.046963                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.058854                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.051840                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.550133                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.550133                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.839565                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.839565                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.213194                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.213194                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.096437                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.096437                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.255604                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.255604                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.702584                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.702584                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.046963                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.058854                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.096437                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.245634                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.163646                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.046963                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.058854                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.096437                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.245634                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.223348                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44836.358961                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56365.166062                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 36874.751360                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36874.751360                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19165.201377                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19165.201377                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 261708.166667                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261708.166667                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60947.703773                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60947.703773                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33423.617392                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33423.617392                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38708.371824                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38708.371824                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107389.530158                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107389.530158                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33423.617392                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43246.250642                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40350.080612                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33423.617392                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43246.250642                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44631.000991                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158474.907493                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138551.521822                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158538.938719                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 158538.938719                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 158508.102464                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143259.843117                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests     22509328                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11536373                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          848                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       485130                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       485124                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        537841                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      9675681                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        18620                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        18619                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      5107009                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      8757288                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       798537                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       405076                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       363715                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       481157                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           40                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           68                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1220841                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1155337                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5319695                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4658319                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       788798                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       781028                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     16044388                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17944373                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       336960                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       515556                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         34841277                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    340632980                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    559762054                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1230712                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1770072                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         903395818                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    5410368                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     27976627                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.025738                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.158355                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          27256564     97.43%     97.43% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            720057      2.57%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 6      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      27976627                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   15196832497                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    183439903                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   8022667500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   7935130422                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    183121000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    294297000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   111674                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               111674                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10360                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        85053                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore           21                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       111653                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.241821                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    61.696123                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047       111651    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::6144-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::18432-20479            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       111653                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        95434                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 21055.163778                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 19260.807562                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16557.880011                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        94629     99.16%     99.16% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          150      0.16%     99.31% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          551      0.58%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           22      0.02%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           39      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215            7      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           21      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           13      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        95434                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  10744163364                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     1.061708                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -663005280     -6.17%     -6.17% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    11407168644    106.17%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  10744163364                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        85053     89.14%     89.14% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        10360     10.86%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        95413                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       111674                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       111674                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        95413                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        95413                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       207087                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    82869257                       # DTB read hits
system.cpu1.dtb.read_misses                     83659                       # DTB read misses
system.cpu1.dtb.write_hits                   74681159                       # DTB write hits
system.cpu1.dtb.write_misses                    28015                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              42668                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   37721                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4459                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10437                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                82952916                       # DTB read accesses
system.cpu1.dtb.write_accesses               74709174                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        157550416                       # DTB hits
system.cpu1.dtb.misses                         111674                       # DTB misses
system.cpu1.dtb.accesses                    157662090                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    54727                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                54727                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          669                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        48424                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        54727                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          54727    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        54727                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        49093                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 23909.080724                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 21093.336913                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 23672.932713                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        48315     98.42%     98.42% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071           33      0.07%     98.48% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          627      1.28%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           24      0.05%     99.81% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           39      0.08%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           15      0.03%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           29      0.06%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        49093                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1309982220                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1309982220    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1309982220                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        48424     98.64%     98.64% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          669      1.36%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        49093                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        54727                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        54727                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        49093                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        49093                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       103820                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   441006552                       # ITB inst hits
system.cpu1.itb.inst_misses                     54727                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              42668                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   26047                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               441061279                       # ITB inst accesses
system.cpu1.itb.hits                        441006552                       # DTB hits
system.cpu1.itb.misses                          54727                       # DTB misses
system.cpu1.itb.accesses                    441061279                       # DTB accesses
system.cpu1.numCycles                     94949400719                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  440696565                       # Number of instructions committed
system.cpu1.committedOps                    517522363                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            474820793                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                365483                       # Number of float alu accesses
system.cpu1.num_func_calls                   25816030                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     67531060                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   474820793                       # number of integer instructions
system.cpu1.num_fp_insts                       365483                       # number of float instructions
system.cpu1.num_int_register_reads          694878928                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         377300064                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              605102                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             276864                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           116712375                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          116303175                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    157542729                       # number of memory refs
system.cpu1.num_load_insts                   82867724                       # Number of load instructions
system.cpu1.num_store_insts                  74675005                       # Number of store instructions
system.cpu1.num_idle_cycles              93871458813.181076                       # Number of idle cycles
system.cpu1.num_busy_cycles              1077941905.818921                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.011353                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.988647                       # Percentage of idle cycles
system.cpu1.Branches                         98303933                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                359137164     69.35%     69.35% # Class of executed instruction
system.cpu1.op_class::IntMult                 1056908      0.20%     69.56% # Class of executed instruction
system.cpu1.op_class::IntDiv                    59454      0.01%     69.57% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.57% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             36204      0.01%     69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.58% # Class of executed instruction
system.cpu1.op_class::MemRead                82867724     16.00%     85.58% # Class of executed instruction
system.cpu1.op_class::MemWrite               74675005     14.42%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 517832459                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   14490                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements          5147651                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          420.489425                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          152204564                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5148159                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            29.564853                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8409197794000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   420.489425                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.821268                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.821268                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          443                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        320234661                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       320234661                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     77182580                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       77182580                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     70763723                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      70763723                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       181716                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       181716                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       197136                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       197136                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1768276                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1768276                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1725683                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1725683                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    147946303                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       147946303                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    148128019                       # number of overall hits
system.cpu1.dcache.overall_hits::total      148128019                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      2911211                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      2911211                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1304261                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1304261                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       646630                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       646630                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       461157                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       461157                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       158092                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       158092                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       198973                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       198973                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4215472                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4215472                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      4862102                       # number of overall misses
system.cpu1.dcache.overall_misses::total      4862102                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  46228111000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  46228111000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  27445585000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  27445585000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  22477695000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  22477695000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2400515000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2400515000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4867748500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4867748500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2101500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2101500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  73673696000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  73673696000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  73673696000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  73673696000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     80093791                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     80093791                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     72067984                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     72067984                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       828346                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       828346                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       658293                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       658293                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1926368                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1926368                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1924656                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1924656                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    152161775                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    152161775                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    152990121                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    152990121                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036348                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.036348                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018098                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018098                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.780628                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.780628                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.700535                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.700535                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.082067                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.082067                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103381                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103381                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027704                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.027704                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031780                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.031780                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15879.340591                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15879.340591                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21043.015930                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21043.015930                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 48741.957728                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 48741.957728                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15184.291425                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15184.291425                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24464.367025                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24464.367025                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17476.974346                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17476.974346                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15152.643034                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15152.643034                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3396408                       # number of writebacks
system.cpu1.dcache.writebacks::total          3396408                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        16912                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        16912                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          462                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          462                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        41725                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        41725                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        17374                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        17374                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        17374                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        17374                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2894299                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2894299                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1303799                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1303799                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       646630                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       646630                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       461157                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       461157                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       116367                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       116367                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       198973                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       198973                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4198098                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4198098                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4844728                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4844728                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        20770                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        20770                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        19330                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        19330                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        40100                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        40100                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  41851387000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  41851387000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26109084500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26109084500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14515592000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14515592000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  22016538000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  22016538000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1587242500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1587242500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4668803500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4668803500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2073500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2073500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  67960471500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  67960471500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  82476063500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  82476063500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3614060000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3614060000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3361466500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3361466500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   6975526500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   6975526500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036136                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036136                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018091                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018091                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.780628                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.780628                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.700535                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.700535                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060407                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.060407                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103381                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103381                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027590                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027590                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031667                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031667                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14459.939004                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14459.939004                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20025.390800                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20025.390800                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22448.064581                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22448.064581                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 47741.957728                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 47741.957728                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13639.970954                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13639.970954                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23464.507747                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23464.507747                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16188.395673                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16188.395673                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17023.879050                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17023.879050                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174003.851709                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174003.851709                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173898.939472                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173898.939472                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173953.279302                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173953.279302                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          4679241                       # number of replacements
system.cpu1.icache.tags.tagsinuse          495.918258                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          436326798                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4679753                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            93.237143                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8409166313000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   495.918258                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.968590                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.968590                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1           48                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          359                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        886692857                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       886692857                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    436326798                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      436326798                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    436326798                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       436326798                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    436326798                       # number of overall hits
system.cpu1.icache.overall_hits::total      436326798                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4679754                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4679754                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4679754                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4679754                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4679754                       # number of overall misses
system.cpu1.icache.overall_misses::total      4679754                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  52951180000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  52951180000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  52951180000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  52951180000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  52951180000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  52951180000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    441006552                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    441006552                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    441006552                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    441006552                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    441006552                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    441006552                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.010612                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.010612                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.010612                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.010612                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.010612                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.010612                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11314.949461                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 11314.949461                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11314.949461                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 11314.949461                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11314.949461                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 11314.949461                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4679754                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      4679754                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      4679754                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      4679754                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      4679754                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      4679754                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  50611303500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  50611303500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  50611303500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  50611303500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  50611303500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  50611303500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14521500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14521500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14521500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     14521500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.010612                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.010612                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.010612                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.010612                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.010612                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.010612                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10814.949568                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10814.949568                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10814.949568                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10814.949568                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10814.949568                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10814.949568                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132013.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132013.636364                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7337880                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7337888                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            7                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       899040                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2034185                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13437.783654                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          16644740                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2049737                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            8.120427                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9820320151000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  6510.894270                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    71.649917                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    96.755911                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2809.884427                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3040.183540                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   908.415590                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.397393                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004373                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005906                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.171502                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.185558                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.055445                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.820177                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1547                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           77                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13928                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          214                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          697                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          636                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           36                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           25                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2599                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5864                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5395                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.094421                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004700                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.850098                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       332457854                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      332457854                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       236423                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       125548                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        361971                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3396406                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3396406                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        63344                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        63344                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        31004                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        31004                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       898756                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       898756                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4166985                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4166985                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2749875                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2749875                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       193932                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       193932                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       236423                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       125548                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4166985                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3648631                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8177587                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       236423                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       125548                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4166985                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3648631                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8177587                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9552                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7233                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        16785                       # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       123356                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       123356                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       167961                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       167961                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            8                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       219942                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       219942                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       512769                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       512769                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       907421                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       907421                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       265828                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       265828                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker         9552                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7233                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       512769                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1127363                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1656917                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker         9552                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7233                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       512769                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1127363                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1656917                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    404155000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    336372500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    740527500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3749073000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   3749073000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   4008183000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   4008183000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2030999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2030999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  12972852500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  12972852500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  18777464000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  18777464000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  34592386500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  34592386500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  20042243500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total  20042243500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    404155000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    336372500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  18777464000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  47565239000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  67083230500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    404155000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    336372500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  18777464000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  47565239000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  67083230500                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       245975                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       132781                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       378756                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3396407                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3396407                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       186700                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       186700                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       198965                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       198965                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1118698                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1118698                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4679754                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      4679754                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3657296                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3657296                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       459760                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       459760                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       245975                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       132781                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4679754                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4775994                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      9834504                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       245975                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       132781                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4679754                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4775994                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      9834504                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.038833                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.054473                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.044316                       # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.660718                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.660718                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.844174                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.844174                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.196605                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.196605                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.109572                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.109572                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.248113                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.248113                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.578189                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.578189                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.038833                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.054473                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.109572                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.236048                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.168480                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.038833                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.054473                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.109572                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.236048                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.168480                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 42311.034338                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46505.253698                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44118.409294                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30392.303577                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30392.303577                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23863.771947                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23863.771947                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 253874.875000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 253874.875000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58983.061443                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58983.061443                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36619.733252                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36619.733252                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38121.650810                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38121.650810                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 75395.532073                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 75395.532073                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 42311.034338                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46505.253698                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36619.733252                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42191.591351                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 40486.777853                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 42311.034338                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46505.253698                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36619.733252                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42191.591351                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 40486.777853                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1015409                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1015409                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         7242                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         7242                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          595                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          595                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            1                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            1                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7837                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         7837                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7837                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         7837                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker         9552                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7233                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        16785                       # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks        96130                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total        96130                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       687356                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       687356                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       123356                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       123356                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       167961                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       167961                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       212700                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       212700                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       512769                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       512769                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       906826                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       906826                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       265827                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       265827                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker         9552                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7233                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       512769                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1119526                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1649080                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker         9552                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7233                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       512769                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1119526                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       687356                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2336436                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        20770                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        20880                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        19330                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        19330                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        40100                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        40210                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    346843000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    292974500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    639817500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  44220457933                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  44220457933                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4206113500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4206113500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3161211000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3161211000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1862999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1862999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  10724509000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  10724509000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  15700856000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  15700856000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  29099850500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  29099850500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  18447195500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  18447195500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    346843000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    292974500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  15700856000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  39824359500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  56165033000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    346843000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    292974500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  15700856000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  39824359500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  44220457933                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 100385490933                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13696500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3447900000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3461596500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3216491500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3216491500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13696500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   6664391500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   6678088000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.038833                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.054473                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.044316                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.660718                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.660718                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.844174                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.844174                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.190132                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.190132                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.109572                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.109572                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.247950                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.247950                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.578186                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.578186                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.038833                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.054473                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.109572                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234407                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.167683                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.038833                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.054473                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.109572                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234407                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.237575                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38118.409294                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64334.141163                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 34097.356432                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34097.356432                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18821.101327                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18821.101327                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 232874.875000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 232874.875000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50420.822755                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50420.822755                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30619.744953                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30619.744953                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32089.784038                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32089.784038                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69395.492181                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69395.492181                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30619.744953                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35572.518637                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34058.404080                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30619.744953                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35572.518637                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42965.221788                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166003.851709                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165785.272989                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166398.939472                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166398.939472                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 166194.301746                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 166080.278538                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests     20369965                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10454543                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1008                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       477453                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       477447                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq        508237                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      8929000                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        19330                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        19330                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      4444983                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      8042862                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       852297                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       366971                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       363003                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       446864                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           48                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           68                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1185291                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1125998                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4679754                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4554667                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       467005                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       459760                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14038440                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16622497                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       296146                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       569967                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         31527050                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    299504632                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    528992733                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1062248                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1967800                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         831527413                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5090691                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     25485456                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.028305                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.165844                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          24764094     97.17%     97.17% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            721356      2.83%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 6      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      25485456                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   13733891999                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    167318993                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7019739500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7617418010                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    163365000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    323992499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40317                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40317                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136619                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136619                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47666                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231192                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231192                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353872                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47686                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155707                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496577                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36194000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           565735913                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92712000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147888000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115577                       # number of replacements
system.iocache.tags.tagsinuse               11.281807                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115593                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9206321837000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.831702                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.450105                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.239481                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.465632                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.705113                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040721                       # Number of tag accesses
system.iocache.tags.data_accesses             1040721                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8868                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8905                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8868                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8908                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8868                       # number of overall misses
system.iocache.overall_misses::total             8908                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1668103306                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1673298306                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13929903607                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13929903607                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1668103306                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1673667306                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1668103306                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1673667306                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8868                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8905                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8868                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8908                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8868                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8908                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 188103.665539                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 187905.480741                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130517.798581                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130517.798581                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 188103.665539                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 187883.622137                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 188103.665539                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 187883.622137                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         33272                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3491                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.530793                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8868                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8905                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8868                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8908                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8868                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8908                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1224703306                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1228048306                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8593503607                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8593503607                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1224703306                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1228267306                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1224703306                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1228267306                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138103.665539                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 137905.480741                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80517.798581                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80517.798581                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 138103.665539                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 137883.622137                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 138103.665539                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 137883.622137                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1400633                       # number of replacements
system.l2c.tags.tagsinuse                63705.794368                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5028924                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1460176                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.444053                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   18928.346727                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   167.390384                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   216.986390                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4428.367994                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    11717.643832                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11340.141344                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   156.822011                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   230.353384                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2614.971757                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     4665.203250                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  9239.567296                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.288824                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002554                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003311                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.067572                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.178797                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.173037                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002393                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003515                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.039901                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.071185                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.140985                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.972073                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10769                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          294                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        48480                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          265                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          409                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        10095                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          294                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1411                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5015                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        41942                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.164322                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.004486                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.739746                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 64230359                       # Number of tag accesses
system.l2c.tags.data_accesses                64230359                       # Number of data accesses
system.l2c.Writeback_hits::writebacks         2314762                       # number of Writeback hits
system.l2c.Writeback_hits::total              2314762                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           28623                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           30874                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               59497                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          6079                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          5789                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             11868                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           160432                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           145801                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               306233                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5516                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4550                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       461560                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       521601                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       265120                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         4769                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         3407                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       473807                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       524703                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       267683                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2532716                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5516                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4550                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              461560                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              682033                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       265120                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          4769                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3407                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              473807                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              670504                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       267683                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2838949                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5516                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4550                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             461560                       # number of overall hits
system.l2c.overall_hits::cpu0.data             682033                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       265120                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         4769                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3407                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             473807                       # number of overall hits
system.l2c.overall_hits::cpu1.data             670504                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       267683                       # number of overall hits
system.l2c.overall_hits::total                2838949                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         45739                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         41402                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             87141                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        10551                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        10041                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           20592                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         478288                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         167740                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             646028                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1990                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2246                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        51456                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       156048                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       188933                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1431                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1351                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        38962                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       102025                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       234272                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         778714                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1990                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2246                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             51456                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            634336                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       188933                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1431                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1351                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             38962                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            269765                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       234272                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1424742                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1990                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2246                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            51456                       # number of overall misses
system.l2c.overall_misses::cpu0.data           634336                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       188933                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1431                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1351                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            38962                       # number of overall misses
system.l2c.overall_misses::cpu1.data           269765                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       234272                       # number of overall misses
system.l2c.overall_misses::total              1424742                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    656419000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    602429500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1258848500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data    138505500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data    121106000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    259611500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  64575954000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  22241696500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  86817650500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    275343500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    312648500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6939841000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  21911323500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  30784141526                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    199825500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    189752500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5267042000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  14361628000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  39331165000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 119572711026                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    275343500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    312648500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6939841000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  86487277500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  30784141526                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    199825500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    189752500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   5267042000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  36603324500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  39331165000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    206390361526                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    275343500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    312648500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6939841000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  86487277500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  30784141526                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    199825500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    189752500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   5267042000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  36603324500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  39331165000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   206390361526                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks      2314762                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2314762                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        74362                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        72276                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          146638                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        16630                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        15830                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         32460                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       638720                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       313541                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           952261                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         7506                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6796                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       513016                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       677649                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       454053                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         6200                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         4758                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       512769                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       626728                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       501955                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3311430                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         7506                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6796                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          513016                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1316369                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       454053                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         6200                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         4758                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          512769                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          940269                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       501955                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4263691                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         7506                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6796                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         513016                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1316369                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       454053                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         6200                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         4758                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         512769                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         940269                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       501955                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4263691                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.615086                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.572832                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.594259                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.634456                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.634302                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.634381                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.748823                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.534986                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.678415                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.265121                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.330489                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.100301                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.230279                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.230806                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.283943                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.075984                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.162790                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.235159                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.265121                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.330489                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.100301                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.481883                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.230806                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.283943                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.075984                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.286902                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.334157                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.265121                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.330489                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.100301                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.481883                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.230806                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.283943                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.075984                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.286902                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.334157                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14351.406896                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14550.734264                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 14446.110327                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13127.239124                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12061.149288                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 12607.396076                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 135014.790252                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132596.259091                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 134386.823017                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138363.567839                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 139202.359751                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134869.422419                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140413.997616                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139640.461216                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140453.367876                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135184.076793                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140765.773095                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 153551.510601                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138363.567839                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 139202.359751                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 134869.422419                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 136343.006703                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139640.461216                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140453.367876                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135184.076793                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 135685.965563                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 144861.568990                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138363.567839                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 139202.359751                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 134869.422419                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 136343.006703                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139640.461216                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140453.367876                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135184.076793                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 135685.965563                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 144861.568990                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               455                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        5                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs            91                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1097098                       # number of writebacks
system.l2c.writebacks::total                  1097098                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          101                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           29                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           79                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           11                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          220                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            101                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             29                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             79                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                220                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           101                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            29                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            79                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               220                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        44502                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        44502                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        45739                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        41402                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        87141                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10551                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        10041                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        20592                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       478288                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       167740                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        646028                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1990                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         2246                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        51355                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       156019                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       188933                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1431                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1351                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        38883                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       102014                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       234272                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       778494                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1990                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2246                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        51355                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       634307                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       188933                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1431                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1351                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        38883                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       269754                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       234272                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1424522                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1990                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2246                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        51355                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       634307                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       188933                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1431                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1351                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        38883                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       269754                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       234272                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1424522                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        17296                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        20768                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        81299                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        18619                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        19330                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        37949                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        35915                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        40098                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       119248                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   3380760500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   3033576500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   6414337000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    808671000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    769117000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total   1577788000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  59793074000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  20564296500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  80357370500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    255443500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    290188500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   6414337000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  20347560500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  28894811526                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    185515500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    176242500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   4869464500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  13340357000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  36988445000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 111762365526                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    255443500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    290188500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   6414337000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  80140634500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  28894811526                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    185515500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    176242500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   4869464500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  33904653500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  36988445000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 192119736026                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    255443500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    290188500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   6414337000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  80140634500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  28894811526                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    185515500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    176242500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   4869464500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  33904653500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  36988445000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 192119736026                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   4854189000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2429636000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11716500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3074041000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  10369582500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2635303500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2887877500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5523181000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   4854189000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5064939500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11716500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5961918500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  15892763500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.615086                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.572832                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.594259                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.634456                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.634302                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.634381                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.748823                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.534986                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.678415                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.265121                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.330489                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.100104                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.230236                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.230806                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.283943                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.075829                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.162772                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.235093                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.265121                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.330489                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.100104                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.481861                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.230806                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.283943                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.075829                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.286890                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.334105                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.265121                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.330489                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.100104                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.481861                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.230806                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.283943                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.075829                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.286890                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.334105                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73914.176086                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73271.255012                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73608.714612                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76644.014785                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76597.649636                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76621.406371                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 125014.790252                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122596.259091                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 124386.823017                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124901.898549                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130417.195983                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125233.765399                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130769.864921                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143562.269621                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124901.898549                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 126343.607275                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125233.765399                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125687.305842                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 134866.106684                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124901.898549                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 126343.607275                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125233.765399                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125687.305842                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 134866.106684                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140473.866790                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148018.152928                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 127548.709086                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 141538.401633                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149398.732540                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145542.201376                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 141025.741334                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148683.687466                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 133274.885113                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               81299                       # Transaction distribution
system.membus.trans_dist::ReadResp             868698                       # Transaction distribution
system.membus.trans_dist::WriteReq              37949                       # Transaction distribution
system.membus.trans_dist::WriteResp             37949                       # Transaction distribution
system.membus.trans_dist::Writeback           1203792                       # Transaction distribution
system.membus.trans_dist::CleanEvict           220565                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           376258                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         321655                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          113911                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            660250                       # Transaction distribution
system.membus.trans_dist::ReadExResp           639853                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        787399                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122600                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24206                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5071225                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5218123                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341689                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       341689                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5559812                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155707                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        48412                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    161136300                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    161340623                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7239232                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7239232                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               168579855                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           607627                       # Total snoops (count)
system.membus.snoop_fanout::samples           3798608                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3798608    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3798608                       # Request fanout histogram
system.membus.reqLayer0.occupancy           101169498                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            20972999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8203462570                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7924808506                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          230064369                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     10304168                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      5242935                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1823032                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         155703                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       143721                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        11982                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              81301                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4203748                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             37949                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            37949                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          3518592                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1268318                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          429580                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        333523                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         763103                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           68                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           68                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1086913                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1086913                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4129694                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7476293                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6448186                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              13924479                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    230559242                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    190965829                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              421525071                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3161630                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         12055300                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.328437                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.471756                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                8107870     67.26%     67.26% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                3935448     32.64%     99.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  11982      0.10%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           12055300                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         7945670452                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2561165                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4404072117                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3899520231                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------