path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.579919                       # Number of seconds simulated
sim_ticks                                47579919171500                       # Number of ticks simulated
final_tick                               47579919171500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 994477                       # Simulator instruction rate (inst/s)
host_op_rate                                  1169790                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            52043300787                       # Simulator tick rate (ticks/s)
host_mem_usage                                 760992                       # Number of bytes of host memory used
host_seconds                                   914.24                       # Real time elapsed on the host
sim_insts                                   909188095                       # Number of instructions simulated
sim_ops                                    1069465904                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        95808                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        82560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3301172                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         14310344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     18775424                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       218368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       230464                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3000056                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         12646096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     13033600                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        427520                       # Number of bytes read from this memory
system.physmem.bytes_read::total             66121412                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3301172                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3000056                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6301228                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     84303296                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          84323880                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1497                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1290                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             91988                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            223612                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       293366                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         3412                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         3601                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             46964                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            197608                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       203650                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6680                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1073668                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1317239                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1319813                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2014                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1735                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               69382                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              300764                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       394608                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          4589                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          4844                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               63053                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              265786                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       273931                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8985                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1389692                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          69382                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          63053                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             132435                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1771825                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1772258                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1771825                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2014                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1735                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              69382                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             301197                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       394608                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         4589                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         4844                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              63053                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             265786                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       273931                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8985                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3161949                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1073668                       # Number of read requests accepted
system.physmem.writeReqs                      1319813                       # Number of write requests accepted
system.physmem.readBursts                     1073668                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1319813                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 68691008                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     23744                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  84321664                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  66121412                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               84323880                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      371                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2261                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               64017                       # Per bank write bursts
system.physmem.perBankRdBursts::1               68044                       # Per bank write bursts
system.physmem.perBankRdBursts::2               61517                       # Per bank write bursts
system.physmem.perBankRdBursts::3               65955                       # Per bank write bursts
system.physmem.perBankRdBursts::4               65874                       # Per bank write bursts
system.physmem.perBankRdBursts::5               75726                       # Per bank write bursts
system.physmem.perBankRdBursts::6               64933                       # Per bank write bursts
system.physmem.perBankRdBursts::7               65424                       # Per bank write bursts
system.physmem.perBankRdBursts::8               62003                       # Per bank write bursts
system.physmem.perBankRdBursts::9              113372                       # Per bank write bursts
system.physmem.perBankRdBursts::10              63434                       # Per bank write bursts
system.physmem.perBankRdBursts::11              64718                       # Per bank write bursts
system.physmem.perBankRdBursts::12              56904                       # Per bank write bursts
system.physmem.perBankRdBursts::13              64084                       # Per bank write bursts
system.physmem.perBankRdBursts::14              56898                       # Per bank write bursts
system.physmem.perBankRdBursts::15              60394                       # Per bank write bursts
system.physmem.perBankWrBursts::0               80527                       # Per bank write bursts
system.physmem.perBankWrBursts::1               85904                       # Per bank write bursts
system.physmem.perBankWrBursts::2               80420                       # Per bank write bursts
system.physmem.perBankWrBursts::3               86054                       # Per bank write bursts
system.physmem.perBankWrBursts::4               85401                       # Per bank write bursts
system.physmem.perBankWrBursts::5               88715                       # Per bank write bursts
system.physmem.perBankWrBursts::6               80808                       # Per bank write bursts
system.physmem.perBankWrBursts::7               81222                       # Per bank write bursts
system.physmem.perBankWrBursts::8               80522                       # Per bank write bursts
system.physmem.perBankWrBursts::9               87926                       # Per bank write bursts
system.physmem.perBankWrBursts::10              79616                       # Per bank write bursts
system.physmem.perBankWrBursts::11              81105                       # Per bank write bursts
system.physmem.perBankWrBursts::12              77689                       # Per bank write bursts
system.physmem.perBankWrBursts::13              84231                       # Per bank write bursts
system.physmem.perBankWrBursts::14              77252                       # Per bank write bursts
system.physmem.perBankWrBursts::15              80134                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         116                       # Number of times write queue was full causing retry
system.physmem.totGap                    47579915806000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1030443                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1317239                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    761963                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     94096                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     44762                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     38689                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     33193                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     29336                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     25572                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     22083                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     17610                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2659                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1054                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      617                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      470                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      330                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      233                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      201                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      153                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      138                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       78                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    42279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    54831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    58608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    65543                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    69713                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    74423                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    78144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    80302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    80268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    82803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    85991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    82780                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    84137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    91440                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    82956                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    77042                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    74792                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1528                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      878                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      781                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      492                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      412                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      401                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      374                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      302                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1107709                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      138.133954                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      95.206974                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     184.490982                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         762645     68.85%     68.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       210995     19.05%     87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        48832      4.41%     92.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        22284      2.01%     94.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        16979      1.53%     95.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        10320      0.93%     96.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         6180      0.56%     97.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5743      0.52%     97.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        23731      2.14%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1107709                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         70958                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        15.125666                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      121.252784                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          70954     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           70958                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         70958                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.567688                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.991036                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.306981                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           58539     82.50%     82.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            9965     14.04%     96.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             642      0.90%     97.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             182      0.26%     97.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             135      0.19%     97.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             121      0.17%     98.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             191      0.27%     98.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              83      0.12%     98.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             286      0.40%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              59      0.08%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              34      0.05%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              42      0.06%     99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             259      0.37%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              42      0.06%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              31      0.04%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             116      0.16%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             167      0.24%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             3      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             3      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             4      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             5      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             8      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             8      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           70958                       # Writes before turning the bus around for reads
system.physmem.totQLat                    35332291342                       # Total ticks spent queuing
system.physmem.totMemAccLat               55456610092                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5366485000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       32919.40                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  51669.40                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.44                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.77                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.39                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.77                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.40                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.48                       # Average write queue length when enqueuing
system.physmem.readRowHits                     793862                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    489250                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   73.96                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  37.13                       # Row buffer hit rate for writes
system.physmem.avgGap                     19878961.15                       # Average gap between requests
system.physmem.pageHitRate                      53.67                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 4296030480                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2344064250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4145606400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4335450480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3107688614160                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1225363115070                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27473067932250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31821240813090                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.795690                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45703113685218                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1588797860000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    288003145282                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 4078249560                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2225235375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4226055600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4202118000                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3107688614160                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1219254807825                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27478426088250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31820101168770                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.771738                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45712034121275                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1588797860000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    279086495725                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   116306                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               116306                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10885                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        88573                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           22                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       116284                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean     0.223591                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev    76.245351                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-2047       116283    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       116284                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        99480                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22519.581825                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 21136.105654                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 15840.339731                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        98726     99.24%     99.24% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          154      0.15%     99.40% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          495      0.50%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           15      0.02%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           37      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           19      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           26      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        99480                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   8374009004                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.680543                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.466266                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     2675132860     31.95%     31.95% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     5698876144     68.05%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   8374009004                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        88573     89.06%     89.06% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        10885     10.94%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        99458                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       116306                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       116306                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        99458                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        99458                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       215764                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    86290817                       # DTB read hits
system.cpu0.dtb.read_misses                     86990                       # DTB read misses
system.cpu0.dtb.write_hits                   77965379                       # DTB write hits
system.cpu0.dtb.write_misses                    29316                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              43834                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   36691                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4448                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9789                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                86377807                       # DTB read accesses
system.cpu0.dtb.write_accesses               77994695                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        164256196                       # DTB hits
system.cpu0.dtb.misses                         116306                       # DTB misses
system.cpu0.dtb.accesses                    164372502                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    53337                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                53337                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          559                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        47077                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        53337                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          53337    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        53337                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        47636                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 25421.330506                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23137.989766                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 22597.528238                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        46963     98.59%     98.59% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071           37      0.08%     98.66% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          536      1.13%     99.79% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           19      0.04%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           27      0.06%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           15      0.03%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           23      0.05%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287           11      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        47636                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1979242204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1979242204    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1979242204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        47077     98.83%     98.83% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          559      1.17%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        47636                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53337                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53337                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        47636                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        47636                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       100973                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   461259285                       # ITB inst hits
system.cpu0.itb.inst_misses                     53337                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              43834                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   25459                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               461312622                       # ITB inst accesses
system.cpu0.itb.hits                        461259285                       # DTB hits
system.cpu0.itb.misses                          53337                       # DTB misses
system.cpu0.itb.accesses                    461312622                       # DTB accesses
system.cpu0.numCycles                     95159838338                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13594                       # number of quiesce instructions executed
system.cpu0.committedInsts                  460977499                       # Number of instructions committed
system.cpu0.committedOps                    540688150                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            495872658                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                377758                       # Number of float alu accesses
system.cpu0.num_func_calls                   27096084                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     70442961                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   495872658                       # number of integer instructions
system.cpu0.num_fp_insts                       377758                       # number of float instructions
system.cpu0.num_int_register_reads          724744849                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         393986605                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              623895                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             289632                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           122670714                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          122315787                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    164249297                       # number of memory refs
system.cpu0.num_load_insts                   86287437                       # Number of load instructions
system.cpu0.num_store_insts                  77961860                       # Number of store instructions
system.cpu0.num_idle_cycles              93938070746.252213                       # Number of idle cycles
system.cpu0.num_busy_cycles              1221767591.747779                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.012839                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.987161                       # Percentage of idle cycles
system.cpu0.Branches                        102925889                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                375485543     69.40%     69.40% # Class of executed instruction
system.cpu0.op_class::IntMult                 1178634      0.22%     69.62% # Class of executed instruction
system.cpu0.op_class::IntDiv                    59866      0.01%     69.63% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.63% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             39720      0.01%     69.64% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.64% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.64% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.64% # Class of executed instruction
system.cpu0.op_class::MemRead                86287437     15.95%     85.59% # Class of executed instruction
system.cpu0.op_class::MemWrite               77961860     14.41%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 541013060                       # Class of executed instruction
system.cpu0.dcache.tags.replacements          5729731                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          475.426094                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          158277130                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5730241                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.621374                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       6293818000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   475.426094                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.928567                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.928567                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1           56                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          399                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        334208607                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       334208607                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     80244173                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       80244173                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     73488227                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      73488227                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       200421                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       200421                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       184838                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       184838                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1883304                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1883304                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1842196                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1842196                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    153732400                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       153732400                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    153932821                       # number of overall hits
system.cpu0.dcache.overall_hits::total      153932821                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3080001                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3080001                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1447988                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1447988                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       695954                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       695954                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       768699                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       768699                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       158470                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       158470                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       198134                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       198134                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4527989                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4527989                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5223943                       # number of overall misses
system.cpu0.dcache.overall_misses::total      5223943                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  52478340000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  52478340000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  38322628500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  38322628500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  49559521500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  49559521500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2516267500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2516267500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5589291500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   5589291500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2738500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2738500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  90800968500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  90800968500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  90800968500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  90800968500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     83324174                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     83324174                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     74936215                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     74936215                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       896375                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       896375                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       953537                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       953537                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2041774                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2041774                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2040330                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2040330                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    158260389                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    158260389                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    159156764                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    159156764                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036964                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036964                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.019323                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.019323                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.776409                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.776409                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.806155                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.806155                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.077614                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077614                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.097109                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.097109                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028611                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.028611                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032823                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.032823                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17038.416546                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17038.416546                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26466.122993                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 26466.122993                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 64471.947407                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 64471.947407                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15878.510128                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15878.510128                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28209.653568                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28209.653568                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20053.266141                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20053.266141                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17381.692048                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17381.692048                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      5729731                       # number of writebacks
system.cpu0.dcache.writebacks::total          5729731                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        28073                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        28073                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21239                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21239                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        41058                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        41058                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        49312                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        49312                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        49312                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        49312                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3051928                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3051928                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1426749                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1426749                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       694810                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       694810                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       768699                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       768699                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       117412                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       117412                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       198134                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       198134                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4478677                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4478677                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5173487                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5173487                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        28514                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        28514                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        27871                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27871                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        56385                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        56385                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  47315434500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  47315434500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  36384996000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  36384996000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17003029000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17003029000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  48790822500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  48790822500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1643233500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1643233500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5391195500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5391195500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2700500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2700500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83700430500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  83700430500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 100703459500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 100703459500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5280351500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5280351500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5086850000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5086850000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10367201500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10367201500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036627                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036627                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019040                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019040                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.775133                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.775133                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.806155                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.806155                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057505                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.057505                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.097109                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.097109                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028299                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028299                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032506                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032506                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15503.456995                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15503.456995                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25502.030140                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25502.030140                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24471.479973                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24471.479973                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 63471.947407                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 63471.947407                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13995.447654                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13995.447654                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27209.845357                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27209.845357                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18688.650800                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18688.650800                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19465.296714                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.296714                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185184.523392                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185184.523392                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182514.082738                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182514.082738                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183864.529573                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 183864.529573                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          4741257                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.854043                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          456517510                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          4741769                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            96.275780                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      46470060000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.854043                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999715                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999715                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          110                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          276                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        927260344                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       927260344                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    456517510                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      456517510                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    456517510                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       456517510                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    456517510                       # number of overall hits
system.cpu0.icache.overall_hits::total      456517510                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      4741775                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      4741775                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      4741775                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       4741775                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      4741775                       # number of overall misses
system.cpu0.icache.overall_misses::total      4741775                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  53890518500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  53890518500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  53890518500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  53890518500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  53890518500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  53890518500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    461259285                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    461259285                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    461259285                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    461259285                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    461259285                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    461259285                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010280                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.010280                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010280                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.010280                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010280                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.010280                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11365.051800                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11365.051800                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11365.051800                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11365.051800                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11365.051800                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11365.051800                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      4741257                       # number of writebacks
system.cpu0.icache.writebacks::total          4741257                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4741775                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      4741775                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      4741775                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      4741775                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      4741775                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      4741775                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  51519631500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  51519631500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  51519631500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  51519631500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  51519631500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  51519631500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5954209000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5954209000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   5954209000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   5954209000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010280                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010280                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010280                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010280                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010280                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010280                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10865.051906                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10865.051906                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10865.051906                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10865.051906                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10865.051906                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10865.051906                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      8039497                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      8039521                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           21                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1012143                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2514209                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16169.325614                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          14408578                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2529817                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            5.695502                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      8106870500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15164.632353                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    45.004325                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    56.118535                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   903.570401                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.925576                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002747                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003425                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.055150                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.986897                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1599                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           82                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        13927                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          253                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          682                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          664                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           42                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           30                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1           76                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2528                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5951                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         5308                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.097595                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005005                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.850037                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       356318803                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      356318803                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       276065                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       135571                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        411636                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3830429                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3830429                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      6639546                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      6639546                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          500                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total          500                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       929961                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       929961                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4274266                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      4274266                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2881532                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2881532                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       169886                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       169886                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       276065                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       135571                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4274266                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3811493                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8497395                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       276065                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       135571                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4274266                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3811493                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8497395                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10002                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7458                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        17460                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       252814                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       252814                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       198129                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       198129                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       262789                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       262789                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       467509                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       467509                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       982618                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       982618                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       596960                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       596960                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10002                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7458                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       467509                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1245407                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1730376                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10002                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7458                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       467509                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1245407                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1730376                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    427118500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    335132000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    762250500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3305201500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   3305201500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   2087626000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2087626000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2642498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2642498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  18677102500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  18677102500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  18746620500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  18746620500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  41394693000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  41394693000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    415110500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    415110500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    427118500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    335132000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  18746620500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  60071795500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  79580666500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    427118500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    335132000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  18746620500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  60071795500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  79580666500                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       286067                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       143029                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       429096                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3830429                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3830429                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      6639546                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      6639546                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       253314                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       253314                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       198129                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       198129                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1192750                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1192750                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      4741775                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      4741775                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3864150                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3864150                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       766846                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       766846                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       286067                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       143029                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      4741775                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5056900                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     10227771                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       286067                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       143029                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      4741775                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5056900                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     10227771                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.034964                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.052143                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.040690                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998026                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998026                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.220322                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.220322                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.098594                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.098594                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.254291                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.254291                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.778461                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.778461                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.034964                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.052143                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.098594                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.246279                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.169184                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.034964                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.052143                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.098594                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.246279                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.169184                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42703.309338                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44935.907750                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 43656.958763                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13073.649007                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13073.649007                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10536.700836                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10536.700836                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 528499.600000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528499.600000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 71072.619097                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 71072.619097                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40098.951036                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40098.951036                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 42126.943532                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 42126.943532                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   695.374062                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   695.374062                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42703.309338                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44935.907750                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40098.951036                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 48234.669871                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 45990.389661                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42703.309338                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44935.907750                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40098.951036                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 48234.669871                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 45990.389661                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1647047                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1647047                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         9683                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         9683                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          697                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          697                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        10380                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        10380                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        10380                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        10380                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10002                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7458                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        17460                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       803286                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       803286                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       252814                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       252814                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       198129                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       198129                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       253106                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       253106                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       467509                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       467509                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       981921                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       981921                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       596960                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       596960                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10002                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7458                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       467509                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1235027                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1719996                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10002                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7458                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       467509                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1235027                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       803286                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2523282                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        28514                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        71639                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        27871                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        27871                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        56385                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        99510                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    367106500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    290384000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    657490500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  55761183140                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  55761183140                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7610950500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7610950500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3903930000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3903930000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2414498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2414498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  15925015500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  15925015500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  15941566500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  15941566500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  35435763500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  35435763500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  42907731500                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  42907731500                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    367106500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    290384000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  15941566500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  51360779000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  67959836000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    367106500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    290384000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  15941566500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  51360779000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  55761183140                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 123721019140                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5051874500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10682646000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4877454000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4877454000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9929328500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15560100000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.034964                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.052143                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.040690                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998026                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998026                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.212204                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.212204                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.098594                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.098594                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.254110                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.254110                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.778461                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.778461                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.034964                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.052143                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.098594                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.244226                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.168169                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.034964                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.052143                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.098594                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.244226                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.246709                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37656.958763                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69416.351262                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30104.940787                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30104.940787                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19703.980740                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19703.980740                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 482899.600000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 482899.600000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62918.364243                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62918.364243                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34098.951036                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34098.951036                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36088.202106                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36088.202106                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71877.062952                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71877.062952                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34098.951036                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41586.766119                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39511.624446                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34098.951036                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41586.766119                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49031.784454                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177171.722663                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149117.743129                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175001.040508                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175001.040508                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176098.758535                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156367.199276                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests     21737448                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11172038                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1012                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops      1879362                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1879064                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          298                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        568365                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      9266330                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        27872                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        27871                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5482404                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      6640558                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2386717                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       980471                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       448075                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       360841                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       517122                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           53                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           86                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1223880                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1201425                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      4741775                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4748017                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       819035                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       766846                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     14311056                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18559366                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       302345                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       623475                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         33796242                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    607086484                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    696970881                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1144232                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2288536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1307490133                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    6577979                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     17957076                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.118626                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.323399                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          15827205     88.14%     88.14% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           2129573     11.86%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               298      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      17957076                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   21527019496                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    184192978                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   7155786000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8237151691                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    159316000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    337408998                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   108188                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               108188                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         9416                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        83328                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            4                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       108184                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.073948                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    24.322514                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-511       108183    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7680-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       108184                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        92748                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 25260.781904                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21819.891311                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 28424.827210                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        90515     97.59%     97.59% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          165      0.18%     97.77% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1735      1.87%     99.64% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           64      0.07%     99.71% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679          109      0.12%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           46      0.05%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           73      0.08%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           21      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        92748                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   -800290088                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean    -1.452962                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1963081332    245.30%    245.30% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1     1162791244   -145.30%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   -800290088                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        83329     89.85%     89.85% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         9416     10.15%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        92745                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       108188                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       108188                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        92745                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        92745                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       200933                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    84911532                       # DTB read hits
system.cpu1.dtb.read_misses                     79075                       # DTB read misses
system.cpu1.dtb.write_hits                   77663318                       # DTB write hits
system.cpu1.dtb.write_misses                    29113                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              43834                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   39584                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  5277                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10813                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                84990607                       # DTB read accesses
system.cpu1.dtb.write_accesses               77692431                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        162574850                       # DTB hits
system.cpu1.dtb.misses                         108188                       # DTB misses
system.cpu1.dtb.accesses                    162683038                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    63937                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                63937                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          631                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        57861                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        63937                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          63937    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        63937                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        58492                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 30403.747521                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24852.510144                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 37514.660324                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        55985     95.71%     95.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071           47      0.08%     95.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607         2099      3.59%     99.38% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           87      0.15%     99.53% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679          102      0.17%     99.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           51      0.09%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           79      0.14%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287           15      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823           17      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::917504-983039            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        58492                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1988115332                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1988115332    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1988115332                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        57861     98.92%     98.92% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          631      1.08%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        58492                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        63937                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        63937                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        58492                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        58492                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       122429                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   448499634                       # ITB inst hits
system.cpu1.itb.inst_misses                     63937                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              43834                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   27923                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               448563571                       # ITB inst accesses
system.cpu1.itb.hits                        448499634                       # DTB hits
system.cpu1.itb.misses                          63937                       # DTB misses
system.cpu1.itb.accesses                    448563571                       # DTB accesses
system.cpu1.numCycles                     95159838343                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    5923                       # number of quiesce instructions executed
system.cpu1.committedInsts                  448210596                       # Number of instructions committed
system.cpu1.committedOps                    528777754                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            486415785                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                519922                       # Number of float alu accesses
system.cpu1.num_func_calls                   27136019                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     67942031                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   486415785                       # number of integer instructions
system.cpu1.num_fp_insts                       519922                       # number of float instructions
system.cpu1.num_int_register_reads          706615491                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         385601488                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              832776                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             452540                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           115428294                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          115157338                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    162566757                       # number of memory refs
system.cpu1.num_load_insts                   84909557                       # Number of load instructions
system.cpu1.num_store_insts                  77657200                       # Number of store instructions
system.cpu1.num_idle_cycles              94045434394.442017                       # Number of idle cycles
system.cpu1.num_busy_cycles              1114403948.557976                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.011711                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.988289                       # Percentage of idle cycles
system.cpu1.Branches                         99989008                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                365279701     69.04%     69.04% # Class of executed instruction
system.cpu1.op_class::IntMult                 1087060      0.21%     69.25% # Class of executed instruction
system.cpu1.op_class::IntDiv                    61840      0.01%     69.26% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.26% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             71500      0.01%     69.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.27% # Class of executed instruction
system.cpu1.op_class::MemRead                84909557     16.05%     85.32% # Class of executed instruction
system.cpu1.op_class::MemWrite               77657200     14.68%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 529066901                       # Class of executed instruction
system.cpu1.dcache.tags.replacements          5332630                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          455.913081                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          157043226                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5333142                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            29.446661                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8395596843000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   455.913081                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.890455                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.890455                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          413                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           40                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        330516943                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       330516943                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     79081838                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       79081838                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     73714078                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      73714078                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       184325                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       184325                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       141992                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       141992                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1768915                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1768915                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1742986                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1742986                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    152795916                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       152795916                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    152980241                       # number of overall hits
system.cpu1.dcache.overall_hits::total      152980241                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3051137                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3051137                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1365469                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1365469                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       638330                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       638330                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       475836                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       475836                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       176856                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       176856                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       201345                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       201345                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4416606                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4416606                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      5054936                       # number of overall misses
system.cpu1.dcache.overall_misses::total      5054936                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  51930161500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  51930161500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  32223402000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  32223402000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  17094390000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  17094390000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3024227500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   3024227500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5760420500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   5760420500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      4429500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      4429500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  84153563500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  84153563500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  84153563500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  84153563500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     82132975                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     82132975                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     75079547                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     75079547                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       822655                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       822655                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       617828                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       617828                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1945771                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1945771                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1944331                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1944331                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    157212522                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    157212522                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    158035177                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    158035177                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037149                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.037149                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018187                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018187                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.775939                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.775939                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.770176                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.770176                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.090893                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.090893                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103555                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103555                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028093                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.028093                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031986                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.031986                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17019.937649                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 17019.937649                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23598.779613                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 23598.779613                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35924.961541                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35924.961541                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17099.942891                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17099.942891                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28609.702252                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28609.702252                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19053.898740                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19053.898740                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16647.799992                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16647.799992                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      5332630                       # number of writebacks
system.cpu1.dcache.writebacks::total          5332630                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        22206                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        22206                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          454                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          454                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        46550                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        46550                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        22660                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        22660                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        22660                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        22660                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3028931                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      3028931                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1365015                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1365015                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       638330                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       638330                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       475836                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       475836                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       130306                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       130306                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       201345                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       201345                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4393946                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4393946                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5032276                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5032276                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        10149                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        10149                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        10618                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        10618                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        20767                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        20767                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  46920862500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  46920862500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  30832329000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  30832329000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  15929044000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  15929044000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  16618554000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  16618554000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1916877000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1916877000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5559123500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5559123500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      4381500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      4381500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  77753191500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  77753191500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  93682235500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  93682235500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1652437500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1652437500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1820826500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1820826500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3473264000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3473264000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036878                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036878                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018181                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018181                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.775939                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.775939                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.770176                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.770176                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.066969                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066969                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103555                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103555                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027949                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027949                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031843                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031843                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15490.898439                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15490.898439                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22587.538598                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22587.538598                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24954.246236                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24954.246236                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34924.961541                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34924.961541                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14710.581247                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14710.581247                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27609.940649                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27609.940649                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17695.527323                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17695.527323                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18616.275320                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18616.275320                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162817.765297                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162817.765297                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171484.884159                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171484.884159                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167249.193432                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167249.193432                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          5368535                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.099630                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          443130586                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5369047                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            82.534309                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8395565369000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.099630                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.968945                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.968945                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          112                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        902368316                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       902368316                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    443130586                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      443130586                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    443130586                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       443130586                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    443130586                       # number of overall hits
system.cpu1.icache.overall_hits::total      443130586                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      5369048                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      5369048                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      5369048                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       5369048                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      5369048                       # number of overall misses
system.cpu1.icache.overall_misses::total      5369048                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  58701560000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  58701560000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  58701560000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  58701560000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  58701560000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  58701560000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    448499634                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    448499634                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    448499634                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    448499634                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    448499634                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    448499634                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011971                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.011971                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011971                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.011971                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011971                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.011971                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10933.327473                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10933.327473                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10933.327473                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10933.327473                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10933.327473                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10933.327473                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks      5368535                       # number of writebacks
system.cpu1.icache.writebacks::total          5368535                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5369048                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5369048                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5369048                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5369048                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5369048                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5369048                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  56017036000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  56017036000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  56017036000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  56017036000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  56017036000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  56017036000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14763500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14763500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14763500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     14763500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011971                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011971                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011971                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.011971                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011971                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.011971                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10433.327473                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10433.327473                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10433.327473                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10433.327473                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10433.327473                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10433.327473                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7379094                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7379143                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           42                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       880313                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2062305                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13347.402456                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          15756881                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2078287                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            7.581667                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    10111476094500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12484.773775                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    51.991468                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    59.953770                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   750.683443                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.762010                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003173                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003659                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.045818                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.814661                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1312                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           49                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14621                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           23                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          231                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          561                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          497                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           20                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          989                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4575                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5108                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3891                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.080078                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002991                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.892395                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       362674413                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      362674413                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       250614                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       164455                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        415069                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3362211                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3362211                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      7338042                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      7338042                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          793                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total          793                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       895753                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       895753                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4900610                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4900610                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2870677                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2870677                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       215360                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       215360                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       250614                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       164455                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4900610                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3766430                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        9082109                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       250614                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       164455                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4900610                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3766430                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       9082109                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11669                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10135                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        21804                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       207192                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       207192                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       201338                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       201338                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            7                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       263735                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       263735                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       468438                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       468438                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       926890                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       926890                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       258258                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       258258                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11669                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker        10135                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       468438                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1190625                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1680867                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11669                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker        10135                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       468438                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1190625                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1680867                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    716522000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    701084000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1417606000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3305334500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   3305334500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   2142938000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   2142938000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      4308999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      4308999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  15026168500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  15026168500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  18507593500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  18507593500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  40367140999                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  40367140999                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    516760500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    516760500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    716522000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    701084000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  18507593500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  55393309499                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  75318508999                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    716522000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    701084000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  18507593500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  55393309499                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  75318508999                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       262283                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       174590                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       436873                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3362211                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3362211                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      7338042                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      7338042                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       207985                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       207985                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       201338                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       201338                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1159488                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1159488                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5369048                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      5369048                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3797567                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3797567                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       473618                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       473618                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       262283                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       174590                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5369048                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4957055                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10762976                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       262283                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       174590                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5369048                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4957055                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10762976                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.044490                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.058050                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.049909                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.996187                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.996187                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.227458                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.227458                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.087248                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.087248                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.244075                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.244075                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.545288                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.545288                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.044490                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.058050                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.087248                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.240188                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.156171                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.044490                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.058050                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.087248                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.240188                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.156171                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 61403.890650                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 69174.543661                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 65015.868648                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15953.002529                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15953.002529                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10643.485085                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10643.485085                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 615571.285714                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 615571.285714                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56974.495232                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56974.495232                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39509.163433                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39509.163433                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43551.166804                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43551.166804                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  2000.946728                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  2000.946728                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 61403.890650                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 69174.543661                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39509.163433                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 46524.564409                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 44809.321022                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 61403.890650                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 69174.543661                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39509.163433                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 46524.564409                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 44809.321022                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1141854                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1141854                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         5992                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         5992                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          581                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          581                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         6573                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         6573                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         6573                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         6573                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11669                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10135                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        21804                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       737355                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       737355                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       207192                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       207192                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       201338                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       201338                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       257743                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       257743                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       468438                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       468438                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       926309                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       926309                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       258258                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       258258                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11669                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10135                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       468438                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1184052                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1674294                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11669                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        10135                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       468438                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1184052                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       737355                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2411649                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        10149                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        10259                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        10618                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        10618                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        20767                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        20877                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    646508000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    640274000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1286782000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  39407007921                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  39407007921                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   6717201500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   6717201500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   4047781500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   4047781500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      4020999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4020999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  12743172000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  12743172000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  15696965500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  15696965500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  34752380999                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  34752380999                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  12891073000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  12891073000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    646508000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    640274000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  15696965500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  47495552999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  64479300499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    646508000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    640274000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  15696965500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  47495552999                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  39407007921                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 103886308420                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13938500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1570752500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1584691000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1740638000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1740638000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13938500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3311390500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3325329000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.044490                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.058050                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.049909                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.996187                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.996187                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.222290                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.222290                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.087248                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.087248                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.243922                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.243922                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.545288                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.545288                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.044490                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.058050                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.087248                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.238862                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.155561                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.044490                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.058050                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.087248                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.238862                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.224069                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 59015.868648                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53443.738662                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32420.177903                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32420.177903                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20104.409004                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20104.409004                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574428.428571                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574428.428571                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49441.389291                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49441.389291                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33509.163433                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33509.163433                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37517.049925                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37517.049925                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49915.483741                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49915.483741                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33509.163433                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40112.725623                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38511.337017                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33509.163433                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40112.725623                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43076.877448                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154769.189083                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154468.369237                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163932.755698                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163932.755698                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159454.446959                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159281.937060                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests     22159802                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11360195                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          912                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops      1833001                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1832814                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          187                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq        515851                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9779420                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        10618                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        10618                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4509550                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      7338954                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      2389159                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       893791                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       389403                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       363316                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       479303                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           45                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           86                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1190307                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1167875                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5369048                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4688099                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       521676                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       473618                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     16106851                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17229570                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       365629                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       576836                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         34278886                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    687205752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    665341501                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1396720                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      2098264                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1356042237                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5987251                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     17478652                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.119213                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.324072                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          15395152     88.08%     88.08% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           2083313     11.92%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               187      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      17478652                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   21924818496                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    193282156                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   8053682000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7892863413                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    191039000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    314553499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40370                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40370                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136628                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136628                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47782                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122664                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231252                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231252                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353996                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47802                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155794                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339024                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7339024                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496904                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             37005501                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               324001                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               13000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            26468500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            37415000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           567277400                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92767000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147948000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115622                       # number of replacements
system.iocache.tags.tagsinuse               11.298154                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115638                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9192209246000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.385038                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.913116                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.461565                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.244570                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706135                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040991                       # Number of tag accesses
system.iocache.tags.data_accesses             1040991                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8898                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8935                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8898                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8938                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8898                       # number of overall misses
system.iocache.overall_misses::total             8938                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5199500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1672896003                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1678095503                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13552714897                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13552714897                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5568500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1672896003                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1678464503                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5568500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1672896003                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1678464503                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8898                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8935                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8898                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8938                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8898                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8938                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 188008.092043                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 187811.472076                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126983.686540                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126983.686540                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 188008.092043                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 187789.718393                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 188008.092043                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 187789.718393                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         33965                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3500                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.704286                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8898                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8935                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8898                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8938                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8898                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8938                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3349500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1227996003                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1231345503                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8209903918                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8209903918                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3568500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1227996003                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1231564503                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3568500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1227996003                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1231564503                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138008.092043                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 137811.472076                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76923.618151                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76923.618151                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 138008.092043                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 137789.718393                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 138008.092043                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 137789.718393                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1521682                       # number of replacements
system.l2c.tags.tagsinuse                63275.480852                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5639856                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1580939                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.567409                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              17731050500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   23300.510768                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   120.316787                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   198.572474                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3006.389178                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5620.523219                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  9896.072880                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   161.524171                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   257.856403                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3567.908148                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     7366.209685                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  9779.597138                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.355538                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001836                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003030                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.045874                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.085762                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.151002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002465                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003935                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.054442                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.112399                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.149225                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.965507                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10707                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          245                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        48305                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          130                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          740                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9837                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          245                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          121                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1549                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5150                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        41466                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.163376                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003738                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.737076                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 74056413                       # Number of tag accesses
system.l2c.tags.data_accesses                74056413                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks      2788899                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2788899                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          164206                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          131282                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              295488                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         38310                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         41053                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             79363                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            46553                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            57229                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               103782                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5034                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3536                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       418413                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       580330                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       274635                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5573                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4587                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       421326                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       539744                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       292866                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2546044                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       113687                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       125274                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           238961                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5034                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3536                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              418413                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              626883                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       274635                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5573                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4587                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              421326                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              596973                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       292866                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2649826                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5034                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3536                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             418413                       # number of overall hits
system.l2c.overall_hits::cpu0.data             626883                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       274635                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5573                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4587                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             421326                       # number of overall hits
system.l2c.overall_hits::cpu1.data             596973                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       292866                       # number of overall hits
system.l2c.overall_hits::total                2649826                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         62081                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         62914                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            124995                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        13155                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        14316                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           27471                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          85397                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          60501                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             145898                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1497                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1290                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        49096                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       140382                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       293392                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         3412                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         3601                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        47112                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       140231                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       203866                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         883879                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       471175                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       117804                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         588979                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1497                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1290                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             49096                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            225779                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       293392                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         3412                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         3601                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             47112                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            200732                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       203866                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1029777                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1497                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1290                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            49096                       # number of overall misses
system.l2c.overall_misses::cpu0.data           225779                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       293392                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         3412                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         3601                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            47112                       # number of overall misses
system.l2c.overall_misses::cpu1.data           200732                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       203866                       # number of overall misses
system.l2c.overall_misses::total              1029777                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    990526500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data   1021428000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   2011954500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data    200664500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data    227119000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    427783500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  11753356499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   8113476500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  19866832999                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    212874000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    183032000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6661915000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  19580832500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  50706713994                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    480314000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    507652000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   6389557500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  19780122000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  34128825244                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 138631838238                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data    137833000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data    159862500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total    297695500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    212874000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    183032000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6661915000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  31334188999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  50706713994                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    480314000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    507652000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   6389557500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  27893598500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  34128825244                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    158498671237                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    212874000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    183032000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6661915000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  31334188999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  50706713994                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    480314000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    507652000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   6389557500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  27893598500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  34128825244                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   158498671237                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2788899                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2788899                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       226287                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       194196                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          420483                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        51465                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        55369                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        106834                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       131950                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       117730                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           249680                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         6531                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         4826                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       467509                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       720712                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       568027                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8985                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         8188                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       468438                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       679975                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       496732                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3429923                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       584862                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       243078                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       827940                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         6531                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4826                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          467509                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          852662                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       568027                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         8985                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         8188                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          468438                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          797705                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       496732                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             3679603                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         6531                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4826                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         467509                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         852662                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       568027                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         8985                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         8188                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         468438                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         797705                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       496732                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            3679603                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.274346                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.323972                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.297265                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.255611                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.258556                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.257137                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.647192                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.513896                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.584340                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.229215                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.267302                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.105016                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.194782                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.516511                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.379744                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.439790                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.100573                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.206230                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.410414                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.257696                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.805617                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.484635                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.711379                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.229215                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.267302                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.105016                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.264793                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.516511                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.379744                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.439790                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.100573                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.251637                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.410414                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.279861                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.229215                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.267302                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.105016                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.264793                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.516511                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.379744                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.439790                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.100573                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.251637                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.410414                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.279861                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15955.388927                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16235.305337                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 16096.279851                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15253.857849                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15864.696843                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 15572.185213                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 137631.960127                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134104.832978                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 136169.330621                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142200.400802                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141885.271318                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 135691.604204                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139482.501318                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 172829.231860                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140771.981243                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140975.284643                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135624.840805                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141053.846867                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167408.127123                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 156844.815001                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   292.530376                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data  1357.020984                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   505.443318                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142200.400802                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141885.271318                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 135691.604204                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 138782.566133                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 172829.231860                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140771.981243                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140975.284643                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135624.840805                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 138959.401092                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167408.127123                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 153915.528544                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142200.400802                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141885.271318                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 135691.604204                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 138782.566133                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 172829.231860                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140771.981243                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140975.284643                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135624.840805                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 138959.401092                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167408.127123                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 153915.528544                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               442                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        7                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     63.142857                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1210545                       # number of writebacks
system.l2c.writebacks::total                  1210545                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          196                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           72                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          242                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           69                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          589                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            196                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             72                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            242                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             69                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher           10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                589                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           196                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            72                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           242                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            69                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher           10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               589                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        56231                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        56231                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        62081                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        62914                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total       124995                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        13155                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        14316                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        27471                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        85397                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        60501                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        145898                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1497                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1290                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        48900                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       140310                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       293392                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         3412                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         3601                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        46870                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       140162                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       203856                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       883290                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       471175                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       117804                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       588979                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1497                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1290                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        48900                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       225707                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       293392                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         3412                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         3601                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        46870                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       200663                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       203856                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1029188                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1497                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1290                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        48900                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       225707                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       293392                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         3412                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         3601                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        46870                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       200663                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       203856                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1029188                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        28514                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        10147                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        81896                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        27871                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        10618                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38489                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        56385                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        20765                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       120385                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   4385750000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   4455748500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   8841498500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    969977000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data   1055544500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total   2025521500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  10899069105                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   7507982381                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  18407051486                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    197889529                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    170123517                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   6149223860                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  18166902374                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  47770195366                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    446163561                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    471618547                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   5891103441                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  18366630812                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  32086715450                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 129716566457                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  32475619499                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   8166236998                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  40641856497                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    197889529                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    170123517                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   6149223860                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  29065971479                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  47770195366                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    446163561                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    471618547                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   5891103441                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  25874613193                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  32086715450                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 148123617943                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    197889529                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    170123517                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   6149223860                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  29065971479                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  47770195366                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    446163561                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    471618547                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   5891103441                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  25874613193                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  32086715450                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 148123617943                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   4854521000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4538545031                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11957000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1387996535                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  10793019566                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4403248038                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1559838113                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5963086151                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   4854521000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8941793069                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11957000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2947834648                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  16756105717                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.274346                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.323972                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.297265                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.255611                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.258556                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.257137                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.647192                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.513896                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.584340                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.229215                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.267302                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.104597                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.194682                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.516511                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.379744                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.439790                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.100056                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.206128                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.410394                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.257525                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.805617                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.484635                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.711379                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.229215                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.267302                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.104597                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.264709                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.516511                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.379744                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.439790                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.100056                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.251550                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.410394                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.279701                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.229215                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.267302                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.104597                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.264709                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.516511                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.379744                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.439790                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.100056                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.251550                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.410394                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.279701                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70645.608157                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70822.845472                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70734.817393                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73734.473584                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73731.803576                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73733.082159                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127628.243439                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124096.831143                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 126163.836968                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125750.999182                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129476.889559                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125690.280371                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131038.589718                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146856.147423                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68924.750887                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69320.540881                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69003.914396                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125750.999182                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 128777.448103                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125690.280371                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128945.611264                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 143922.799278                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125750.999182                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 128777.448103                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125690.280371                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128945.611264                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 143922.799278                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159169.005787                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst       108700                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136788.857298                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131789.337281                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157986.725916                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146905.077510                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154929.620177                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158584.607059                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst       108700                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141961.697472                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 139187.653919                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               81896                       # Transaction distribution
system.membus.trans_dist::ReadResp             974121                       # Transaction distribution
system.membus.trans_dist::WriteReq              38489                       # Transaction distribution
system.membus.trans_dist::WriteResp             38489                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1317239                       # Transaction distribution
system.membus.trans_dist::CleanEvict           246913                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           405326                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         320030                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            159351                       # Transaction distribution
system.membus.trans_dist::ReadExResp           141190                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        892225                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        691970                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122664                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26416                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4917130                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5066302                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237968                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237968                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5304270                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155794                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52832                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    143189356                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    143398186                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7255936                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7255936                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               150654122                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           585601                       # Total snoops (count)
system.membus.snoop_fanout::samples           4153558                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4153558    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4153558                       # Request fanout histogram
system.membus.reqLayer0.occupancy           101297998                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21722999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9168141817                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5620018463                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45534588                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             162                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              162                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     11339751                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      6165572                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1768705                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         157796                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       143620                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        14176                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              81898                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4275837                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38489                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38489                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      4106250                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2453030                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          692369                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        399393                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1091762                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           86                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           86                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           305771                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          305771                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4201160                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       934668                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       827940                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9127029                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7489964                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              16616993                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    227401989                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    187094309                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              414496298                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3137723                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          8291271                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.336829                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.476230                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5512705     66.49%     66.49% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                2764390     33.34%     99.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  14176      0.17%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            8291271                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8991327701                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2644911                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4134292430                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3690529810                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------