path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.403575                       # Number of seconds simulated
sim_ticks                                47403574916500                       # Number of ticks simulated
final_tick                               47403574916500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 473223                       # Simulator instruction rate (inst/s)
host_op_rate                                   556671                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            25492174892                       # Simulator tick rate (ticks/s)
host_mem_usage                                 749540                       # Number of bytes of host memory used
host_seconds                                  1859.53                       # Real time elapsed on the host
sim_insts                                   879974755                       # Number of instructions simulated
sim_ops                                    1035148021                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       121792                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       126720                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3082292                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         13718664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     15413504                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       111872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       105344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2806840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          9358928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     11301824                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        428736                       # Number of bytes read from this memory
system.physmem.bytes_read::total             56576516                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3082292                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2806840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5889132                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     75184384                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          75204968                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1903                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1980                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             88568                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            214367                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       240836                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1748                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1646                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             43945                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            146246                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       176591                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6699                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                924529                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1174756                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1177330                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2569                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2673                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               65022                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              289401                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       325155                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2360                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2222                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               59212                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              197431                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       238417                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9044                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1193507                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          65022                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          59212                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             124234                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1586049                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1586483                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1586049                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2569                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2673                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              65022                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             289836                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       325155                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2360                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2222                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              59212                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             197431                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       238417                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9044                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2779990                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        924529                       # Number of read requests accepted
system.physmem.writeReqs                      1177330                       # Number of write requests accepted
system.physmem.readBursts                      924529                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1177330                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 59142848                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     27008                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  75203008                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  56576516                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               75204968                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      422                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2259                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               51848                       # Per bank write bursts
system.physmem.perBankRdBursts::1               60547                       # Per bank write bursts
system.physmem.perBankRdBursts::2               52943                       # Per bank write bursts
system.physmem.perBankRdBursts::3               59873                       # Per bank write bursts
system.physmem.perBankRdBursts::4               53995                       # Per bank write bursts
system.physmem.perBankRdBursts::5               59394                       # Per bank write bursts
system.physmem.perBankRdBursts::6               55656                       # Per bank write bursts
system.physmem.perBankRdBursts::7               56350                       # Per bank write bursts
system.physmem.perBankRdBursts::8               47470                       # Per bank write bursts
system.physmem.perBankRdBursts::9               98045                       # Per bank write bursts
system.physmem.perBankRdBursts::10              51346                       # Per bank write bursts
system.physmem.perBankRdBursts::11              58216                       # Per bank write bursts
system.physmem.perBankRdBursts::12              52575                       # Per bank write bursts
system.physmem.perBankRdBursts::13              60842                       # Per bank write bursts
system.physmem.perBankRdBursts::14              50185                       # Per bank write bursts
system.physmem.perBankRdBursts::15              54822                       # Per bank write bursts
system.physmem.perBankWrBursts::0               69717                       # Per bank write bursts
system.physmem.perBankWrBursts::1               76530                       # Per bank write bursts
system.physmem.perBankWrBursts::2               71410                       # Per bank write bursts
system.physmem.perBankWrBursts::3               77292                       # Per bank write bursts
system.physmem.perBankWrBursts::4               71372                       # Per bank write bursts
system.physmem.perBankWrBursts::5               75019                       # Per bank write bursts
system.physmem.perBankWrBursts::6               75211                       # Per bank write bursts
system.physmem.perBankWrBursts::7               75617                       # Per bank write bursts
system.physmem.perBankWrBursts::8               67898                       # Per bank write bursts
system.physmem.perBankWrBursts::9               76939                       # Per bank write bursts
system.physmem.perBankWrBursts::10              70016                       # Per bank write bursts
system.physmem.perBankWrBursts::11              75357                       # Per bank write bursts
system.physmem.perBankWrBursts::12              71664                       # Per bank write bursts
system.physmem.perBankWrBursts::13              78615                       # Per bank write bursts
system.physmem.perBankWrBursts::14              70257                       # Per bank write bursts
system.physmem.perBankWrBursts::15              72133                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          33                       # Number of times write queue was full causing retry
system.physmem.totGap                    47403571626000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  881304                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1174756                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    659566                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     77579                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     38369                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     33211                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     28414                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     24996                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     21849                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     17731                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     15667                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2476                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1265                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      800                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      630                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      311                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      261                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      199                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      167                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       87                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       57                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    31459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    39858                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    50403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    56466                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    61622                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    64323                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    67039                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    68725                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    71220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    71835                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    75432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    77625                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    73262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    73463                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    77885                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    70974                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    65826                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    63695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      576                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      555                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      446                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      338                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      356                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      440                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      231                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       98                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       970623                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      138.411655                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      95.318742                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     185.703174                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         665453     68.56%     68.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       189210     19.49%     88.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        42199      4.35%     92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        19114      1.97%     94.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        13470      1.39%     95.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         8660      0.89%     96.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         6031      0.62%     97.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         4990      0.51%     97.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        21496      2.21%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         970623                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         60964                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        15.158028                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      130.577791                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          60961    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           60964                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         60964                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.274441                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.533375                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.742081                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           49066     80.48%     80.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            4709      7.72%     88.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            2977      4.88%     93.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31            1753      2.88%     95.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             988      1.62%     97.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             316      0.52%     98.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             174      0.29%     98.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             124      0.20%     98.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              67      0.11%     98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              44      0.07%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              37      0.06%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              48      0.08%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             425      0.70%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              48      0.08%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              48      0.08%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              40      0.07%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              26      0.04%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.00%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            10      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            27      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             3      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             6      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           60964                       # Writes before turning the bus around for reads
system.physmem.totQLat                    29056215697                       # Total ticks spent queuing
system.physmem.totMemAccLat               46383221947                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4620535000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       31442.48                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  50192.48                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.25                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.59                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.19                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.59                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.95                       # Average write queue length when enqueuing
system.physmem.readRowHits                     688543                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    439987                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.51                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  37.44                       # Row buffer hit rate for writes
system.physmem.avgGap                     22553164.43                       # Average gap between requests
system.physmem.pageHitRate                      53.76                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3707333280                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2022850500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3514687800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3837248640                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3096170747280                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1188225117900                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27399839328750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31697317314150                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.669411                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45581711195731                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1582909380000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    238953890769                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3630576600                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1980969375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3693307800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3777055920                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3096170747280                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1193695955100                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27395040340500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31697988952575                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.683580                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45573641620138                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1582909380000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    247019106112                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   114038                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               114038                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        12642                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        85549                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           19                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       114019                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean     0.228032                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev    76.998938                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-2047       114018    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       114019                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        98210                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22487.465635                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 21018.091466                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 14315.982425                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767        93486     95.19%     95.19% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535         3452      3.51%     98.70% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303          155      0.16%     98.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071          934      0.95%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839           21      0.02%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607           20      0.02%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-229375           48      0.05%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::229376-262143           12      0.01%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-294911           37      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679           30      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-360447            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        98210                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   3576910072                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.522403                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0    -1868589580    -52.24%    -52.24% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     5445499652    152.24%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   3576910072                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        85549     87.13%     87.13% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        12642     12.87%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        98191                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       114038                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       114038                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        98191                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        98191                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       212229                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    86092375                       # DTB read hits
system.cpu0.dtb.read_misses                     87013                       # DTB read misses
system.cpu0.dtb.write_hits                   77928513                       # DTB write hits
system.cpu0.dtb.write_misses                    27025                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              41066                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   38112                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4351                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9561                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                86179388                       # DTB read accesses
system.cpu0.dtb.write_accesses               77955538                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        164020888                       # DTB hits
system.cpu0.dtb.misses                         114038                       # DTB misses
system.cpu0.dtb.accesses                    164134926                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    57747                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                57747                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          561                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        51498                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        57747                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          57747    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        57747                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        52059                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 25570.833093                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23301.899076                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 19704.068320                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767        48075     92.35%     92.35% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535         2753      5.29%     97.64% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303           34      0.07%     97.70% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071         1024      1.97%     99.67% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839           15      0.03%     99.70% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607           13      0.02%     99.72% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375           43      0.08%     99.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143           19      0.04%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911           37      0.07%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679           21      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447            6      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983            6      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-491519            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        52059                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -282313796                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -282313796    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -282313796                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        51498     98.92%     98.92% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          561      1.08%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        52059                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57747                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57747                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52059                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52059                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       109806                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   458544228                       # ITB inst hits
system.cpu0.itb.inst_misses                     57747                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              41066                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   26949                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               458601975                       # ITB inst accesses
system.cpu0.itb.hits                        458544228                       # DTB hits
system.cpu0.itb.misses                          57747                       # DTB misses
system.cpu0.itb.accesses                    458601975                       # DTB accesses
system.cpu0.numPwrStateTransitions              27516                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples        13758                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    3404463734.886103                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   97180881292.374130                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3759     27.32%     27.32% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         9972     72.48%     99.80% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11           11      0.08%     99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.01%     99.91% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.91% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           12      0.09%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7033293879000                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total          13758                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   564962851937                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46838612064563                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                     94807149833                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13758                       # number of quiesce instructions executed
system.cpu0.committedInsts                  458270897                       # Number of instructions committed
system.cpu0.committedOps                    538093671                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            494447989                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                420942                       # Number of float alu accesses
system.cpu0.num_func_calls                   27507374                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     69395953                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   494447989                       # number of integer instructions
system.cpu0.num_fp_insts                       420942                       # number of float instructions
system.cpu0.num_int_register_reads          717601691                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         392303230                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              699105                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             312628                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           119518995                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          119177994                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    164010919                       # number of memory refs
system.cpu0.num_load_insts                   86087147                       # Number of load instructions
system.cpu0.num_store_insts                  77923772                       # Number of store instructions
system.cpu0.num_idle_cycles              93677224129.124023                       # Number of idle cycles
system.cpu0.num_busy_cycles              1129925703.875976                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.011918                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.988082                       # Percentage of idle cycles
system.cpu0.Branches                        102213618                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                373117768     69.30%     69.30% # Class of executed instruction
system.cpu0.op_class::IntMult                 1177948      0.22%     69.52% # Class of executed instruction
system.cpu0.op_class::IntDiv                    60910      0.01%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             42581      0.01%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::MemRead                86087147     15.99%     85.53% # Class of executed instruction
system.cpu0.op_class::MemWrite               77923772     14.47%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 538410126                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          5755741                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          471.832715                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          158017240                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5756252                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.451411                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       4031081000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   471.832715                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.921548                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.921548                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          308                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        333769183                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       333769183                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     80089936                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       80089936                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     73524451                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      73524451                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       195750                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       195750                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       158273                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       158273                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1825906                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1825906                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1807959                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1807959                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    153772660                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       153772660                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    153968410                       # number of overall hits
system.cpu0.dcache.overall_hits::total      153968410                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3122111                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3122111                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1430717                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1430717                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       657703                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       657703                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       783281                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       783281                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       173414                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       173414                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       190134                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       190134                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      5336109                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       5336109                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5993812                       # number of overall misses
system.cpu0.dcache.overall_misses::total      5993812                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  46238724000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  46238724000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  29544894000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  29544894000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25637315000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  25637315000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2487014500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2487014500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4740803500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4740803500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2810500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2810500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 101420933000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 101420933000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 101420933000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 101420933000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     83212047                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     83212047                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     74955168                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     74955168                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       853453                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       853453                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       941554                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       941554                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1999320                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1999320                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1998093                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1998093                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    159108769                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    159108769                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    159962222                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    159962222                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037520                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.037520                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.019088                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.019088                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.770638                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.770638                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.831902                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.831902                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086736                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086736                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.095158                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.095158                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.033537                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.033537                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.037470                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.037470                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14810.083306                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14810.083306                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20650.410948                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20650.410948                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32730.673922                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32730.673922                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14341.486270                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14341.486270                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24934.012328                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24934.012328                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19006.533225                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19006.533225                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16920.939963                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16920.939963                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      5755741                       # number of writebacks
system.cpu0.dcache.writebacks::total          5755741                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25545                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25545                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21233                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21233                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        44607                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        44607                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        46778                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        46778                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        46778                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        46778                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3096566                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3096566                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1409484                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1409484                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       656541                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       656541                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       783281                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       783281                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       128807                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       128807                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       190134                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       190134                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5289331                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5289331                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5945872                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5945872                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        27575                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        27575                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26540                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26540                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        54115                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        54115                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  42074729000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  42074729000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  27794776000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  27794776000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13747691500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13747691500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  24854034000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24854034000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1645535500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1645535500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4550721500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4550721500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2758500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2758500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  94723539000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  94723539000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108471230500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 108471230500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5071681500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5071681500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5071681500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5071681500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037213                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037213                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018804                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018804                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.769276                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.769276                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.831902                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.831902                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064425                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064425                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.095158                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.095158                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.033243                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.033243                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.037170                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.037170                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13587.544719                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.544719                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.823709                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.823709                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20939.578031                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20939.578031                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31730.673922                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31730.673922                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12775.202435                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12775.202435                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23934.285819                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23934.285819                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17908.415828                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.415828                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18243.115644                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18243.115644                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183923.173164                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183923.173164                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93720.437956                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93720.437956                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          4916262                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.907947                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          453627454                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          4916774                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            92.261197                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      29905343000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.907947                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999820                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999820                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        922005230                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       922005230                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    453627454                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      453627454                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    453627454                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       453627454                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    453627454                       # number of overall hits
system.cpu0.icache.overall_hits::total      453627454                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      4916774                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      4916774                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      4916774                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       4916774                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      4916774                       # number of overall misses
system.cpu0.icache.overall_misses::total      4916774                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  52276659500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  52276659500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  52276659500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  52276659500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  52276659500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  52276659500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    458544228                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    458544228                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    458544228                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    458544228                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    458544228                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    458544228                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010723                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.010723                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010723                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.010723                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010723                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.010723                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10632.308807                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10632.308807                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10632.308807                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10632.308807                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10632.308807                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10632.308807                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      4916262                       # number of writebacks
system.cpu0.icache.writebacks::total          4916262                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4916774                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      4916774                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      4916774                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      4916774                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      4916774                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      4916774                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  49818272500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  49818272500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  49818272500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  49818272500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  49818272500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  49818272500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3819470000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3819470000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3819470000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3819470000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010723                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010723                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010723                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010723                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010723                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010723                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10132.308807                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10132.308807                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10132.308807                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10132.308807                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10132.308807                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10132.308807                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7829609                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7829625                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1043159                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements         2362641                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16162.227513                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          14986861                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2378231                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.301684                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      5100393500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15129.176557                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    55.599278                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    80.860024                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   896.591654                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.923412                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003394                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004935                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.054724                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.986464                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1593                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           72                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        13925                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          258                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          732                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          603                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           40                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          191                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2612                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5888                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         5210                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.097229                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004395                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.849915                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       362405390                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      362405390                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       268274                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       147126                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        415400                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3821588                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3821588                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      6849535                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      6849535                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          548                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total          548                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       933451                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       933451                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4462897                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      4462897                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2959469                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2959469                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       207284                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       207284                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       268274                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       147126                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4462897                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3892920                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8771217                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       268274                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       147126                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4462897                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3892920                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8771217                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10042                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8210                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        18252                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       241773                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       241773                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       190127                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       190127                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            7                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       253021                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       253021                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       453877                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       453877                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       922445                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       922445                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       574180                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       574180                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10042                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8210                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       453877                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1175466                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1647595                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10042                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8210                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       453877                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1175466                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1647595                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    376993500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    339890500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    716884000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   1915432500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   1915432500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1581298000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1581298000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2680500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2680500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  12742251999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  12742251999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  15633345500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  15633345500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  32366023500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  32366023500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    286150500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    286150500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    376993500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    339890500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  15633345500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  45108275499                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  61458504999                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    376993500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    339890500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  15633345500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  45108275499                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  61458504999                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       278316                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       155336                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       433652                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3821588                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3821588                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      6849535                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      6849535                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       242321                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       242321                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       190127                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       190127                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1186472                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1186472                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      4916774                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      4916774                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3881914                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3881914                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       781464                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       781464                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       278316                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       155336                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      4916774                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5068386                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     10418812                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       278316                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       155336                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      4916774                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5068386                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     10418812                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.036081                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.052853                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.042089                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.997739                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.997739                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.213255                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.213255                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.092312                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.092312                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.237626                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.237626                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.734749                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.734749                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.036081                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.052853                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.092312                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.231921                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.158137                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.036081                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.052853                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.092312                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.231921                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.158137                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37541.674965                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41399.573691                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39277.010739                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  7922.441712                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  7922.441712                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  8317.061753                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  8317.061753                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 382928.571429                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 382928.571429                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50360.452291                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50360.452291                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34444.013466                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34444.013466                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35087.212246                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35087.212246                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   498.363754                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   498.363754                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37541.674965                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41399.573691                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34444.013466                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38374.802418                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 37301.949204                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37541.674965                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41399.573691                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34444.013466                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38374.802418                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 37301.949204                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           39736                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks      1527732                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1527732                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5839                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5839                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          307                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          307                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6146                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         6146                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6146                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         6146                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10042                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8210                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        18252                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       748015                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       748015                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       241773                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       241773                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       190127                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       190127                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       247182                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       247182                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       453877                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       453877                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       922138                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       922138                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       574180                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       574180                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10042                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8210                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       453877                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1169320                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1641449                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10042                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8210                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       453877                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1169320                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       748015                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2389464                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        27575                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        70700                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        26540                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        26540                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        54115                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        97240                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    316741500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    290630500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    607372000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  33693542276                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  33693542276                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   5018820000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   5018820000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3123659500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3123659500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2368500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2368500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10716539999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10716539999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  12910083500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  12910083500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  26808700000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  26808700000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  18844533500                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  18844533500                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    316741500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    290630500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  12910083500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  37525239999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  51042695499                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    316741500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    290630500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  12910083500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  37525239999                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  33693542276                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  84736237775                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3496032500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4850748500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8346781000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3496032500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4850748500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8346781000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.036081                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.052853                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.042089                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.997739                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.997739                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.208334                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.208334                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.092312                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092312                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.237547                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.237547                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.734749                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.734749                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.036081                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.052853                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.092312                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.230709                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.157547                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.036081                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.052853                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.092312                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.230709                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229341                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33277.010739                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45043.939327                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20758.397340                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20758.397340                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16429.331447                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16429.331447                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338357.142857                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338357.142857                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43354.855932                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43354.855932                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28444.013466                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28444.013466                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29072.329738                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29072.329738                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32819.905779                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32819.905779                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28444.013466                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32091.506174                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31096.120257                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28444.013466                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32091.506174                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35462.445877                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175911.097008                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118059.137199                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89637.780652                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85836.908680                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests     22110497                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11343995                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          879                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops      1795730                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1795410                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          320                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        572087                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      9462372                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        26540                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        26540                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5352908                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      6850414                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2268094                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       917561                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       438813                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       347856                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       497865                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           64                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          109                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1218452                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1195725                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      4916774                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4752404                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       832834                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       781464                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     14836060                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18594952                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       327877                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       607160                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         34366049                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    629486804                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    699379029                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1242688                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2226528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1332335049                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    6259200                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic            105003768                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples     17822799                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.114255                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.318177                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          15786774     88.58%     88.58% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           2035705     11.42%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               320      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      17822799                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   21920125505                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    184217084                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   7418286000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8250668056                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    172541000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    328844000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   102344                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               102344                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10188                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        77277                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore           10                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       102334                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.244298                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    78.150189                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047       102333    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       102334                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        87475                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 22637.736496                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21131.866681                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 13933.012219                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        86378     98.75%     98.75% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          960      1.10%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607           39      0.04%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           45      0.05%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           38      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        87475                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -5328755248                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.736470                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.440547                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1404285148     26.35%     26.35% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    -3924470100     73.65%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -5328755248                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        77278     88.35%     88.35% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        10188     11.65%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        87466                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       102344                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       102344                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        87466                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        87466                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       189810                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    79660508                       # DTB read hits
system.cpu1.dtb.read_misses                     74735                       # DTB read misses
system.cpu1.dtb.write_hits                   72705787                       # DTB write hits
system.cpu1.dtb.write_misses                    27609                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              41066                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   36374                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4588                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10004                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                79735243                       # DTB read accesses
system.cpu1.dtb.write_accesses               72733396                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        152366295                       # DTB hits
system.cpu1.dtb.misses                         102344                       # DTB misses
system.cpu1.dtb.accesses                    152468639                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    58593                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                58593                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          620                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        52801                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        58593                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          58593    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        58593                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        53421                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 25912.740308                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23776.245370                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18077.529945                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        47948     89.75%     89.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535         4330      8.11%     97.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303           49      0.09%     97.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071          923      1.73%     99.68% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839           30      0.06%     99.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607           25      0.05%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375           42      0.08%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143           13      0.02%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911           27      0.05%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679           20      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        53421                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1503171148                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1503171148    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1503171148                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        52801     98.84%     98.84% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          620      1.16%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        53421                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        58593                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        58593                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        53421                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        53421                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       112014                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   421982441                       # ITB inst hits
system.cpu1.itb.inst_misses                     58593                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              41066                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   25297                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               422041034                       # ITB inst accesses
system.cpu1.itb.hits                        421982441                       # DTB hits
system.cpu1.itb.misses                          58593                       # DTB misses
system.cpu1.itb.accesses                    422041034                       # DTB accesses
system.cpu1.numPwrStateTransitions               9904                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         4952                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    9471329494.171041                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   145765994017.543427                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3395     68.56%     68.56% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         1531     30.92%     99.47% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.02%     99.50% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            2      0.04%     99.54% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            3      0.06%     99.60% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            2      0.04%     99.64% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.02%     99.66% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11            1      0.02%     99.68% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11            1      0.02%     99.70% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12            1      0.02%     99.72% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           14      0.28%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 7470352176392                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           4952                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   501551261365                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 46902023655135                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                     94807149833                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    4952                       # number of quiesce instructions executed
system.cpu1.committedInsts                  421703858                       # Number of instructions committed
system.cpu1.committedOps                    497054350                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            456781482                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                475663                       # Number of float alu accesses
system.cpu1.num_func_calls                   25188507                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     64210733                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   456781482                       # number of integer instructions
system.cpu1.num_fp_insts                       475663                       # number of float instructions
system.cpu1.num_int_register_reads          664763727                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         362355133                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              757340                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             426036                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           109701618                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          109432507                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    152358964                       # number of memory refs
system.cpu1.num_load_insts                   79658830                       # Number of load instructions
system.cpu1.num_store_insts                  72700134                       # Number of store instructions
system.cpu1.num_idle_cycles              93804047310.268021                       # Number of idle cycles
system.cpu1.num_busy_cycles              1003102522.731979                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.010580                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.989420                       # Percentage of idle cycles
system.cpu1.Branches                         94064671                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                343802607     69.13%     69.13% # Class of executed instruction
system.cpu1.op_class::IntMult                 1044362      0.21%     69.34% # Class of executed instruction
system.cpu1.op_class::IntDiv                    57840      0.01%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             69226      0.01%     69.36% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.36% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.36% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.36% # Class of executed instruction
system.cpu1.op_class::MemRead                79658830     16.02%     85.38% # Class of executed instruction
system.cpu1.op_class::MemWrite               72700134     14.62%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 497333042                       # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements          5003393                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          453.941998                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          147178696                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5003905                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            29.412768                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8378733231000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   453.941998                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.886605                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.886605                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          398                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        309758535                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       309758535                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data     74209320                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       74209320                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     68941180                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      68941180                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       175621                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       175621                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       163479                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       163479                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1660182                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1660182                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1630108                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1630108                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    143313979                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       143313979                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    143489600                       # number of overall hits
system.cpu1.dcache.overall_hits::total      143489600                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      2836392                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      2836392                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1297238                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1297238                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       605603                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       605603                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       460373                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       460373                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       162387                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       162387                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       191354                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       191354                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4594003                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4594003                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      5199606                       # number of overall misses
system.cpu1.dcache.overall_misses::total      5199606                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  40714366500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  40714366500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  24361465000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  24361465000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  11037691000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  11037691000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2429522000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2429522000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4779056000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4779056000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2991500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2991500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  76113522500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  76113522500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  76113522500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  76113522500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     77045712                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     77045712                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     70238418                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     70238418                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       781224                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       781224                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       623852                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       623852                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1822569                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1822569                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1821462                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1821462                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    147907982                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    147907982                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    148689206                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    148689206                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036814                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.036814                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018469                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018469                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.775198                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.775198                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.737952                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.737952                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.089098                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.089098                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105055                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105055                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031060                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031060                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034970                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.034970                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14354.280544                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14354.280544                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18779.487650                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18779.487650                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23975.539400                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23975.539400                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14961.308479                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14961.308479                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24974.946957                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24974.946957                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16568.017587                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16568.017587                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14638.325000                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14638.325000                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      5003393                       # number of writebacks
system.cpu1.dcache.writebacks::total          5003393                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        17753                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        17753                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          420                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          420                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44380                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44380                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        18173                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        18173                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        18173                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        18173                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2818639                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2818639                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1296818                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1296818                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       605603                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       605603                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       460373                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       460373                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       118007                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       118007                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       191354                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       191354                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4575830                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4575830                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5181433                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5181433                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        11021                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        11021                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11924                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11924                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        22945                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        22945                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  36912397500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  36912397500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23044975500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23044975500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12992134000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12992134000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  10577318000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  10577318000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1572635000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1572635000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4587759000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4587759000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2934500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2934500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  70534691000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  70534691000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  83526825000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  83526825000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1888408000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1888408000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1888408000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1888408000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036584                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036584                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018463                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018463                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.775198                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.775198                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.737952                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.737952                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064748                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064748                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105055                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105055                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030937                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.030937                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034847                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.034847                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13095.823020                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13095.823020                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17770.400704                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17770.400704                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21453.219353                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21453.219353                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22975.539400                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22975.539400                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13326.624692                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13326.624692                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23975.244834                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23975.244834                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15414.622265                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15414.622265                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16120.410126                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16120.410126                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171346.338808                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171346.338808                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82301.503596                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82301.503596                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements          5018955                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.221127                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          416962969                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5019467                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            83.069172                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8378705112000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.221127                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969182                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969182                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          131                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        848984354                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       848984354                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst    416962969                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      416962969                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    416962969                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       416962969                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    416962969                       # number of overall hits
system.cpu1.icache.overall_hits::total      416962969                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      5019472                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      5019472                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      5019472                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       5019472                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      5019472                       # number of overall misses
system.cpu1.icache.overall_misses::total      5019472                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  53186343000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  53186343000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  53186343000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  53186343000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  53186343000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  53186343000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    421982441                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    421982441                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    421982441                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    421982441                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    421982441                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    421982441                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011895                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.011895                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011895                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.011895                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011895                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.011895                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10596.003524                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10596.003524                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10596.003524                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10596.003524                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10596.003524                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10596.003524                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      5018955                       # number of writebacks
system.cpu1.icache.writebacks::total          5018955                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5019472                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5019472                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5019472                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5019472                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5019472                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5019472                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  50676607000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  50676607000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  50676607000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  50676607000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  50676607000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  50676607000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10226000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10226000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10226000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10226000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011895                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011895                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011895                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.011895                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011895                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.011895                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10096.003524                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10096.003524                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10096.003524                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10096.003524                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10096.003524                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10096.003524                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92963.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92963.636364                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued      6881080                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      6881096                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       855832                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements         1952199                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13310.052713                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          14647404                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         1968271                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            7.441762                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9691338413500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12374.908537                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    46.710351                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    42.105943                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   846.327882                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.755304                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002851                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.002570                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.051656                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.812381                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1315                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           51                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14706                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           28                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          206                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          560                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          521                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           20                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           22                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          976                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4506                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5198                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3947                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.080261                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003113                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.897583                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       339868675                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      339868675                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       236019                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       150274                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        386293                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3171050                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3171050                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      6850339                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      6850339                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          404                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total          404                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       839001                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       839001                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4555671                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4555671                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2665864                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2665864                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       201941                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       201941                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       236019                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       150274                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4555671                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3504865                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8446829                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       236019                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       150274                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4555671                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3504865                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8446829                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10494                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9148                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        19642                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       207236                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       207236                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       191347                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       191347                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            7                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       252464                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       252464                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       463801                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       463801                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       876385                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       876385                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       256334                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       256334                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10494                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9148                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       463801                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1128849                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1612292                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10494                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9148                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       463801                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1128849                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1612292                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    383427500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    341472000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    724899500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   1893664000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   1893664000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1540982500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1540982500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2848499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2848499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10062122499                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10062122499                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  15777836000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  15777836000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  28794953500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  28794953500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    441282000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    441282000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    383427500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    341472000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  15777836000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  38857075999                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  55359811499                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    383427500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    341472000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  15777836000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  38857075999                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  55359811499                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       246513                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       159422                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       405935                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3171050                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3171050                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      6850339                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      6850339                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       207640                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       207640                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       191347                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       191347                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1091465                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1091465                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5019472                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      5019472                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3542249                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3542249                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       458275                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       458275                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       246513                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       159422                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5019472                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4633714                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10059121                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       246513                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       159422                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5019472                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4633714                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10059121                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.042570                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.057382                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.048387                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.998054                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.998054                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.231307                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.231307                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.092400                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.092400                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.247409                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.247409                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.559345                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.559345                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.042570                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.057382                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.092400                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.243616                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.160282                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.042570                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.057382                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.092400                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.243616                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.160282                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36537.783495                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37327.503279                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36905.584971                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  9137.717385                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  9137.717385                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  8053.340267                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  8053.340267                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 406928.428571                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 406928.428571                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39855.672488                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39855.672488                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34018.546747                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34018.546747                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32856.511122                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32856.511122                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1721.511778                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1721.511778                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36537.783495                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37327.503279                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34018.546747                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34421.854472                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 34336.095136                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36537.783495                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37327.503279                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34018.546747                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34421.854472                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 34336.095136                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches           40910                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks      1077285                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1077285                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         4355                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         4355                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          371                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          371                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4726                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         4726                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4726                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         4726                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10494                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9148                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        19642                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       670250                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       670250                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       207236                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       207236                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       191347                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       191347                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       248109                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       248109                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       463801                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       463801                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       876014                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       876014                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       256334                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       256334                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10494                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9148                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       463801                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1124123                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1607566                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10494                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9148                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       463801                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1124123                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       670250                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2277816                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        11021                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        11131                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11924                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11924                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        22945                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        23055                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    320463500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    286584000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    607047500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  26432385766                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  26432385766                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4355093500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4355093500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3151504000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3151504000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2506499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2506499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8136910999                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8136910999                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  12995030000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  12995030000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  23494652500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  23494652500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6984949000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6984949000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    320463500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    286584000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  12995030000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  31631563499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  45233640999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    320463500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    286584000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  12995030000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  31631563499                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  26432385766                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  71666026765                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9401000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1799706000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1809107000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9401000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1799706000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1809107000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.042570                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.057382                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.048387                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.998054                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.998054                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.227317                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.227317                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.092400                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092400                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.247304                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.247304                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.559345                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.559345                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.042570                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.057382                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.092400                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.242597                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.159812                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.042570                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.057382                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.092400                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.242597                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.226443                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30905.584971                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39436.606887                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21015.139744                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21015.139744                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16470.098826                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16470.098826                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 358071.285714                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 358071.285714                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32795.710752                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32795.710752                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28018.546747                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28018.546747                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26819.950937                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26819.950937                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27249.405073                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27249.405073                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28018.546747                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28138.881154                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28137.968207                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28018.546747                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28138.881154                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31462.605744                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163297.885854                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162528.703621                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78435.650469                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78469.182390                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests     20762161                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10650842                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          958                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops      1727817                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1727605                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          212                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq        482395                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9130479                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        11924                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11924                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4254476                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      6851297                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      2274133                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       818827                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       384823                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       346834                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       460171                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           59                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          109                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1120311                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1099104                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5019472                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4398430                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       506547                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       458275                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15058119                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16186537                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       334443                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       542756                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         32121855                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    642459768                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    622853650                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1275376                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1972104                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1268560898                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5663025                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic             75880456                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples     16447181                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.119069                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.323910                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          14489040     88.09%     88.09% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           1957929     11.90%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               212      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      16447181                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   20541870997                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    171936035                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7529318000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7396555908                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    175021499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    296243499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40346                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40346                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136621                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136621                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47682                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122616                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231238                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231238                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47702                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155723                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338968                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338968                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496777                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36887001                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               320000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            26455501                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            37419000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569241095                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92726000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147934000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115616                       # number of replacements
system.iocache.tags.tagsinuse               11.233110                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115632                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9095552544000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.412176                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.820935                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.463261                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.238808                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.702069                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040928                       # Number of tag accesses
system.iocache.tags.data_accesses             1040928                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8891                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8928                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115619                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115659                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115619                       # number of overall misses
system.iocache.overall_misses::total           115659                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5198000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1628324544                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1633522544                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12891433551                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12891433551                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5567000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  14519758095                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  14525325095                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5567000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  14519758095                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  14525325095                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8891                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8928                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115619                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115659                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115619                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115659                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 183143.014734                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 182966.234767                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120787.736592                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120787.736592                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139175                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125582.802956                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125587.503739                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139175                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125582.802956                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125587.503739                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         31812                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3498                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.094340                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106695                       # number of writebacks
system.iocache.writebacks::total               106695                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8891                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8928                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115619                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115659                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115619                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115659                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1183774544                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1187122544                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7546042407                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7546042407                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3567000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   8729816951                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8733383951                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3567000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   8729816951                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8733383951                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133143.014734                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 132966.234767                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70703.493057                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70703.493057                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89175                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75505.037675                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75509.765353                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89175                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75505.037675                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75509.765353                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1334376                       # number of replacements
system.l2c.tags.tagsinuse                63294.471519                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5390543                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1393372                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.868703                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               9808893500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   22223.163606                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   261.500257                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   456.360455                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3501.846073                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    10429.068271                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16721.904383                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    41.820782                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker    49.581814                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3191.520948                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3798.713740                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2618.991189                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.339099                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003990                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.006964                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.053434                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.159135                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.255156                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000638                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000757                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.048699                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.057964                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.039963                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.965797                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10362                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          274                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        48360                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          240                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          245                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9869                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          274                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1630                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5501                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        41094                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.158112                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.004181                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.737915                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 69824789                       # Number of tag accesses
system.l2c.tags.data_accesses                69824789                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks      2605015                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2605015                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          157240                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          131498                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              288738                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         36551                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         35663                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             72214                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            46670                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            57995                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               104665                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         4832                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3674                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       408343                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       539971                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       281420                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5997                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5496                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       419901                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       530515                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       275271                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2475420                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       117433                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       122622                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           240055                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker          4832                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3674                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              408343                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              586641                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       281420                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5997                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5496                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              419901                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              588510                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       275271                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2580085                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         4832                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3674                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             408343                       # number of overall hits
system.l2c.overall_hits::cpu0.data             586641                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       281420                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5997                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5496                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             419901                       # number of overall hits
system.l2c.overall_hits::cpu1.data             588510                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       275271                       # number of overall hits
system.l2c.overall_hits::total                2580085                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         61532                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         60685                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            122217                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        12602                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        13049                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           25651                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          81623                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          50736                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             132359                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1903                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1980                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        45534                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       135010                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       240877                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1748                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1646                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        43900                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        98157                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       176782                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         747537                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       445868                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       117477                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         563345                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1903                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1980                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             45534                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            216633                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       240877                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1748                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1646                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             43900                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            148893                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       176782                       # number of demand (read+write) misses
system.l2c.demand_misses::total                879896                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1903                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1980                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            45534                       # number of overall misses
system.l2c.overall_misses::cpu0.data           216633                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       240877                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1748                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1646                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            43900                       # number of overall misses
system.l2c.overall_misses::cpu1.data           148893                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       176782                       # number of overall misses
system.l2c.overall_misses::total               879896                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    390440000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    373608000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    764048000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     65654000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     76676500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    142330500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   7135565500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4240679000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  11376244500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    166331500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    176995000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   3903055500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  11953058500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  28580004804                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    157717000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    151093000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3757434500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data   9007178500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  21390253127                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  79243121431                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data     55722000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data     43983500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total     99705500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    166331500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    176995000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   3903055500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  19088624000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  28580004804                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    157717000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    151093000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3757434500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  13247857500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  21390253127                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     90619365931                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    166331500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    176995000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   3903055500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  19088624000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  28580004804                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    157717000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    151093000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3757434500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  13247857500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  21390253127                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    90619365931                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2605015                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2605015                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       218772                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       192183                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          410955                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        49153                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        48712                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         97865                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       128293                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       108731                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           237024                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         6735                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         5654                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       453877                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       674981                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       522297                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         7745                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7142                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       463801                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       628672                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       452053                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3222957                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       563301                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       240099                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       803400                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         6735                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         5654                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          453877                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          803274                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       522297                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         7745                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7142                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          463801                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          737403                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       452053                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             3459981                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         6735                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         5654                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         453877                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         803274                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       522297                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         7745                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7142                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         463801                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         737403                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       452053                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            3459981                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.281261                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.315767                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.297398                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.256383                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.267881                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.262106                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.636223                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.466619                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.558420                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.282554                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.350195                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.100322                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.200020                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.225694                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.230468                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.094653                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.156134                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.231941                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.791527                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.489286                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.701201                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.282554                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.350195                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.100322                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.269688                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.225694                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.230468                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.094653                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.201915                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.254307                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.282554                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.350195                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.100322                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.269688                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.225694                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.230468                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.094653                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.201915                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.254307                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6345.316258                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6156.513142                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6251.568931                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5209.807967                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5876.044141                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5548.731044                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87421.014910                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83583.234784                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 85949.912737                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87404.887020                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89391.414141                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85717.387008                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88534.615954                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90227.116705                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 91794.046173                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85590.763098                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91762.976660                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 106005.617690                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   124.974208                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   374.400947                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   176.988346                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87404.887020                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89391.414141                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 85717.387008                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 88115.033259                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90227.116705                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 91794.046173                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 85590.763098                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 88975.690597                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 102988.723589                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87404.887020                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89391.414141                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 85717.387008                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 88115.033259                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90227.116705                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 91794.046173                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 85590.763098                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 88975.690597                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 102988.723589                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               494                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        9                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     54.888889                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1068061                       # number of writebacks
system.l2c.writebacks::total                  1068061                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           54                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           19                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           49                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           43                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          165                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             54                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             19                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             49                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             43                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                165                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            54                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            19                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            49                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            43                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               165                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        48108                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        48108                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        61532                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        60685                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total       122217                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        12602                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        13049                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        25651                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        81623                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        50736                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        132359                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1903                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1980                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        45480                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       134991                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       240877                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1748                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1646                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        43851                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        98114                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       176782                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       747372                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       445868                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       117477                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       563345                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1903                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1980                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        45480                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       216614                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       240877                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1748                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1646                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        43851                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       148850                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       176782                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           879731                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1903                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1980                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        45480                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       216614                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       240877                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1748                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1646                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        43851                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       148850                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       176782                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          879731                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        27575                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        11019                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        81829                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        26540                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11924                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38464                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        54115                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        22943                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       120293                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1338948000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1324584000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   2663532000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    312012000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    323877000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    635889000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6319298576                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3733266108                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  10052564684                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    147301500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    157194002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   3443824526                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  10601706692                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  26171043713                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    140235503                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    134631004                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3315499572                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   8022481292                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  19622178672                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  71756096476                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   8904054000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2392104000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  11296158000                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    147301500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    157194002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   3443824526                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  16921005268                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  26171043713                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    140235503                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    134631004                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   3315499572                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  11755747400                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  19622178672                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  81808661160                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    147301500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    157194002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   3443824526                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  16921005268                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  26171043713                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    140235503                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    134631004                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   3315499572                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  11755747400                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  19622178672                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  81808661160                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2719782000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4354335503                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7420500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1601314002                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8682852005                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2719782000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4354335503                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7420500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1601314002                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   8682852005                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.281261                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.315767                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.297398                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.256383                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.267881                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.262106                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.636223                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.466619                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.558420                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.282554                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.350195                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.100203                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.199992                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.225694                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.230468                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.094547                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.156065                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.231890                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.791527                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.489286                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.701201                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.282554                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.350195                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.100203                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.269664                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.225694                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.230468                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.094547                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.201857                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.254259                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.282554                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.350195                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.100203                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.269664                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.225694                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.230468                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.094547                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.201857                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.254259                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21760.189820                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21827.206064                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21793.465721                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24758.927154                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24820.062840                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24790.027679                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77420.562538                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73582.192289                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 75949.234159                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75721.735400                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78536.396441                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75608.300198                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81766.937359                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96011.218611                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19970.157087                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20362.317730                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20051.936203                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75721.735400                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78115.935572                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75608.300198                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78977.140746                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 92992.813894                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75721.735400                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78115.935572                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75608.300198                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78977.140746                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 92992.813894                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157908.812439                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145322.987748                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106109.716665                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80464.483101                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69795.318921                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 72180.858446                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       3668271                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2217535                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3152                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               81829                       # Transaction distribution
system.membus.trans_dist::ReadResp             838129                       # Transaction distribution
system.membus.trans_dist::WriteReq              38464                       # Transaction distribution
system.membus.trans_dist::WriteResp             38464                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1174756                       # Transaction distribution
system.membus.trans_dist::CleanEvict           216961                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           398327                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         309165                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              22                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq            145872                       # Transaction distribution
system.membus.trans_dist::ReadExResp           127949                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        756300                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        666856                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122616                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26280                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4403166                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4552154                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237974                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237974                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4790128                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155723                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52560                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    124524268                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    124732755                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7257216                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7257216                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               131989971                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           572885                       # Total snoops (count)
system.membus.snoopTraffic                     188480                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2396814                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.013654                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.116050                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2364088     98.63%     98.63% # Request fanout histogram
system.membus.snoop_fanout::1                   32726      1.37%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2396814                       # Request fanout histogram
system.membus.reqLayer0.occupancy           101168498                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21745999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8211058586                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         4830240380                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45484396                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     10770571                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      5860830                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1720391                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         132185                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       120739                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        11446                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              81831                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4048119                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38464                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38464                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      3673076                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2310912                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          679438                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        381379                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1060817                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          109                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          109                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           291982                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          291982                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      3967045                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       832947                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       803400                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8640930                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7144066                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              15784996                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    212830169                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    175839034                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              388669203                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2716758                       # Total snoops (count)
system.toL2Bus.snoopTraffic                 119453392                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples          7607581                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.354994                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.481646                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                4918380     64.65%     64.65% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                2677755     35.20%     99.85% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  11446      0.15%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            7607581                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8483488339                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2591888                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3918166834                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3514899349                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------