path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.460623                       # Number of seconds simulated
sim_ticks                                47460623015500                       # Number of ticks simulated
final_tick                               47460623015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 557401                       # Simulator instruction rate (inst/s)
host_op_rate                                   655644                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            30226773681                       # Simulator tick rate (ticks/s)
host_mem_usage                                 730476                       # Number of bytes of host memory used
host_seconds                                  1570.15                       # Real time elapsed on the host
sim_insts                                   875204273                       # Number of instructions simulated
sim_ops                                    1029460892                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        81920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        78144                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3183732                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         11874696                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     12415040                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       115712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       117120                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2511992                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          9752208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     13330752                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        455552                       # Number of bytes read from this memory
system.physmem.bytes_read::total             53916868                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3183732                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2511992                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5695724                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     73320768                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          73341352                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1280                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1221                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             90153                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            185555                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       193985                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1808                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1830                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             39338                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            152391                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       208293                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           7118                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                882972                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1145637                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1148211                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1726                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1647                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               67082                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              250201                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       261586                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2438                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2468                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               52928                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              205480                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       280880                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9599                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1136034                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          67082                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          52928                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             120009                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1544876                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1545310                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1544876                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1726                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1647                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              67082                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             250635                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       261586                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2438                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2468                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              52928                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             205480                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       280880                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9599                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2681343                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        882972                       # Number of read requests accepted
system.physmem.writeReqs                      1148211                       # Number of write requests accepted
system.physmem.readBursts                      882972                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1148211                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 56486656                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     23552                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  73339968                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  53916868                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               73341352                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      368                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2256                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               53897                       # Per bank write bursts
system.physmem.perBankRdBursts::1               57581                       # Per bank write bursts
system.physmem.perBankRdBursts::2               50596                       # Per bank write bursts
system.physmem.perBankRdBursts::3               56941                       # Per bank write bursts
system.physmem.perBankRdBursts::4               52224                       # Per bank write bursts
system.physmem.perBankRdBursts::5               57867                       # Per bank write bursts
system.physmem.perBankRdBursts::6               48622                       # Per bank write bursts
system.physmem.perBankRdBursts::7               53589                       # Per bank write bursts
system.physmem.perBankRdBursts::8               50057                       # Per bank write bursts
system.physmem.perBankRdBursts::9               95322                       # Per bank write bursts
system.physmem.perBankRdBursts::10              46946                       # Per bank write bursts
system.physmem.perBankRdBursts::11              52908                       # Per bank write bursts
system.physmem.perBankRdBursts::12              47194                       # Per bank write bursts
system.physmem.perBankRdBursts::13              52526                       # Per bank write bursts
system.physmem.perBankRdBursts::14              52237                       # Per bank write bursts
system.physmem.perBankRdBursts::15              54097                       # Per bank write bursts
system.physmem.perBankWrBursts::0               68696                       # Per bank write bursts
system.physmem.perBankWrBursts::1               73430                       # Per bank write bursts
system.physmem.perBankWrBursts::2               69832                       # Per bank write bursts
system.physmem.perBankWrBursts::3               74009                       # Per bank write bursts
system.physmem.perBankWrBursts::4               72053                       # Per bank write bursts
system.physmem.perBankWrBursts::5               74820                       # Per bank write bursts
system.physmem.perBankWrBursts::6               69700                       # Per bank write bursts
system.physmem.perBankWrBursts::7               72497                       # Per bank write bursts
system.physmem.perBankWrBursts::8               69824                       # Per bank write bursts
system.physmem.perBankWrBursts::9               74930                       # Per bank write bursts
system.physmem.perBankWrBursts::10              66965                       # Per bank write bursts
system.physmem.perBankWrBursts::11              71787                       # Per bank write bursts
system.physmem.perBankWrBursts::12              69900                       # Per bank write bursts
system.physmem.perBankWrBursts::13              73092                       # Per bank write bursts
system.physmem.perBankWrBursts::14              71437                       # Per bank write bursts
system.physmem.perBankWrBursts::15              72965                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          49                       # Number of times write queue was full causing retry
system.physmem.totGap                    47460619650000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  839747                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1145637                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    632223                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     71339                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     35282                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     31150                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     27029                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     24072                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     21057                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     18521                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     14779                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2467                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1357                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      874                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      674                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      507                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      376                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      293                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      241                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      190                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      100                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    33201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    39474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    49559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    52179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    57658                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    60584                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    63950                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    67460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    69091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    68874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    71191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    73992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    71007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    71950                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    78189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    71162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    66652                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    64454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1565                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      916                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      789                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      640                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      509                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      414                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      311                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      363                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      316                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      272                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      377                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      141                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       939668                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      138.161751                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      95.082106                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     185.728908                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         647019     68.86%     68.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       180648     19.22%     88.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        40379      4.30%     92.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        17830      1.90%     94.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        14299      1.52%     95.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         8441      0.90%     96.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         5223      0.56%     97.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         4905      0.52%     97.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        20924      2.23%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         939668                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         60779                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        14.521496                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      130.920998                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          60776    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           60779                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         60779                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.854160                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.212866                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.632019                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           48749     80.21%     80.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            9610     15.81%     96.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             589      0.97%     96.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             189      0.31%     97.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             137      0.23%     97.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             124      0.20%     97.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             218      0.36%     98.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              91      0.15%     98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             270      0.44%     98.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              61      0.10%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              30      0.05%     98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              50      0.08%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             255      0.42%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              52      0.09%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              24      0.04%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              99      0.16%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             170      0.28%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             3      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            22      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            13      0.02%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           60779                       # Writes before turning the bus around for reads
system.physmem.totQLat                    27990688881                       # Total ticks spent queuing
system.physmem.totMemAccLat               44539513881                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4413020000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       31713.76                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  50463.76                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.19                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.55                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.14                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.55                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.60                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.42                       # Average write queue length when enqueuing
system.physmem.readRowHits                     659544                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    429323                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.73                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  37.46                       # Row buffer hit rate for writes
system.physmem.avgGap                     23365998.85                       # Average gap between requests
system.physmem.pageHitRate                      53.68                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3575759040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1951059000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3364272600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3726194400                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3099896966400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1199863250505                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27423860344500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31736237846445                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.685699                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45621402632571                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1584814400000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    254405603429                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3528047880                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1925026125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3519999600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3699373680                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3099896966400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1198418138910                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27425127986250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31736115538845                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.683122                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45623502554973                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1584814400000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    252305273527                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   102194                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               102194                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9208                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        76624                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore            9                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       102185                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean     0.254440                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev    81.335431                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-2047       102184    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       102185                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        85841                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22586.042800                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 20965.618936                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16893.735669                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        85046     99.07%     99.07% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          170      0.20%     99.27% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          522      0.61%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           25      0.03%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           28      0.03%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           14      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           28      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        85841                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   4536625496                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.282786                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.450353                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     3253731032     71.72%     71.72% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     1282894464     28.28%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   4536625496                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        76625     89.27%     89.27% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M         9208     10.73%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        85833                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       102194                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       102194                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85833                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85833                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       188027                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    85563003                       # DTB read hits
system.cpu0.dtb.read_misses                     75756                       # DTB read misses
system.cpu0.dtb.write_hits                   77475573                       # DTB write hits
system.cpu0.dtb.write_misses                    26438                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              40703                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1030                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   34001                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4044                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     8915                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                85638759                       # DTB read accesses
system.cpu0.dtb.write_accesses               77502011                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        163038576                       # DTB hits
system.cpu0.dtb.misses                         102194                       # DTB misses
system.cpu0.dtb.accesses                    163140770                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    56381                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                56381                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          642                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        50009                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        56381                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          56381    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        56381                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        50651                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 25304.495469                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23033.115990                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 21560.503846                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        49913     98.54%     98.54% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071           55      0.11%     98.65% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          593      1.17%     99.82% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           11      0.02%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           28      0.06%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           13      0.03%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           34      0.07%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        50651                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1979242204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1979242204    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1979242204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        50009     98.73%     98.73% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          642      1.27%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        50651                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        56381                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        56381                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        50651                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        50651                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       107032                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   455204971                       # ITB inst hits
system.cpu0.itb.inst_misses                     56381                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              40703                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1030                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   24108                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               455261352                       # ITB inst accesses
system.cpu0.itb.hits                        455204971                       # DTB hits
system.cpu0.itb.misses                          56381                       # DTB misses
system.cpu0.itb.accesses                    455261352                       # DTB accesses
system.cpu0.numCycles                     94921246031                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13214                       # number of quiesce instructions executed
system.cpu0.committedInsts                  454926589                       # Number of instructions committed
system.cpu0.committedOps                    534313943                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            491049300                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                395385                       # Number of float alu accesses
system.cpu0.num_func_calls                   27308099                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     68959046                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   491049300                       # number of integer instructions
system.cpu0.num_fp_insts                       395385                       # number of float instructions
system.cpu0.num_int_register_reads          709557386                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         389375063                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              654866                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             293356                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           117980325                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          117652107                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    163029477                       # number of memory refs
system.cpu0.num_load_insts                   85557806                       # Number of load instructions
system.cpu0.num_store_insts                  77471671                       # Number of store instructions
system.cpu0.num_idle_cycles              93727706914.782028                       # Number of idle cycles
system.cpu0.num_busy_cycles              1193539116.217975                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.012574                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.987426                       # Percentage of idle cycles
system.cpu0.Branches                        101606994                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                370328410     69.27%     69.27% # Class of executed instruction
system.cpu0.op_class::IntMult                 1177627      0.22%     69.49% # Class of executed instruction
system.cpu0.op_class::IntDiv                    60510      0.01%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             39424      0.01%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::MemRead                85557806     16.00%     85.51% # Class of executed instruction
system.cpu0.op_class::MemWrite               77471671     14.49%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 534635449                       # Class of executed instruction
system.cpu0.dcache.tags.replacements          5459134                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          479.881862                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          157334556                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5459646                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.817721                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       6293818000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   479.881862                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.937269                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.937269                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          412                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           41                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        331496751                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       331496751                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     79723477                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       79723477                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     73152105                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      73152105                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       199556                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       199556                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       181390                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       181390                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1847375                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1847375                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1814831                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1814831                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    152875582                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       152875582                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    153075138                       # number of overall hits
system.cpu0.dcache.overall_hits::total      153075138                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2983943                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      2983943                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1350734                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1350734                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       619590                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       619590                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       750130                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       750130                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       159632                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       159632                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       191006                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       191006                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4334677                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4334677                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4954267                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4954267                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  47916762500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  47916762500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  34952130000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  34952130000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  46124909500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  46124909500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2449383000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2449383000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5329904000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   5329904000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5776000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5776000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  82868892500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  82868892500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  82868892500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  82868892500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     82707420                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     82707420                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     74502839                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     74502839                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       819146                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       819146                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       931520                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       931520                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2007007                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2007007                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2005837                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2005837                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    157210259                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    157210259                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    158029405                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    158029405                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036078                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036078                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018130                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018130                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.756385                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.756385                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.805275                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.805275                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.079537                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079537                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.095225                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.095225                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027572                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.027572                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031350                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.031350                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16058.203022                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16058.203022                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25876.397573                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 25876.397573                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61489.221202                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61489.221202                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15343.934800                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15343.934800                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27904.379967                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27904.379967                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19117.662631                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19117.662631                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16726.771589                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16726.771589                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      5459134                       # number of writebacks
system.cpu0.dcache.writebacks::total          5459134                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        24235                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        24235                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21402                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21402                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        43300                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        43300                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        45637                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        45637                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        45637                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        45637                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2959708                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2959708                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1329332                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1329332                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       618446                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       618446                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       750130                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       750130                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       116332                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       116332                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       191006                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       191006                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4289040                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4289040                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4907486                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4907486                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29450                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29450                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28924                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28924                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        58374                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58374                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43283569500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  43283569500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  33090463000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33090463000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14878889500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14878889500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  45374779500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  45374779500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1623777500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1623777500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5138961000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5138961000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5713000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5713000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  76374032500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  76374032500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  91252922000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  91252922000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5439516500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5439516500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5307758000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5307758000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10747274500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10747274500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035785                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035785                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017843                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017843                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.754989                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.754989                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.805275                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.805275                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057963                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.057963                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.095225                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.095225                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027282                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027282                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031054                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.031054                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14624.270198                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14624.270198                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24892.549792                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24892.549792                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24058.510363                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24058.510363                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60489.221202                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60489.221202                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13958.132758                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13958.132758                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26904.709800                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26904.709800                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17806.789515                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17806.789515                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18594.637254                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18594.637254                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184703.446520                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184703.446520                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 183507.052966                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183507.052966                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184110.640011                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184110.640011                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          5000286                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.853700                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          450204172                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5000798                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            90.026466                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      46470060000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.853700                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999714                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999714                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          336                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          116                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        915410741                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       915410741                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    450204172                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      450204172                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    450204172                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       450204172                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    450204172                       # number of overall hits
system.cpu0.icache.overall_hits::total      450204172                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5000799                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5000799                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5000799                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5000799                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5000799                       # number of overall misses
system.cpu0.icache.overall_misses::total      5000799                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  55488072500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  55488072500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  55488072500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  55488072500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  55488072500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  55488072500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    455204971                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    455204971                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    455204971                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    455204971                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    455204971                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    455204971                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010986                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.010986                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010986                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.010986                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010986                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.010986                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11095.841385                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11095.841385                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11095.841385                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11095.841385                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11095.841385                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11095.841385                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      5000286                       # number of writebacks
system.cpu0.icache.writebacks::total          5000286                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5000799                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      5000799                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      5000799                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      5000799                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      5000799                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      5000799                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  52987673000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  52987673000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  52987673000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  52987673000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  52987673000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  52987673000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5954209000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5954209000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   5954209000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   5954209000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010986                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010986                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010986                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010986                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010986                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010986                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10595.841385                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10595.841385                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10595.841385                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10595.841385                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10595.841385                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10595.841385                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7383328                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7383330                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            1                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       974782                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2298690                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16186.717586                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          14759696                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2314768                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.376318                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      8106870500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15157.672211                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    53.142846                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    76.415973                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   899.486557                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.925151                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003244                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004664                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.054900                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.987959                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1325                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           54                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14699                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           20                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          193                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          683                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          429                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           36                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           15                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1043                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4210                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6256                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3119                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.080872                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003296                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.897156                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       354680611                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      354680611                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       235924                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       143301                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        379225                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3602563                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3602563                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      6855894                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      6855894                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          389                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total          389                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       855344                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       855344                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4541852                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      4541852                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2786021                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2786021                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       182713                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       182713                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       235924                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       143301                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4541852                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3641365                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8562442                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       235924                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       143301                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4541852                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3641365                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8562442                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker         9735                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7677                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        17412                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       241880                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       241880                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       190989                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       190989                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           17                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total           17                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       251163                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       251163                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       458947                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       458947                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       908465                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       908465                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       565429                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       565429                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker         9735                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7677                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       458947                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1159628                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1635987                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker         9735                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7677                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       458947                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1159628                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1635987                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    390278500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    327424000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    717702500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3214093500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   3214093500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1890945000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1890945000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      5616997                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      5616997                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16356012499                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  16356012499                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  18207706500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  18207706500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  36093910000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  36093910000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    390401000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    390401000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    390278500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    327424000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  18207706500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  52449922499                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  71375331499                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    390278500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    327424000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  18207706500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  52449922499                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  71375331499                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       245659                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       150978                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       396637                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3602563                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3602563                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      6855894                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      6855894                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       242269                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       242269                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       190989                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       190989                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           17                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           17                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1106507                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1106507                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5000799                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      5000799                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3694486                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3694486                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       748142                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       748142                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       245659                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       150978                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5000799                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4800993                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     10198429                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       245659                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       150978                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5000799                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4800993                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     10198429                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.039628                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.050848                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.043899                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998394                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998394                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.226987                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.226987                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.091775                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.091775                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.245898                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.245898                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.755778                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.755778                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.039628                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.050848                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.091775                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.241539                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.160416                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.039628                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.050848                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.091775                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.241539                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.160416                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40090.241397                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42649.993487                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41218.843326                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13287.967174                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13287.967174                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9900.805806                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9900.805806                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 330411.588235                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 330411.588235                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65121.106608                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65121.106608                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39672.786836                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39672.786836                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39730.655556                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39730.655556                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   690.450967                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   690.450967                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40090.241397                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42649.993487                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39672.786836                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45229.955209                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 43628.299919                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40090.241397                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42649.993487                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39672.786836                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45229.955209                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 43628.299919                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1473434                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1473434                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5831                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5831                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          658                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          658                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6489                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         6489                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6489                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         6489                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker         9735                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7677                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        17412                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       676944                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       676944                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       241880                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       241880                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       190989                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       190989                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           17                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           17                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       245332                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       245332                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       458947                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       458947                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       907807                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       907807                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       565429                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       565429                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker         9735                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7677                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       458947                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1153139                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1629498                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker         9735                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7677                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       458947                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1153139                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       676944                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2306442                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        29450                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        72575                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28924                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28924                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        58374                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       101499                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    331868500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    281362000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    613230500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  37650647602                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  37650647602                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7335732000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7335732000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3705379500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3705379500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      5238997                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5238997                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  14201538999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  14201538999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  15454024500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  15454024500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  30580591000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  30580591000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  39622342000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  39622342000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    331868500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    281362000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  15454024500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  44782129999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  60849384999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    331868500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    281362000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  15454024500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  44782129999                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  37650647602                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  98500032601                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5203415000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10834186500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5090437000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5090437000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10293852000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15924623500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.039628                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.050848                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.043899                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998394                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998394                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.221718                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.221718                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.091775                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.091775                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.245719                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.245719                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.755778                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.755778                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.039628                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.050848                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.091775                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240188                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.159779                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.039628                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.050848                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.091775                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240188                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.226157                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35218.843326                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55618.555748                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30327.980817                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30327.980817                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19401.010006                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19401.010006                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 308176.294118                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 308176.294118                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57887.022480                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57887.022480                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33672.786836                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33672.786836                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33686.225156                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33686.225156                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70074.831676                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70074.831676                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33672.786836                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38834.979997                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37342.411589                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33672.786836                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38834.979997                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42706.485834                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176686.417657                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149282.624871                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175993.534781                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175993.534781                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176343.097955                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156894.388122                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests     21678176                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11128402                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          962                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops      1759585                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1759287                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          298                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        537700                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      9321471                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28925                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28924                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5081322                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      6856856                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2248329                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       834929                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       427184                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       348871                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       496915                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           88                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          134                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1135852                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1114697                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5000799                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4556956                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       799366                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       748142                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     15088134                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17701155                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       319339                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       542421                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         33651049                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    640241940                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    663021135                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1207824                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1965272                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1306436171                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    6076867                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     17397758                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.114750                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.318774                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          15401663     88.53%     88.53% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           1995797     11.47%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               298      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      17397758                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   21478508994                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    177190009                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   7544323500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   7836374127                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    168361000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    296762000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   108457                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               108457                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         9827                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        84631                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore           22                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       108435                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.073777                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    24.294348                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-511       108434    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7680-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       108435                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        94480                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23264.092930                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21359.678554                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 19330.218287                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        93351     98.81%     98.81% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          176      0.19%     98.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          798      0.84%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           40      0.04%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           45      0.05%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           27      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           24      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        94480                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   3353012192                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     1.550742                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1846644332    -55.07%    -55.07% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1     5199656524    155.07%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   3353012192                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        84631     89.60%     89.60% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         9827     10.40%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        94458                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       108457                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       108457                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        94458                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        94458                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       202915                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    79507348                       # DTB read hits
system.cpu1.dtb.read_misses                     80723                       # DTB read misses
system.cpu1.dtb.write_hits                   72319570                       # DTB write hits
system.cpu1.dtb.write_misses                    27734                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              40703                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1030                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   39844                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4607                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10580                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                79588071                       # DTB read accesses
system.cpu1.dtb.write_accesses               72347304                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        151826918                       # DTB hits
system.cpu1.dtb.misses                         108457                       # DTB misses
system.cpu1.dtb.accesses                    151935375                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    59789                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                59789                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          555                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        54230                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        59789                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          59789    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        59789                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        54785                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 26806.178699                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23797.611376                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 25937.791406                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        53612     97.86%     97.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071           36      0.07%     97.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          992      1.81%     99.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           28      0.05%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           57      0.10%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           10      0.02%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           37      0.07%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            4      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        54785                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1988115332                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1988115332    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1988115332                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        54230     98.99%     98.99% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          555      1.01%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        54785                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        59789                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        59789                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        54785                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        54785                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       114574                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   420546617                       # ITB inst hits
system.cpu1.itb.inst_misses                     59789                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              40703                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1030                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   27682                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               420606406                       # ITB inst accesses
system.cpu1.itb.hits                        420546617                       # DTB hits
system.cpu1.itb.misses                          59789                       # DTB misses
system.cpu1.itb.accesses                    420606406                       # DTB accesses
system.cpu1.numCycles                     94920662633                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    5531                       # number of quiesce instructions executed
system.cpu1.committedInsts                  420277684                       # Number of instructions committed
system.cpu1.committedOps                    495146949                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            454880180                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                506575                       # Number of float alu accesses
system.cpu1.num_func_calls                   25039229                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     63957319                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   454880180                       # number of integer instructions
system.cpu1.num_fp_insts                       506575                       # number of float instructions
system.cpu1.num_int_register_reads          664278142                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         361063382                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              809640                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             450820                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           110083158                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          109779727                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    151817768                       # number of memory refs
system.cpu1.num_load_insts                   79504880                       # Number of load instructions
system.cpu1.num_store_insts                  72312888                       # Number of store instructions
system.cpu1.num_idle_cycles              93883487625.302155                       # Number of idle cycles
system.cpu1.num_busy_cycles              1037175007.697842                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.010927                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.989073                       # Percentage of idle cycles
system.cpu1.Branches                         93646526                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                342430715     69.12%     69.12% # Class of executed instruction
system.cpu1.op_class::IntMult                 1035788      0.21%     69.33% # Class of executed instruction
system.cpu1.op_class::IntDiv                    58966      0.01%     69.34% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.34% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             72713      0.01%     69.36% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.36% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.36% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.36% # Class of executed instruction
system.cpu1.op_class::MemRead                79504880     16.05%     85.40% # Class of executed instruction
system.cpu1.op_class::MemWrite               72312888     14.60%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 495415992                       # Class of executed instruction
system.cpu1.dcache.tags.replacements          5111729                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          453.815972                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          146515734                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5112105                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            28.660549                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8395596843000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   453.815972                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.886359                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.886359                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          376                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          373                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.734375                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        308802786                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       308802786                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     74029008                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       74029008                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     68561672                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      68561672                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       171099                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       171099                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       145458                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       145458                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1631683                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1631683                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1602426                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1602426                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    142590680                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       142590680                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    142761779                       # number of overall hits
system.cpu1.dcache.overall_hits::total      142761779                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      2875045                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      2875045                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1313230                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1313230                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       626301                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       626301                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       483495                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       483495                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       165519                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       165519                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       193387                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       193387                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4188275                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4188275                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      4814576                       # number of overall misses
system.cpu1.dcache.overall_misses::total      4814576                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  45279528500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  45279528500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  30099423000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  30099423000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  18095848000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  18095848000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2729020500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2729020500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5550193500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   5550193500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      6333000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      6333000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  75378951500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  75378951500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  75378951500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  75378951500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     76904053                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     76904053                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     69874902                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     69874902                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       797400                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       797400                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       628953                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       628953                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1797202                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1797202                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1795813                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1795813                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    146778955                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    146778955                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    147576355                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    147576355                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037385                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.037385                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018794                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018794                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.785429                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.785429                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.768730                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.768730                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.092098                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.092098                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.107688                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.107688                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028535                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.028535                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.032624                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.032624                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15749.154709                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15749.154709                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22920.145748                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22920.145748                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37427.166775                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37427.166775                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16487.657006                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16487.657006                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28699.930709                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28699.930709                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17997.612740                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17997.612740                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15656.404946                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15656.404946                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      5111729                       # number of writebacks
system.cpu1.dcache.writebacks::total          5111729                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        16692                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        16692                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          402                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          402                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44979                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44979                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        17094                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        17094                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        17094                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        17094                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2858353                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2858353                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1312828                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1312828                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       626301                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       626301                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       483495                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       483495                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       120540                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       120540                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       193387                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       193387                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4171181                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4171181                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4797482                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4797482                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         8711                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         8711                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         9093                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         9093                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        17804                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        17804                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  40977017000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  40977017000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  28757951500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  28757951500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14279978500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14279978500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  17612353000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  17612353000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1713373500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1713373500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5356877500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5356877500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      6262000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      6262000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  69734968500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  69734968500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  84014947000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  84014947000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1460511000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1460511000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1571513500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1571513500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3032024500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3032024500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037168                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037168                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018788                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018788                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.785429                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.785429                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.768730                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.768730                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067071                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067071                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.107688                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.107688                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028418                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.028418                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032508                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.032508                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14335.883986                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14335.883986                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21905.345940                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21905.345940                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22800.504071                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22800.504071                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36427.166775                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36427.166775                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14214.148830                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14214.148830                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27700.297848                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27700.297848                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16718.279188                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16718.279188                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17512.300619                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17512.300619                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167662.840087                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167662.840087                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172826.734851                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172826.734851                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170300.185352                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170300.185352                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          4920276                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.059748                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          415625824                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4920788                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            84.463266                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8395565369000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.059748                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.968867                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.968867                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          403                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          109                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        846014027                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       846014027                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    415625824                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      415625824                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    415625824                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       415625824                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    415625824                       # number of overall hits
system.cpu1.icache.overall_hits::total      415625824                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4920793                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4920793                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4920793                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4920793                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4920793                       # number of overall misses
system.cpu1.icache.overall_misses::total      4920793                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  53750624000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  53750624000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  53750624000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  53750624000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  53750624000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  53750624000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    420546617                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    420546617                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    420546617                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    420546617                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    420546617                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    420546617                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011701                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.011701                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011701                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.011701                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011701                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.011701                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10923.162994                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10923.162994                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10923.162994                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10923.162994                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10923.162994                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10923.162994                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks      4920276                       # number of writebacks
system.cpu1.icache.writebacks::total          4920276                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4920793                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      4920793                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      4920793                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      4920793                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      4920793                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      4920793                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  51290227500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  51290227500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  51290227500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  51290227500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  51290227500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  51290227500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14763500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14763500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14763500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     14763500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011701                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011701                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011701                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.011701                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011701                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.011701                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10423.162994                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10423.162994                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10423.162994                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10423.162994                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10423.162994                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10423.162994                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7108517                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7108606                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           78                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       877146                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         1947890                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13258.686630                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          14658232                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         1963173                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            7.466602                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    10431898029000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12337.010876                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    64.483445                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    73.799198                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   783.393111                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.752991                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003936                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004504                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.047815                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.809246                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1528                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           68                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13687                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           43                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          698                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          787                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           39                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           29                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          680                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6525                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         6482                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.093262                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004150                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.835388                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       340572805                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      340572805                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       256581                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       155471                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        412052                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3259472                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3259472                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      6771640                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      6771640                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          476                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total          476                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       874528                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       874528                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4470558                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4470558                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2746836                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2746836                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       216255                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       216255                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       256581                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       155471                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4470558                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3621364                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8503974                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       256581                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       155471                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4470558                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3621364                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8503974                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9634                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8009                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        17643                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       195149                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       195149                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       193373                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       193373                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           14                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total           14                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       244689                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       244689                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       450235                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       450235                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       858358                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       858358                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       265386                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       265386                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker         9634                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8009                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       450235                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1103047                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1570925                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker         9634                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8009                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       450235                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1103047                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1570925                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    459999000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    417305500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    877304500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3163875000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   3163875000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   2039332500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   2039332500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      6154498                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      6154498                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  13641270998                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  13641270998                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  17048494000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  17048494000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  33667115000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  33667115000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    534332000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    534332000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    459999000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    417305500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  17048494000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  47308385998                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  65234184498                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    459999000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    417305500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  17048494000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  47308385998                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  65234184498                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       266215                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       163480                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       429695                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3259472                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3259472                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      6771640                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      6771640                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       195625                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       195625                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       193373                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       193373                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           14                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           14                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1119217                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1119217                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4920793                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      4920793                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3605194                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3605194                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       481641                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       481641                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       266215                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       163480                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4920793                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4724411                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10074899                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       266215                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       163480                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4920793                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4724411                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10074899                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.036189                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.048991                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.041059                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.997567                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.997567                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.218625                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.218625                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.091496                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.091496                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.238089                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.238089                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.551004                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.551004                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.036189                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.048991                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.091496                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.233478                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.155925                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.036189                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.048991                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.091496                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.233478                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.155925                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 47747.456923                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 52104.569859                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 49725.358499                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16212.611902                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16212.611902                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10546.107781                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10546.107781                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       439607                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       439607                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 55749.424772                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 55749.424772                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37865.767877                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37865.767877                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39222.696124                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39222.696124                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  2013.414423                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  2013.414423                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 47747.456923                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 52104.569859                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37865.767877                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42888.821599                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 41525.970048                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 47747.456923                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 52104.569859                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37865.767877                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42888.821599                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 41525.970048                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1103180                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1103180                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         6962                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         6962                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          454                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          454                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            1                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            1                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7416                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         7416                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7416                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         7416                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker         9634                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8009                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        17643                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       688811                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       688811                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       195149                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       195149                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       193373                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       193373                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           14                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           14                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       237727                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       237727                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       450235                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       450235                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       857904                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       857904                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       265385                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       265385                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker         9634                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8009                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       450235                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1095631                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1563509                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker         9634                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8009                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       450235                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1095631                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       688811                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2252320                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         8711                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         8821                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         9093                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         9093                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        17804                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        17914                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    402195000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    369251500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    771446500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  40532964082                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  40532964082                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   6306578500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   6306578500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3905504500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3905504500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      5728498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5728498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  11332534498                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  11332534498                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  14347084000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  14347084000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  28473868000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  28473868000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  13840214500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  13840214500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    402195000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    369251500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  14347084000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  39806402498                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  54924932998                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    402195000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    369251500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  14347084000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  39806402498                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  40532964082                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  95457897080                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13938500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1390451500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1404390000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1502902000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1502902000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13938500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2893353500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2907292000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.036189                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.048991                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.041059                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.997567                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.997567                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.212405                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.212405                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.091496                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.091496                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.237963                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.237963                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.551002                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.551002                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.036189                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.048991                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.091496                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.231908                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.155189                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.036189                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.048991                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.091496                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.231908                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.223558                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 43725.358499                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58844.826929                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32316.734905                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32316.734905                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20196.741531                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20196.741531                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 409178.428571                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409178.428571                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47670.371889                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47670.371889                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31865.767877                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31865.767877                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33190.039911                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.039911                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 52151.457317                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 52151.457317                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31865.767877                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36331.942504                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35129.272040                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31865.767877                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36331.942504                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42382.031452                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159620.192860                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159209.840154                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165281.205323                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165281.205323                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162511.430016                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162291.615496                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests     20782124                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10655468                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          892                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops      1707466                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1707307                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          159                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq        502417                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9121363                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         9093                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         9093                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4367100                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      6772532                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      2206652                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       838220                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       373270                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       349428                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       455882                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           77                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          134                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1149239                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1127446                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4920793                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4454860                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       528061                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       481641                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14762082                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16505656                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       342155                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       581136                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         32191029                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    629828856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    636046096                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1307840                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      2129720                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1269312512                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5644464                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     16439738                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.118176                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.322847                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          14497112     88.18%     88.18% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           1942467     11.82%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               159      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      16439738                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   20566237996                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    185505924                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7381299500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7535601373                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    178675000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    314921000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40334                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40334                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136621                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136621                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47682                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122616                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231214                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231214                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353910                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47702                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155723                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338872                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338872                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496681                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36912500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               323000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               13000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            26561500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            37416000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           567387857                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92726000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147910000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115602                       # number of replacements
system.iocache.tags.tagsinuse               11.206206                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115618                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9192082489000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.403530                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.802676                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.462721                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.237667                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.700388                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040820                       # Number of tag accesses
system.iocache.tags.data_accesses             1040820                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8879                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8916                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8879                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8919                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8879                       # number of overall misses
system.iocache.overall_misses::total             8919                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5198000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1680349949                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1685547949                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13547011908                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13547011908                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5567000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1680349949                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1685916949                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5567000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1680349949                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1685916949                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8879                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8916                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8879                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8919                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8879                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8919                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 189249.909787                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 189047.549237                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126930.251743                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126930.251743                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139175                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 189249.909787                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 189025.333445                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139175                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 189249.909787                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 189025.333445                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         33462                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3547                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.433888                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106693                       # number of writebacks
system.iocache.writebacks::total               106693                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8879                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8916                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8879                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8919                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8879                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8919                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1236399949                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1239747949                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8204144644                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8204144644                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3567000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1236399949                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1239966949                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3567000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1236399949                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1239966949                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139249.909787                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 139047.549237                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76869.655985                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76869.655985                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89175                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 139249.909787                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 139025.333445                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89175                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 139249.909787                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 139025.333445                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1288575                       # number of replacements
system.l2c.tags.tagsinuse                63334.482670                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5304464                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1347256                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.937235                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              17731050500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   24026.415823                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   182.847205                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   272.174490                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3917.360352                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     7074.037074                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11678.333096                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   109.068959                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   171.850259                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3448.642027                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     6022.848319                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  6430.905066                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.366614                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002790                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.004153                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.059774                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.107941                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.178197                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001664                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.002622                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.052622                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.091901                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.098128                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.966408                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022         9960                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          230                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        48491                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2           46                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          303                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9611                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          230                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          185                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1722                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5705                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        40867                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.151978                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003510                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.739914                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 68640564                       # Number of tag accesses
system.l2c.tags.data_accesses                68640564                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks      2576614                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2576614                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          159474                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          125945                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              285419                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         36876                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         37537                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             74413                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            50046                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            51540                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               101586                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5134                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3916                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       411784                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       545243                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       276625                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5262                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4295                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       410923                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       516914                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       270635                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2450731                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       123087                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       119603                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           242690                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5134                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3916                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              411784                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              595289                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       276625                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5262                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4295                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              410923                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              568454                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       270635                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2552317                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5134                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3916                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             411784                       # number of overall hits
system.l2c.overall_hits::cpu0.data             595289                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       276625                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5262                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4295                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             410923                       # number of overall hits
system.l2c.overall_hits::cpu1.data             568454                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       270635                       # number of overall hits
system.l2c.overall_hits::total                2552317                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         60660                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         57967                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            118627                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        11966                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        14089                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           26055                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          73366                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          52915                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             126281                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1280                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1221                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        47163                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       114217                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       194151                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1808                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1830                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        39312                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       102014                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       208359                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         711355                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       431001                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       129981                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         560982                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1280                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1221                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             47163                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            187583                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       194151                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1808                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1830                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             39312                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            154929                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       208359                       # number of demand (read+write) misses
system.l2c.demand_misses::total                837636                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1280                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1221                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            47163                       # number of overall misses
system.l2c.overall_misses::cpu0.data           187583                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       194151                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1808                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1830                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            39312                       # number of overall misses
system.l2c.overall_misses::cpu1.data           154929                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       208359                       # number of overall misses
system.l2c.overall_misses::total               837636                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    923139500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    911457500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1834597000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data    172867000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data    183172000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    356039000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  10023511500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   7102572500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  17126084000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    179763500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    168992000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6377154500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  15730524500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  32714560984                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    254502500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    255185000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5294694000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  14274314499                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  35606994761                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 110856686244                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data    147802000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data    150755500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total    298557500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    179763500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    168992000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6377154500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  25754036000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  32714560984                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    254502500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    255185000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   5294694000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  21376886999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  35606994761                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    127982770244                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    179763500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    168992000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6377154500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  25754036000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  32714560984                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    254502500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    255185000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   5294694000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  21376886999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  35606994761                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   127982770244                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2576614                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2576614                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       220134                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       183912                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          404046                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        48842                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        51626                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        100468                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       123412                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       104455                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           227867                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         6414                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         5137                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       458947                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       659460                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       470776                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         7070                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6125                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       450235                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       618928                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       478994                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3162086                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       554088                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       249584                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       803672                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         6414                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         5137                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          458947                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          782872                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       470776                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         7070                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6125                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          450235                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          723383                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       478994                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             3389953                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         6414                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         5137                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         458947                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         782872                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       470776                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         7070                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6125                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         450235                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         723383                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       478994                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            3389953                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.275559                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.315189                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.293598                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.244994                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.272905                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.259336                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.594480                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.506582                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.554187                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.199563                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.237687                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.102763                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.173198                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.412406                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.255728                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.298776                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.087314                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.164824                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.434993                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.224964                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.777857                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.520791                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.698024                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.199563                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.237687                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.102763                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.239609                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.412406                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.255728                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.298776                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.087314                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.214173                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.434993                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.247094                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.199563                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.237687                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.102763                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.239609                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.412406                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.255728                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.298776                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.087314                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.214173                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.434993                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.247094                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15218.257501                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15723.730743                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15465.256645                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14446.515126                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13001.064660                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 13664.901171                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 136623.388218                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134226.070112                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 135618.850025                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140440.234375                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138404.586405                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 135215.200475                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137724.896469                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 168500.605117                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140764.657080                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 139445.355191                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134683.913309                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139925.054394                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 155838.767203                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   342.927279                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data  1159.827206                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   532.205133                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140440.234375                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138404.586405                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 135215.200475                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 137294.083153                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 168500.605117                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140764.657080                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 139445.355191                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 134683.913309                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 137978.603096                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 152790.436710                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140440.234375                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138404.586405                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 135215.200475                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 137294.083153                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 168500.605117                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140764.657080                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 139445.355191                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 134683.913309                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 137978.603096                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 170892.520894                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 152790.436710                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              1300                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       25                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs            52                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1038944                       # number of writebacks
system.l2c.writebacks::total                  1038944                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           98                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           25                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           68                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           17                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          208                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             98                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             25                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             68                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                208                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            98                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            25                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            68                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            17                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               208                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        42465                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        42465                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        60660                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        57967                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total       118627                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        11966                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        14089                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        26055                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        73366                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        52915                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        126281                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1280                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1221                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        47065                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       114192                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       194151                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1808                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1830                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        39244                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       101997                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       208359                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       711147                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       431001                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       129981                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       560982                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1280                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1221                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        47065                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       187558                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       194151                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1808                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1830                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        39244                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       154912                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       208359                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           837428                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1280                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1221                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        47065                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       187558                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       194151                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1808                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1830                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        39244                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       154912                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       208359                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          837428                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        29450                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         8709                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        81394                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28924                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         9093                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38017                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        58374                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        17802                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       119411                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   4288394500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   4102128000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   8390522500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    882418000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data   1039410000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total   1921828000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9289531460                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   6573150768                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  15862682228                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    166958510                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    156778008                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5894891941                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  14584550481                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  30771342562                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    236409526                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    236875020                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   4895215723                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  13251631295                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  33521925244                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 103716578310                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  29736888998                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   8990235999                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  38727124997                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    166958510                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    156778008                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   5894891941                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  23874081941                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  30771342562                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    236409526                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    236875020                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   4895215723                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  19824782063                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  33521925244                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 119579260538                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    166958510                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    156778008                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   5894891941                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  23874081941                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  30771342562                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    236409526                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    236875020                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   4895215723                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  19824782063                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  33521925244                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 119579260538                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   4854521000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4673220523                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11957000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1233601518                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  10773300041                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4598373544                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1348007106                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5946380650                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   4854521000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9271594067                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11957000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2581608624                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  16719680691                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.275559                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.315189                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.293598                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.244994                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.272905                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.259336                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.594480                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.506582                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.554187                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.199563                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.237687                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.102550                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.173160                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.412406                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.255728                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.298776                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.087163                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.164796                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.434993                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.224898                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.777857                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.520791                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.698024                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.199563                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.237687                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.102550                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.239577                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.412406                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.255728                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.298776                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.087163                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.214149                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.434993                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.247032                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.199563                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.237687                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.102550                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.239577                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.412406                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.255728                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.298776                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.087163                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.214149                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.434993                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.247032                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70695.590175                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70766.608588                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70730.293272                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73743.774026                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73774.575910                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73760.429860                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 126619.025979                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124220.934858                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 125614.163873                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125250.014682                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127719.546737                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124737.940144                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129921.775101                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 145844.077680                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68994.942002                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69165.770374                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69034.523384                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125250.014682                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 127289.062269                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124737.940144                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127974.476238                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 142793.482590                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125250.014682                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 127289.062269                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124737.940144                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127974.476238                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 142793.482590                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158683.209610                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst       108700                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 141646.746814                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132359.879610                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158981.245471                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148246.684922                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156413.726754                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158830.884760                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst       108700                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145017.898214                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 140017.927084                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               81394                       # Transaction distribution
system.membus.trans_dist::ReadResp             801457                       # Transaction distribution
system.membus.trans_dist::WriteReq              38017                       # Transaction distribution
system.membus.trans_dist::WriteResp             38017                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1145637                       # Transaction distribution
system.membus.trans_dist::CleanEvict           202586                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           388021                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         309846                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              24                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            5                       # Transaction distribution
system.membus.trans_dist::ReadExReq            139521                       # Transaction distribution
system.membus.trans_dist::ReadExResp           122200                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        720063                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        663960                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122616                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24516                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4262617                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4409841                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238367                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       238367                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4648208                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155723                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49032                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    119974316                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    120179275                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7283904                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7283904                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               127463179                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           565217                       # Total snoops (count)
system.membus.snoop_fanout::samples           3689099                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3689099    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3689099                       # Request fanout histogram
system.membus.reqLayer0.occupancy           101296000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            20132498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          7983633356                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         4606610325                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45425919                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     10607741                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      5778542                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1706398                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         126357                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       115095                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        11262                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              81396                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           3972795                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38017                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38017                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      3722299                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2264546                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          665609                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        384259                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1049868                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          134                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          134                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           281631                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          281631                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      3898638                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       910400                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       803672                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8440853                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7105433                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              15546286                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    205041299                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    177324920                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              382366219                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2848440                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          7664337                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.347835                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.479358                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5009678     65.36%     65.36% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                2643397     34.49%     99.85% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  11262      0.15%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            7664337                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8363064932                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2585436                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3816515270                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3482933794                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------