path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.456680                       # Number of seconds simulated
sim_ticks                                47456679626500                       # Number of ticks simulated
final_tick                               47456679626500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 659863                       # Simulator instruction rate (inst/s)
host_op_rate                                   776251                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            36196220555                       # Simulator tick rate (ticks/s)
host_mem_usage                                 759244                       # Number of bytes of host memory used
host_seconds                                  1311.10                       # Real time elapsed on the host
sim_insts                                   865142471                       # Number of instructions simulated
sim_ops                                    1017738631                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        51904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        48448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2877620                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         38342664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     11776896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       153536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       163840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2826616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         16120336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     11259712                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        435648                       # Number of bytes read from this memory
system.physmem.bytes_read::total             84057220                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2877620                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2826616                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5704236                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     70891776                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          70912360                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          811                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker          757                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             85370                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            599117                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       184014                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2399                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2560                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             44254                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            251893                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       175933                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6807                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1353915                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1107684                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1110258                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1094                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1021                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               60637                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              807951                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       248161                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          3235                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          3452                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               59562                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              339685                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       237263                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9180                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1771241                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          60637                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          59562                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             120199                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1493821                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1494255                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1493821                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1094                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1021                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              60637                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             808384                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       248161                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         3235                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         3452                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              59562                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             339685                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       237263                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9180                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3265496                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1353915                       # Number of read requests accepted
system.physmem.writeReqs                      1110258                       # Number of write requests accepted
system.physmem.readBursts                     1353915                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1110258                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 86619200                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     31360                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  70911104                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  84057220                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               70912360                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      490                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         220771                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               83838                       # Per bank write bursts
system.physmem.perBankRdBursts::1               89540                       # Per bank write bursts
system.physmem.perBankRdBursts::2               77326                       # Per bank write bursts
system.physmem.perBankRdBursts::3               81695                       # Per bank write bursts
system.physmem.perBankRdBursts::4               84097                       # Per bank write bursts
system.physmem.perBankRdBursts::5               94926                       # Per bank write bursts
system.physmem.perBankRdBursts::6               83322                       # Per bank write bursts
system.physmem.perBankRdBursts::7               86179                       # Per bank write bursts
system.physmem.perBankRdBursts::8               76741                       # Per bank write bursts
system.physmem.perBankRdBursts::9              125350                       # Per bank write bursts
system.physmem.perBankRdBursts::10              75788                       # Per bank write bursts
system.physmem.perBankRdBursts::11              81366                       # Per bank write bursts
system.physmem.perBankRdBursts::12              76482                       # Per bank write bursts
system.physmem.perBankRdBursts::13              81797                       # Per bank write bursts
system.physmem.perBankRdBursts::14              77630                       # Per bank write bursts
system.physmem.perBankRdBursts::15              77348                       # Per bank write bursts
system.physmem.perBankWrBursts::0               68540                       # Per bank write bursts
system.physmem.perBankWrBursts::1               72321                       # Per bank write bursts
system.physmem.perBankWrBursts::2               65671                       # Per bank write bursts
system.physmem.perBankWrBursts::3               69464                       # Per bank write bursts
system.physmem.perBankWrBursts::4               70371                       # Per bank write bursts
system.physmem.perBankWrBursts::5               77894                       # Per bank write bursts
system.physmem.perBankWrBursts::6               70312                       # Per bank write bursts
system.physmem.perBankWrBursts::7               72647                       # Per bank write bursts
system.physmem.perBankWrBursts::8               65746                       # Per bank write bursts
system.physmem.perBankWrBursts::9               72323                       # Per bank write bursts
system.physmem.perBankWrBursts::10              65450                       # Per bank write bursts
system.physmem.perBankWrBursts::11              68291                       # Per bank write bursts
system.physmem.perBankWrBursts::12              65769                       # Per bank write bursts
system.physmem.perBankWrBursts::13              69040                       # Per bank write bursts
system.physmem.perBankWrBursts::14              66651                       # Per bank write bursts
system.physmem.perBankWrBursts::15              67496                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          71                       # Number of times write queue was full causing retry
system.physmem.totGap                    47456676566000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1310690                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1107684                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1123748                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     74620                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     32556                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     27437                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     23297                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     20472                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     17890                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     14951                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     12831                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2528                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      983                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      550                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      416                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      288                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      209                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      175                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      158                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       98                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       62                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    16504                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    19352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    48877                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    56560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    60723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    62814                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    63983                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    67411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    68337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    71503                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    71245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    72329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    70408                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    71228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    74472                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    69249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    66307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    64601                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1011                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      857                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      658                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      616                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      437                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      344                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      308                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      390                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      287                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      345                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      238                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       850568                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      185.205557                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     113.971853                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     243.835447                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         513606     60.38%     60.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       167161     19.65%     80.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        54824      6.45%     86.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        28166      3.31%     89.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        18449      2.17%     91.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11525      1.35%     93.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         9338      1.10%     94.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9545      1.12%     95.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        37954      4.46%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         850568                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         62842                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.536775                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      323.180031                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          62840    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           62842                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         62842                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.631298                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.120021                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.777595                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           59398     94.52%     94.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            1045      1.66%     96.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             473      0.75%     96.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             210      0.33%     97.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             336      0.53%     97.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             469      0.75%     98.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             106      0.17%     98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              34      0.05%     98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              31      0.05%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              28      0.04%     98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              37      0.06%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              34      0.05%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             449      0.71%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              44      0.07%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              47      0.07%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              32      0.05%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               9      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               4      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             5      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            26      0.04%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             4      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::236-239             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           62842                       # Writes before turning the bus around for reads
system.physmem.totQLat                    31787428314                       # Total ticks spent queuing
system.physmem.totMemAccLat               57164147064                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6767125000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       23486.66                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  42236.66                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.83                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.49                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.77                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.49                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.31                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.28                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1086313                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    524528                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.26                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  47.34                       # Row buffer hit rate for writes
system.physmem.avgGap                     19258662.67                       # Average gap between requests
system.physmem.pageHitRate                      65.44                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3335290560                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1819851000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                5311160400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3675585600                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3099639126480                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1204726391325                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27417225862500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31735733267865                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.730691                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45610216470982                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1584682580000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    261780130518                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3095003520                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1688742000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                5245507800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3504163680                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3099639126480                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1191482148060                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27428843611500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31733498303040                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.683596                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45629577337540                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1584682580000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    242414504460                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   105954                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               105954                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10115                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        80576                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           26                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       105928                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean     0.169927                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev    55.305347                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-2047       105927    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       105928                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        90717                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 19602.257570                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18339.618281                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 10083.229942                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767        87482     96.43%     96.43% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535         2786      3.07%     99.51% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303          233      0.26%     99.76% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071          145      0.16%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839           15      0.02%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607            6      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-229375           19      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::229376-262143            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-294911           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-360447            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        90717                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   9139568088                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.172115                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0    -1573058396    -17.21%    -17.21% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1    10712626484    117.21%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   9139568088                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        80577     88.85%     88.85% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        10115     11.15%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        90692                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       105954                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       105954                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        90692                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        90692                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       196646                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    80457124                       # DTB read hits
system.cpu0.dtb.read_misses                     79863                       # DTB read misses
system.cpu0.dtb.write_hits                   72637408                       # DTB write hits
system.cpu0.dtb.write_misses                    26091                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              39897                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1024                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   34410                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  3731                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     8741                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                80536987                       # DTB read accesses
system.cpu0.dtb.write_accesses               72663499                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        153094532                       # DTB hits
system.cpu0.dtb.misses                         105954                       # DTB misses
system.cpu0.dtb.accesses                    153200486                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    53482                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                53482                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          578                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        47523                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        53482                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          53482    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        53482                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        48101                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 21551.932392                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 19925.788685                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 13354.053067                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767        45094     93.75%     93.75% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535         2542      5.28%     99.03% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303          133      0.28%     99.31% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071          277      0.58%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839            5      0.01%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607            6      0.01%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375           18      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143            2      0.00%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911            5      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679            8      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        48101                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -326738796                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -326738796    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -326738796                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        47523     98.80%     98.80% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          578      1.20%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        48101                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53482                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53482                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        48101                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        48101                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       101583                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   428491503                       # ITB inst hits
system.cpu0.itb.inst_misses                     53482                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              39897                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1024                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   24315                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               428544985                       # ITB inst accesses
system.cpu0.itb.hits                        428491503                       # DTB hits
system.cpu0.itb.misses                          53482                       # DTB misses
system.cpu0.itb.accesses                    428544985                       # DTB accesses
system.cpu0.numCycles                     94913359253                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  428232691                       # Number of instructions committed
system.cpu0.committedOps                    502476550                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            461534262                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                406829                       # Number of float alu accesses
system.cpu0.num_func_calls                   25466680                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     64818437                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   461534262                       # number of integer instructions
system.cpu0.num_fp_insts                       406829                       # number of float instructions
system.cpu0.num_int_register_reads          668961319                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         366250009                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              674435                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             305880                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           111832425                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          111484776                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    153083738                       # number of memory refs
system.cpu0.num_load_insts                   80450777                       # Number of load instructions
system.cpu0.num_store_insts                  72632961                       # Number of store instructions
system.cpu0.num_idle_cycles              93826651579.898026                       # Number of idle cycles
system.cpu0.num_busy_cycles              1086707673.101977                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.011449                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.988551                       # Percentage of idle cycles
system.cpu0.Branches                         95423987                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                348470598     69.31%     69.31% # Class of executed instruction
system.cpu0.op_class::IntMult                 1120076      0.22%     69.53% # Class of executed instruction
system.cpu0.op_class::IntDiv                    60052      0.01%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             44021      0.01%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::MemRead                80450777     16.00%     85.55% # Class of executed instruction
system.cpu0.op_class::MemWrite               72632961     14.45%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 502778486                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   14022                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          5233253                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          480.798924                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          147607157                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5233765                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.202863                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       3987157000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.798924                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.939060                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.939060                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          415                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        311404737                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       311404737                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     74943991                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       74943991                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     68564818                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      68564818                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       176894                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       176894                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       135340                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       135340                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1719391                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1719391                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1677698                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1677698                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    143508809                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       143508809                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    143685703                       # number of overall hits
system.cpu0.dcache.overall_hits::total      143685703                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2840159                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      2840159                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1279764                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1279764                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       601589                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       601589                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       758772                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       758772                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       148889                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       148889                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       188945                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       188945                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4119923                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4119923                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4721512                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4721512                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41012776500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  41012776500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  24489617000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  24489617000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  46337666000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  46337666000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2203666500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2203666500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4074419000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4074419000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2847000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2847000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  65502393500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  65502393500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  65502393500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  65502393500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     77784150                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     77784150                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     69844582                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     69844582                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       778483                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       778483                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       894112                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       894112                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1868280                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1868280                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1866643                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1866643                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    147628732                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    147628732                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    148407215                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    148407215                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036513                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036513                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018323                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018323                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.772771                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.772771                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.848632                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.848632                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.079693                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079693                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.101222                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.101222                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027907                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.027907                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031815                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.031815                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14440.310032                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14440.310032                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19136.041489                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19136.041489                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61069.288271                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61069.288271                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14800.734104                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14800.734104                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21564.047739                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21564.047739                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15898.936339                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15898.936339                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13873.181621                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13873.181621                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      3560219                       # number of writebacks
system.cpu0.dcache.writebacks::total          3560219                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        30162                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        30162                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21215                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21215                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        39917                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        39917                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        51377                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        51377                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        51377                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        51377                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2809997                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2809997                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1258549                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1258549                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       595949                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       595949                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       758772                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       758772                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       108972                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       108972                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       188945                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       188945                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4068546                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4068546                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4664495                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4664495                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        26231                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        26231                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        25453                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        25453                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        51684                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        51684                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  36991828000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  36991828000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  22707525500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  22707525500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  12844611500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  12844611500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  45578894000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  45578894000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1445565000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1445565000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3885534000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3885534000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2787000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2787000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  59699353500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  59699353500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  72543965000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  72543965000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4455810500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4455810500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4073355500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4073355500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   8529166000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   8529166000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036126                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036126                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018019                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018019                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.765526                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.765526                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.848632                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.848632                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058327                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.058327                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.101222                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.101222                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027559                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027559                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031430                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.031430                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13164.365656                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13164.365656                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18042.623291                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18042.623291                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21553.205895                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21553.205895                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60069.288271                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60069.288271                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13265.471864                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13265.471864                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20564.365291                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20564.365291                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14673.387864                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14673.387864                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15552.372765                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15552.372765                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169868.114064                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169868.114064                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160034.396731                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160034.396731                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165025.268942                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165025.268942                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          4666970                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.880807                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          423824020                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          4667482                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            90.803568                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      42558943000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.880807                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999767                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999767                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          124                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        861650489                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       861650489                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    423824020                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      423824020                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    423824020                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       423824020                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    423824020                       # number of overall hits
system.cpu0.icache.overall_hits::total      423824020                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      4667483                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      4667483                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      4667483                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       4667483                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      4667483                       # number of overall misses
system.cpu0.icache.overall_misses::total      4667483                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  48694088500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  48694088500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  48694088500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  48694088500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  48694088500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  48694088500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    428491503                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    428491503                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    428491503                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    428491503                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    428491503                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    428491503                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010893                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.010893                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010893                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.010893                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010893                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.010893                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.622572                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.622572                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.622572                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10432.622572                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.622572                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10432.622572                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4667483                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      4667483                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      4667483                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      4667483                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      4667483                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      4667483                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  46360347000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  46360347000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  46360347000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  46360347000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  46360347000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  46360347000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3777715000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3777715000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3777715000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3777715000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010893                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010893                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010893                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010893                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010893                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010893                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9932.622572                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9932.622572                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9932.622572                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9932.622572                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9932.622572                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9932.622572                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87599.188406                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87599.188406                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7039817                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7039817                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       925071                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2212798                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16140.904175                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          16304400                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2228972                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            7.314762                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle     38965596000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  7022.512638                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    61.899316                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    62.792978                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  3705.081021                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  4185.062005                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1103.556217                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.428620                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003778                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003833                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.226140                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.255436                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.067356                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.985163                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1459                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           55                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14660                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          322                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          603                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          521                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           18                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           23                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          957                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4495                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5217                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3928                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.089050                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003357                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.894775                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       335472623                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      335472623                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       224520                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       122258                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        346778                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      3560218                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      3560218                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        92512                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        92512                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        28864                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        28864                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       829198                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       829198                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4185639                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      4185639                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2620915                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2620915                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       197417                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       197417                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       224520                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       122258                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4185639                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3450113                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        7982530                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       224520                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       122258                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4185639                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3450113                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       7982530                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker         8873                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         6826                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        15699                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       123328                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       123328                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       160077                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       160077                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       230435                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       230435                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       481844                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       481844                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       894003                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       894003                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       560192                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       560192                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker         8873                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         6826                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       481844                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1124438                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1621981                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker         8873                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         6826                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       481844                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1124438                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1621981                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    259670000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    210027000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    469697000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2651049500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2651049500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3319563500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3319563500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2697000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2697000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  11221935999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  11221935999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  14420808000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  14420808000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  28972230000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  28972230000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  43145750500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total  43145750500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    259670000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    210027000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  14420808000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  40194165999                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  55084670999                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    259670000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    210027000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  14420808000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  40194165999                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  55084670999                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       233393                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       129084                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       362477                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      3560218                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      3560218                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       215840                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       215840                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       188941                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       188941                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1059633                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1059633                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      4667483                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      4667483                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3514918                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3514918                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       757609                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       757609                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       233393                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       129084                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      4667483                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4574551                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      9604511                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       233393                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       129084                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      4667483                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4574551                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      9604511                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.038017                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.052880                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.043310                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.571386                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.571386                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.847233                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.847233                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.217467                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.217467                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.103234                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.103234                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.254345                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.254345                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.739421                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.739421                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.038017                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.052880                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.103234                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.245803                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.168877                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.038017                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.052880                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.103234                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.245803                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.168877                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29265.186521                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 30768.678582                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29918.912033                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21495.925499                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21495.925499                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20737.292053                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20737.292053                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       674250                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       674250                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48698.921600                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48698.921600                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29928.375159                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29928.375159                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32407.307358                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32407.307358                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 77019.576324                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 77019.576324                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29265.186521                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 30768.678582                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29928.375159                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35746.004670                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 33961.354047                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29265.186521                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 30768.678582                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29928.375159                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35746.004670                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 33961.354047                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1248318                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1248318                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         3799                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         3799                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          319                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          319                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         4118                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         4118                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         4118                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         4118                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker         8873                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         6826                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        15699                       # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks        86363                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total        86363                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       615430                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       615430                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       123328                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       123328                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       160077                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       160077                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       226636                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       226636                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       481844                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       481844                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       893684                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       893684                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       560192                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       560192                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker         8873                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         6826                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       481844                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1120320                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1617863                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker         8873                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         6826                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       481844                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1120320                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       615430                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2233293                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        26231                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        69356                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        25453                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        25453                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        51684                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        94809                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    206432000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    169071000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    375503000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  25855371219                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  25855371219                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2504859500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2504859500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2454464000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2454464000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2337000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2337000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   9468370499                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9468370499                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  11529744000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  11529744000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  23586536500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  23586536500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  39784598500                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  39784598500                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    206432000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    169071000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  11529744000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  33054906999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  44960153999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    206432000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    169071000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  11529744000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  33054906999                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  25855371219                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  70815525218                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3454277500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4245962500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7700240000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3882458000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3882458000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3454277500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   8128420500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11582698000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.038017                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.052880                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.043310                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.571386                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.571386                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.847233                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.847233                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.213882                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.213882                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.103234                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.103234                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.254255                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.254255                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.739421                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.739421                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.038017                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.052880                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.103234                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.244903                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.168448                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.038017                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.052880                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.103234                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.244903                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.232525                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23918.912033                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42011.879855                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20310.549916                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20310.549916                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15333.020984                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15333.020984                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       584250                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       584250                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41777.875090                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41777.875090                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23928.375159                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23928.375159                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26392.479333                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26392.479333                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71019.576324                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71019.576324                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23928.375159                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29504.879855                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27789.840054                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23928.375159                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29504.879855                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31709.016783                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161868.114064                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111024.857258                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 152534.396731                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 152534.396731                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157271.505688                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 122168.760350                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq        548810                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      8811478                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        38603                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        25453                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      6868539                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      8637410                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       769123                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       445989                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       351950                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       473125                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           65                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          121                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1446257                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1069406                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      4667483                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5564741                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       864337                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       757609                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     14087759                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     16981197                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       288818                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       540500                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         31898274                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    298891412                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    527370978                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1032672                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1867144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         829162206                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    9613339                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     30204161                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.324614                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.468231                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1          20399459     67.54%     67.54% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2           9804702     32.46%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      30204161                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   14006094999                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    188261483                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   7044349500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   7482254107                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    159734000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    307107000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   101352                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               101352                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         8872                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        77968                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            3                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       101349                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.078935                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    25.129292                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-511       101348    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7680-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       101349                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        86843                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 20976.923874                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.710286                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 17538.002789                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        85298     98.22%     98.22% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1315      1.51%     99.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607           45      0.05%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           84      0.10%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           70      0.08%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           23      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        86843                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   -857364308                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean    -0.833676                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1572128036    183.37%    183.37% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1      714763728    -83.37%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   -857364308                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        77968     89.78%     89.78% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         8872     10.22%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        86840                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       101352                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       101352                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        86840                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        86840                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       188192                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    82714274                       # DTB read hits
system.cpu1.dtb.read_misses                     74721                       # DTB read misses
system.cpu1.dtb.write_hits                   75460503                       # DTB write hits
system.cpu1.dtb.write_misses                    26631                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              39897                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1024                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   38549                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4418                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10567                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                82788995                       # DTB read accesses
system.cpu1.dtb.write_accesses               75487134                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        158174777                       # DTB hits
system.cpu1.dtb.misses                         101352                       # DTB misses
system.cpu1.dtb.accesses                    158276129                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    60693                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                60693                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          593                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        54830                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        60693                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          60693    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        60693                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        55423                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 24648.566480                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 21393.176042                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 22659.824821                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        49924     90.08%     90.08% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535         3716      6.70%     96.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303          553      1.00%     97.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071          965      1.74%     99.52% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839           32      0.06%     99.58% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607           27      0.05%     99.63% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375           86      0.16%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143           15      0.03%     99.81% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911           45      0.08%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679           26      0.05%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447           10      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215           12      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        55423                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1656015036                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1656015036    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1656015036                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        54830     98.93%     98.93% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          593      1.07%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        55423                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60693                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60693                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55423                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55423                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       116116                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   437193188                       # ITB inst hits
system.cpu1.itb.inst_misses                     60693                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              39897                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1024                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   27130                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               437253881                       # ITB inst accesses
system.cpu1.itb.hits                        437193188                       # DTB hits
system.cpu1.itb.misses                          60693                       # DTB misses
system.cpu1.itb.accesses                    437253881                       # DTB accesses
system.cpu1.numCycles                     94913359253                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  436909780                       # Number of instructions committed
system.cpu1.committedOps                    515262081                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            474007520                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                488695                       # Number of float alu accesses
system.cpu1.num_func_calls                   26553696                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     66234119                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   474007520                       # number of integer instructions
system.cpu1.num_fp_insts                       488695                       # number of float instructions
system.cpu1.num_int_register_reads          687449190                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         375811208                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              781283                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             430208                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           112572477                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          112287439                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    158166235                       # number of memory refs
system.cpu1.num_load_insts                   82712263                       # Number of load instructions
system.cpu1.num_store_insts                  75453972                       # Number of store instructions
system.cpu1.num_idle_cycles              93876093406.586029                       # Number of idle cycles
system.cpu1.num_busy_cycles              1037265846.413978                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.010929                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.989071                       # Percentage of idle cycles
system.cpu1.Branches                         97493416                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                356171607     69.09%     69.09% # Class of executed instruction
system.cpu1.op_class::IntMult                 1079497      0.21%     69.30% # Class of executed instruction
system.cpu1.op_class::IntDiv                    59940      0.01%     69.31% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             68277      0.01%     69.32% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.32% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.32% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.32% # Class of executed instruction
system.cpu1.op_class::MemRead                82712263     16.04%     85.36% # Class of executed instruction
system.cpu1.op_class::MemWrite               75453972     14.64%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 515545598                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    5256                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements          5176711                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          457.282743                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          152806636                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5177218                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            29.515202                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8391490917000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   457.282743                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.893130                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.893130                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          507                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          474                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.990234                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        321544722                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       321544722                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     77092949                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       77092949                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     71608224                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      71608224                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       188155                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       188155                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       187532                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       187532                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1684198                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1684198                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1657450                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1657450                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    148701173                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       148701173                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    148889328                       # number of overall hits
system.cpu1.dcache.overall_hits::total      148889328                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      2950342                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      2950342                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1305907                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1305907                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       613815                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       613815                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       479868                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       479868                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       172330                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       172330                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       197330                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       197330                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4256249                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4256249                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      4870064                       # number of overall misses
system.cpu1.dcache.overall_misses::total      4870064                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  42135771000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  42135771000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  22153910000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  22153910000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  15218762000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  15218762000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2580362000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2580362000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4225919000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4225919000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2953000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2953000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  64289681000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  64289681000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  64289681000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  64289681000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     80043291                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     80043291                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     72914131                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     72914131                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       801970                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       801970                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       667400                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       667400                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1856528                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1856528                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1854780                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1854780                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    152957422                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    152957422                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    153759392                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    153759392                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036859                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.036859                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.017910                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.017910                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.765384                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.765384                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.719011                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.719011                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.092824                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.092824                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106390                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106390                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027826                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.027826                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031673                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.031673                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14281.656499                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14281.656499                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16964.385672                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 16964.385672                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 31714.475647                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 31714.475647                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14973.376661                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14973.376661                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21415.491816                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21415.491816                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15104.774415                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15104.774415                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13200.993046                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13200.993046                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3350646                       # number of writebacks
system.cpu1.dcache.writebacks::total          3350646                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        17552                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        17552                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          421                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          421                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        45020                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        45020                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        17973                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        17973                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        17973                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        17973                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2932790                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2932790                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1305486                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1305486                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       613815                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       613815                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       479868                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       479868                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       127310                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       127310                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       197330                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       197330                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4238276                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4238276                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4852091                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4852091                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        12503                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        12503                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        13150                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        13150                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        25653                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        25653                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38342874000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38342874000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  20834838000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  20834838000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12333914500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12333914500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  14738894000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  14738894000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1690256500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1690256500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4028650000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4028650000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2892000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2892000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  59177712000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  59177712000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  71511626500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  71511626500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2070021000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2070021000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2282534000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2282534000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4352555000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4352555000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036640                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036640                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017904                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017904                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.765384                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.765384                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.719011                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.719011                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.068574                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.068574                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106390                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106390                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027709                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027709                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031556                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031556                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13073.855953                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13073.855953                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15959.449584                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15959.449584                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20093.862972                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20093.862972                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 30714.475647                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 30714.475647                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.698610                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.698610                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20415.800943                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20415.800943                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13962.684828                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13962.684828                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14738.311070                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14738.311070                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165561.945133                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165561.945133                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173576.730038                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173576.730038                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169670.408919                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169670.408919                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          5209177                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.272261                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          431983494                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5209689                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            82.919248                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8391463454000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.272261                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969282                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969282                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          440                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        879596070                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       879596070                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    431983494                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      431983494                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    431983494                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       431983494                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    431983494                       # number of overall hits
system.cpu1.icache.overall_hits::total      431983494                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      5209694                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      5209694                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      5209694                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       5209694                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      5209694                       # number of overall misses
system.cpu1.icache.overall_misses::total      5209694                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  53989351000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  53989351000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  53989351000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  53989351000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  53989351000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  53989351000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    437193188                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    437193188                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    437193188                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    437193188                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    437193188                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    437193188                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011916                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.011916                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011916                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.011916                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011916                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.011916                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10363.248014                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10363.248014                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10363.248014                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10363.248014                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10363.248014                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10363.248014                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5209694                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5209694                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5209694                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5209694                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5209694                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5209694                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  51384504000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  51384504000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  51384504000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  51384504000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  51384504000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  51384504000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9739500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9739500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9739500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      9739500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011916                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011916                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011916                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.011916                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011916                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.011916                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9863.248014                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9863.248014                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9863.248014                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  9863.248014                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9863.248014                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  9863.248014                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88540.909091                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88540.909091                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7168932                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7168932                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       888356                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2018400                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13471.145620                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          17736817                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2034046                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            8.719968                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9876432033500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5731.708202                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    71.533292                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker   100.125774                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3516.826700                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3218.371115                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   832.580536                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.349836                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004366                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.006111                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.214650                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.196434                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.050817                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.822213                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1631                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           83                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13932                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          249                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          762                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          620                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           42                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           30                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2682                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6101                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5119                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.099548                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005066                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.850342                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       350300692                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      350300692                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       208719                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       141350                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        350069                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3350644                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3350644                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        65287                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        65287                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        34260                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        34260                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       879078                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       879078                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4680645                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4680645                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2771065                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2771065                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       220708                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       220708                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       208719                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       141350                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4680645                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3650143                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8680857                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       208719                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       141350                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4680645                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3650143                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8680857                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10729                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9390                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        20119                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       125786                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       125786                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       163059                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       163059                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           11                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total           11                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       237067                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       237067                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       529049                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       529049                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       902850                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       902850                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       257687                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       257687                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10729                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9390                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       529049                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1139917                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1689085                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10729                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9390                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       529049                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1139917                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1689085                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    428489500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    413569000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    842058500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2736210500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   2736210500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3427875000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3427875000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2800500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2800500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   9388085997                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   9388085997                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  15677246500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  15677246500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  28842829500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  28842829500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  12565083500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total  12565083500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    428489500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    413569000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  15677246500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  38230915497                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  54750220497                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    428489500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    413569000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  15677246500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  38230915497                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  54750220497                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       219448                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       150740                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       370188                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3350644                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3350644                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       191073                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       191073                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       197319                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       197319                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           11                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           11                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1116145                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1116145                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5209694                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      5209694                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3673915                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3673915                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       478395                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       478395                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       219448                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       150740                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5209694                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4790060                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10369942                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       219448                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       150740                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5209694                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4790060                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10369942                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.048891                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.062293                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.054348                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.658314                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.658314                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.826373                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.826373                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.212398                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.212398                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.101551                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.101551                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.245746                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.245746                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.538649                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.538649                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.048891                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.062293                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.101551                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.237976                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.162883                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.048891                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.062293                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.101551                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.237976                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.162883                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39937.505825                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44043.556976                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 41853.894329                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21752.901754                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21752.901754                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21022.298677                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21022.298677                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 254590.909091                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 254590.909091                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39600.981988                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39600.981988                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 29632.881831                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 29632.881831                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31946.424655                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31946.424655                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 48761.029854                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 48761.029854                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39937.505825                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44043.556976                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29632.881831                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33538.332613                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 32414.129838                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39937.505825                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44043.556976                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29632.881831                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33538.332613                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 32414.129838                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks       952252                       # number of writebacks
system.cpu1.l2cache.writebacks::total          952252                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         3771                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         3771                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          320                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          320                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4091                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         4091                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4091                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         4091                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10729                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9390                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        20119                       # number of ReadReq MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks        95458                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total        95458                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       646749                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       646749                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       125786                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       125786                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       163059                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       163059                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           11                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           11                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       233296                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       233296                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       529049                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       529049                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       902530                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       902530                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       257687                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       257687                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10729                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9390                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       529049                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1135826                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1684994                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10729                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9390                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       529049                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1135826                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       646749                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2331743                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        12503                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        12613                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        13150                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        13150                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        25653                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        25763                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    364115500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    357229000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    721344500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  24507257017                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  24507257017                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2611582999                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2611582999                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2531997500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2531997500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2434500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2434500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7622486997                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7622486997                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  12502952500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  12502952500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  23395380000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  23395380000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  11018961500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  11018961500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    364115500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    357229000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  12502952500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  31017866997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  44242163997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    364115500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    357229000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  12502952500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  31017866997                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  24507257017                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  68749421014                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8914500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1969997000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1978911500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2183909000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2183909000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8914500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   4153906000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   4162820500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.048891                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.062293                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.054348                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.658314                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.658314                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.826373                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.826373                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.209019                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.209019                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.101551                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.101551                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.245659                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.245659                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.538649                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.538649                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.048891                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.062293                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.101551                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.237121                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.162488                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.048891                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.062293                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.101551                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.237121                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.224856                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35853.894329                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37892.995609                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20762.111833                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.111833                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15528.106391                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15528.106391                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 221318.181818                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 221318.181818                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32673.029100                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32673.029100                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 23632.881831                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23632.881831                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25921.997053                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25921.997053                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 42761.029854                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 42761.029854                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23632.881831                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.643223                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26256.570645                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23632.881831                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.643223                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29484.133120                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157561.945133                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156894.592880                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166076.730038                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166076.730038                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161926.714224                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161581.356985                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq        557907                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9467454                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        38603                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        13150                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      6658964                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      9333240                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       797552                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       400874                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       357340                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       454404                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           71                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          121                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1816504                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1125838                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5209694                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5632852                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       585123                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       478395                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15628224                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16712375                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       332083                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       514043                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         33186725                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    333420856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    527793939                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1205920                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1755584                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         864176299                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    9912470                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     31389750                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.322129                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.467292                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1          21278201     67.79%     67.79% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2          10111549     32.21%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      31389750                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   14234291993                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    190598993                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7814651000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7637949368                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    181343000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    294595499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40360                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40360                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136623                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136623                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47688                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122622                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231264                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231264                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353966                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47708                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155729                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339072                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7339072                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36209000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           569839842                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92730000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147960000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115629                       # number of replacements
system.iocache.tags.tagsinuse               11.301329                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115645                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9148621285000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.403816                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.897512                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.462739                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.243595                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706333                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1041045                       # Number of tag accesses
system.iocache.tags.data_accesses             1041045                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8904                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8941                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8904                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8944                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8904                       # number of overall misses
system.iocache.overall_misses::total             8944                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1656855076                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1662050076                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12632251766                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12632251766                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1656855076                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1662419076                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1656855076                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1662419076                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8904                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8941                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8904                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8944                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8904                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8944                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 186079.860288                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 185890.848451                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118359.303707                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118359.303707                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 186079.860288                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 185869.753578                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 186079.860288                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 185869.753578                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         32671                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3430                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.525073                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106695                       # number of writebacks
system.iocache.writebacks::total               106695                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8904                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8941                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8904                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8944                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8904                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8944                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1211655076                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1215000076                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7295851766                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7295851766                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1211655076                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1215219076                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1211655076                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1215219076                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136079.860288                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 135890.848451                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68359.303707                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68359.303707                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 136079.860288                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 135869.753578                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 136079.860288                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 135869.753578                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1275038                       # number of replacements
system.l2c.tags.tagsinuse                63572.316878                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4892898                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1334308                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.666993                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   18943.726739                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    66.506889                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker    88.082899                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3576.388780                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     7769.332592                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  6333.160086                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   237.192415                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   333.040502                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3918.032205                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     9111.997525                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13194.856246                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.289058                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.001344                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.054571                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.118551                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.096636                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003619                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.005082                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.059784                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.139038                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.201338                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.970037                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10413                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          223                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        48634                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          260                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          499                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9654                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          222                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1442                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5047                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        42029                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.158890                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003403                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.742096                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 61952788                       # Number of tag accesses
system.l2c.tags.data_accesses                61952788                       # Number of data accesses
system.l2c.Writeback_hits::writebacks         2200570                       # number of Writeback hits
system.l2c.Writeback_hits::total              2200570                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           25702                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           29550                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               55252                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          5421                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          6216                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             11637                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           145994                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           170556                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               316550                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         4694                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3455                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       439478                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       496055                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       255928                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5679                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4922                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       484783                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       520043                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       283587                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2498624                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          4694                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3455                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              439478                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              642049                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       255928                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5679                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4922                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              484783                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              690599                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       283587                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2815174                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         4694                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3455                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             439478                       # number of overall hits
system.l2c.overall_hits::cpu0.data             642049                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       255928                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5679                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4922                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             484783                       # number of overall hits
system.l2c.overall_hits::cpu1.data             690599                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       283587                       # number of overall hits
system.l2c.overall_hits::total                2815174                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         41366                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         45574                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             86940                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         9742                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        11031                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           20773                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         487808                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         146598                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             634406                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          811                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker          757                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        42366                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       114531                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       184040                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2399                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2560                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        44266                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       108963                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       176139                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         676832                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker          811                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker          757                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             42366                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            602339                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       184040                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2399                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2560                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             44266                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            255561                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       176139                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1311238                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          811                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker          757                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            42366                       # number of overall misses
system.l2c.overall_misses::cpu0.data           602339                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       184040                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2399                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2560                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            44266                       # number of overall misses
system.l2c.overall_misses::cpu1.data           255561                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       176139                       # number of overall misses
system.l2c.overall_misses::total              1311238                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    225555000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    234735000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    460290000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     48941500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     54202000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    103143500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  40891325500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  11909713000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  52801038500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     72944500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker     67955000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   3540995500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  10155548500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  21472556269                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    211977500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    227366000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3707983000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data   9711131500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  19710657061                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  68879114830                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     72944500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker     67955000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   3540995500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  51046874000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  21472556269                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    211977500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    227366000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3707983000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  21620844500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  19710657061                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    121680153330                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     72944500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker     67955000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   3540995500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  51046874000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  21472556269                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    211977500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    227366000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3707983000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  21620844500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  19710657061                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   121680153330                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks      2200570                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2200570                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        67068                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        75124                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          142192                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        15163                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        17247                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         32410                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       633802                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       317154                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           950956                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         5505                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         4212                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       481844                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       610586                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       439968                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8078                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7482                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       529049                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       629006                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       459726                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3175456                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         5505                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         4212                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          481844                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1244388                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       439968                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         8078                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7482                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          529049                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          946160                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       459726                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4126412                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         5505                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         4212                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         481844                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1244388                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       439968                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         8078                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7482                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         529049                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         946160                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       459726                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4126412                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.616777                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.606650                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.611427                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.642485                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.639589                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.640944                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.769654                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.462230                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.667124                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.147321                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.179725                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.087925                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.187576                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.296979                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.342155                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.083671                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.173230                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.213145                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.147321                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.179725                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.087925                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.484044                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.296979                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.342155                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.083671                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.270103                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.317767                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.147321                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.179725                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.087925                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.484044                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.296979                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.342155                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.083671                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.270103                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.317767                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5452.666441                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5150.634133                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5294.340925                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5023.763088                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4913.607107                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4965.267414                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83826.680784                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81240.624019                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 83229.096982                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89943.896424                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89768.824306                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83581.067365                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88670.739800                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 88360.775323                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88814.843750                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83765.937740                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89123.202371                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 101766.930095                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89943.896424                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89768.824306                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 83581.067365                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 84747.748361                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88360.775323                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88814.843750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 83765.937740                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 84601.502185                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 92797.915657                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89943.896424                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89768.824306                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 83581.067365                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 84747.748361                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88360.775323                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88814.843750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 83765.937740                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 84601.502185                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 92797.915657                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1000989                       # number of writebacks
system.l2c.writebacks::total                  1000989                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           84                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           16                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          106                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           84                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          290                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             84                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            106                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             84                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                290                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            84                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            16                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           106                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            84                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               290                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        40865                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        40865                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        41366                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        45574                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        86940                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9742                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11031                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        20773                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       487808                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       146598                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        634406                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          811                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker          757                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        42282                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       114515                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       184040                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2399                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2560                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        44160                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       108879                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       176139                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       676542                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          811                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker          757                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        42282                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       602323                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       184040                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2399                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2560                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        44160                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       255477                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       176139                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1310948                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          811                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker          757                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        42282                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       602323                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       184040                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2399                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2560                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        44160                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       255477                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       176139                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1310948                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        26231                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        12501                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        81967                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        25453                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        13150                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38603                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        51684                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        25651                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       120570                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    858580500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    946408001                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1804988501                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    202067500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    228990999                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    431058499                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  36013245500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  10443733000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  46456978500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     64834500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker     60385000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   3112031500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   9009218000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  19632156269                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    187987500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    201766000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3258945500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   8616011500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  17949267061                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  62092602830                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     64834500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker     60385000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   3112031500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  45022463500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  19632156269                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    187987500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    201766000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   3258945500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  19059744500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  17949267061                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 108549581330                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     64834500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker     60385000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   3112031500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  45022463500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  19632156269                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    187987500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    201766000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   3258945500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  19059744500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  17949267061                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 108549581330                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2678027000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3773796500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6934000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1744943000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8203700500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3449741500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1960350500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5410092000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2678027000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   7223538000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6934000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3705293500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13613792500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.616777                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.606650                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.611427                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.642485                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.639589                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.640944                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.769654                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.462230                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.667124                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.147321                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.179725                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.087750                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.187549                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.296979                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.342155                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.083471                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.173097                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.213053                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.147321                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.179725                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.087750                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.484032                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.296979                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.342155                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.083471                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.270015                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.317697                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.147321                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.179725                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.087750                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.484032                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.418303                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.296979                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.342155                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.083471                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.270015                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383139                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.317697                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20755.705168                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20766.401918                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20761.312411                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20741.890782                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20758.861300                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750.902566                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73826.680784                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71240.624019                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 73229.096982                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73601.804550                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78672.820155                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73798.584692                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79133.822868                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 91779.376343                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73601.804550                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74748.039673                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73798.584692                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74604.541700                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 82802.354731                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73601.804550                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74748.039673                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73798.584692                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74604.541700                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 82802.354731                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143867.809081                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139584.273258                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100085.406322                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 135533.787766                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149076.083650                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140146.931586                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139763.524495                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 144450.255351                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 112911.939123                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               81967                       # Transaction distribution
system.membus.trans_dist::ReadResp             767450                       # Transaction distribution
system.membus.trans_dist::WriteReq              38603                       # Transaction distribution
system.membus.trans_dist::WriteResp             38603                       # Transaction distribution
system.membus.trans_dist::Writeback           1107684                       # Transaction distribution
system.membus.trans_dist::CleanEvict           202348                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           391044                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         311393                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          114065                       # Transaction distribution
system.membus.trans_dist::ReadExReq            650749                       # Transaction distribution
system.membus.trans_dist::ReadExResp           628057                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        685483                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122622                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26828                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4735959                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4885501                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342529                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342529                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5228030                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155729                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        53656                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    147705452                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    147915041                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7264128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7264128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               155179169                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           613936                       # Total snoops (count)
system.membus.snoop_fanout::samples           3578377                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3578377    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3578377                       # Request fanout histogram
system.membus.reqLayer0.occupancy           101272500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               55000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            23177500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          7575699049                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7326536131                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          229377455                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq              81969                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4074898                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38603                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38603                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          3308322                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1226405                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          439947                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        323030                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         762977                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          121                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          121                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1086983                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1086983                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4000171                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7169000                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6360157                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              13529157                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    219530790                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    185908027                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              405438817                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3048406                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         11669556                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.129089                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.335298                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               10163148     87.09%     87.09% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                1506408     12.91%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           11669556                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         7690985653                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2550000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4244781764                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3859650249                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------