path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.602418                       # Number of seconds simulated
sim_ticks                                47602418253500                       # Number of ticks simulated
final_tick                               47602418253500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 704375                       # Simulator instruction rate (inst/s)
host_op_rate                                   828740                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            38464814262                       # Simulator tick rate (ticks/s)
host_mem_usage                                 746580                       # Number of bytes of host memory used
host_seconds                                  1237.56                       # Real time elapsed on the host
sim_insts                                   871704321                       # Number of instructions simulated
sim_ops                                    1025613965                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       106624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       114944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3306740                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         39207752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     13461760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        71360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        71552                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2461816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         13970768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher      8718016                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        430784                       # Number of bytes read from this memory
system.physmem.bytes_read::total             81922116                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3306740                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2461816                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5768556                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     69209472                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          69230056                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1666                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1796                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             92075                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            612634                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       210340                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1115                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1118                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             38554                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            218306                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       136219                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6731                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1320554                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1081398                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1083972                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2240                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2415                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               69466                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              823650                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       282796                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1499                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          1503                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               51716                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              293489                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       183142                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9050                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1720965                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          69466                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          51716                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             121182                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1453907                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                432                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1454339                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1453907                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2240                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2415                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              69466                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             824083                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       282796                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1499                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         1503                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              51716                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             293489                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       183142                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9050                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3175304                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1320554                       # Number of read requests accepted
system.physmem.writeReqs                      1083972                       # Number of write requests accepted
system.physmem.readBursts                     1320554                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1083972                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 84482048                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     33408                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  69229248                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  81922116                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               69230056                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      522                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               79060                       # Per bank write bursts
system.physmem.perBankRdBursts::1               84693                       # Per bank write bursts
system.physmem.perBankRdBursts::2               79264                       # Per bank write bursts
system.physmem.perBankRdBursts::3               82906                       # Per bank write bursts
system.physmem.perBankRdBursts::4               76161                       # Per bank write bursts
system.physmem.perBankRdBursts::5               86285                       # Per bank write bursts
system.physmem.perBankRdBursts::6               80943                       # Per bank write bursts
system.physmem.perBankRdBursts::7               81570                       # Per bank write bursts
system.physmem.perBankRdBursts::8               74520                       # Per bank write bursts
system.physmem.perBankRdBursts::9              121634                       # Per bank write bursts
system.physmem.perBankRdBursts::10              72298                       # Per bank write bursts
system.physmem.perBankRdBursts::11              79752                       # Per bank write bursts
system.physmem.perBankRdBursts::12              77563                       # Per bank write bursts
system.physmem.perBankRdBursts::13              85585                       # Per bank write bursts
system.physmem.perBankRdBursts::14              78768                       # Per bank write bursts
system.physmem.perBankRdBursts::15              79030                       # Per bank write bursts
system.physmem.perBankWrBursts::0               65472                       # Per bank write bursts
system.physmem.perBankWrBursts::1               70626                       # Per bank write bursts
system.physmem.perBankWrBursts::2               66791                       # Per bank write bursts
system.physmem.perBankWrBursts::3               69615                       # Per bank write bursts
system.physmem.perBankWrBursts::4               63756                       # Per bank write bursts
system.physmem.perBankWrBursts::5               71331                       # Per bank write bursts
system.physmem.perBankWrBursts::6               67500                       # Per bank write bursts
system.physmem.perBankWrBursts::7               68943                       # Per bank write bursts
system.physmem.perBankWrBursts::8               63410                       # Per bank write bursts
system.physmem.perBankWrBursts::9               68673                       # Per bank write bursts
system.physmem.perBankWrBursts::10              63007                       # Per bank write bursts
system.physmem.perBankWrBursts::11              67951                       # Per bank write bursts
system.physmem.perBankWrBursts::12              66506                       # Per bank write bursts
system.physmem.perBankWrBursts::13              73077                       # Per bank write bursts
system.physmem.perBankWrBursts::14              66769                       # Per bank write bursts
system.physmem.perBankWrBursts::15              68280                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          42                       # Number of times write queue was full causing retry
system.physmem.totGap                    47602414888000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1277329                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1081398                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1104957                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     68933                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     30329                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     25891                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     22057                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     19390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     16894                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     14853                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     11934                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1802                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      867                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      532                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      435                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      305                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      221                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      191                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      164                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      130                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       81                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       59                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    18639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    22143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    48134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    53739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    58424                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    60173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    62461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    64493                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    65899                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    66079                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    68869                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    71761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    68201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    69441                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    73837                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    67956                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    64592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    63507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      646                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      634                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      357                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      376                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      129                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       850234                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      180.786598                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     111.487051                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     240.213026                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         527654     62.06%     62.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       158419     18.63%     80.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        52205      6.14%     86.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        27644      3.25%     90.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        18445      2.17%     92.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11596      1.36%     93.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         9081      1.07%     94.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9121      1.07%     95.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        36069      4.24%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         850234                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         60429                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.843949                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      329.896328                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          60426    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           60429                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         60429                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.900462                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.285869                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.671229                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           56824     94.03%     94.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            1552      2.57%     96.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             279      0.46%     97.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             180      0.30%     97.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             145      0.24%     97.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             117      0.19%     97.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             182      0.30%     98.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              82      0.14%     98.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             275      0.46%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              67      0.11%     98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              37      0.06%     98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              44      0.07%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             253      0.42%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              30      0.05%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              37      0.06%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             108      0.18%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             152      0.25%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               5      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             3      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            16      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             3      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            13      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             4      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-235             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           60429                       # Writes before turning the bus around for reads
system.physmem.totQLat                    28489428593                       # Total ticks spent queuing
system.physmem.totMemAccLat               53240028593                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6600160000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       21582.38                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  40332.38                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.77                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.45                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.72                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.45                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.12                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1056858                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    494645                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.06                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  45.73                       # Row buffer hit rate for writes
system.physmem.avgGap                     19797005.68                       # Average gap between requests
system.physmem.pageHitRate                      64.60                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3250149840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1773395250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                5076832800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3525340320                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3109158352560                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1224482966955                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27487341349500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31834608387225                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.760359                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45727050942416                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1589549260000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    285815210084                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3177619200                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1733820000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                5219370000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3484121040                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3109158352560                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1221031665405                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27490368798750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31834173746955                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.751229                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45732072121963                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1589549260000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    280793976787                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   112758                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               112758                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10038                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        87373                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           24                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       112734                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean     0.230631                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev    77.436531                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-2047       112733    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       112734                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        97435                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23281.346539                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 21381.718359                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 19258.937396                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        96246     98.78%     98.78% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          178      0.18%     98.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          868      0.89%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           20      0.02%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           55      0.06%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           17      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           37      0.04%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        97435                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   8883013024                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.766632                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.422974                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     2073007704     23.34%     23.34% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     6810005320     76.66%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   8883013024                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        87373     89.70%     89.70% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        10038     10.30%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        97411                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       112758                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       112758                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        97411                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        97411                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       210169                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    88968055                       # DTB read hits
system.cpu0.dtb.read_misses                     85634                       # DTB read misses
system.cpu0.dtb.write_hits                   80360369                       # DTB write hits
system.cpu0.dtb.write_misses                    27124                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              39919                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   39097                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  3879                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10141                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                89053689                       # DTB read accesses
system.cpu0.dtb.write_accesses               80387493                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        169328424                       # DTB hits
system.cpu0.dtb.misses                         112758                       # DTB misses
system.cpu0.dtb.accesses                    169441182                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    62308                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                62308                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          814                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        55869                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        62308                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          62308    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        62308                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        56683                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26679.454157                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23625.111342                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 26536.909948                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        55487     97.89%     97.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071           42      0.07%     97.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          988      1.74%     99.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           26      0.05%     99.75% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           65      0.11%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           13      0.02%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           49      0.09%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::655360-720895            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        56683                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1979242204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1979242204    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1979242204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        55869     98.56%     98.56% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          814      1.44%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        56683                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        62308                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        62308                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        56683                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        56683                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       118991                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   472241024                       # ITB inst hits
system.cpu0.itb.inst_misses                     62308                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              39919                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   28001                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               472303332                       # ITB inst accesses
system.cpu0.itb.hits                        472241024                       # DTB hits
system.cpu0.itb.misses                          62308                       # DTB misses
system.cpu0.itb.accesses                    472303332                       # DTB accesses
system.cpu0.numCycles                     95204836507                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    5131                       # number of quiesce instructions executed
system.cpu0.committedInsts                  471986732                       # Number of instructions committed
system.cpu0.committedOps                    554132163                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            509304939                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                463756                       # Number of float alu accesses
system.cpu0.num_func_calls                   28209702                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     71348449                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   509304939                       # number of integer instructions
system.cpu0.num_fp_insts                       463756                       # number of float instructions
system.cpu0.num_int_register_reads          736700300                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         403898232                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              771652                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             344244                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           122509563                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          122079243                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    169317654                       # number of memory refs
system.cpu0.num_load_insts                   88962856                       # Number of load instructions
system.cpu0.num_store_insts                  80354798                       # Number of store instructions
system.cpu0.num_idle_cycles              93934250531.242035                       # Number of idle cycles
system.cpu0.num_busy_cycles              1270585975.757973                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.013346                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.986654                       # Percentage of idle cycles
system.cpu0.Branches                        105166310                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                383762588     69.22%     69.22% # Class of executed instruction
system.cpu0.op_class::IntMult                 1237276      0.22%     69.44% # Class of executed instruction
system.cpu0.op_class::IntDiv                    66509      0.01%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             45552      0.01%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::MemRead                88962856     16.05%     85.51% # Class of executed instruction
system.cpu0.op_class::MemWrite               80354798     14.49%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 554429579                       # Class of executed instruction
system.cpu0.dcache.tags.replacements          5824476                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          506.611071                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          163267162                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5824987                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.028760                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       6293818000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.611071                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.989475                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.989475                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        344508686                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       344508686                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     82887500                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       82887500                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     75943802                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      75943802                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       196404                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       196404                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       140054                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       140054                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1847526                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1847526                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1825483                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1825483                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    158831302                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       158831302                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    159027706                       # number of overall hits
system.cpu0.dcache.overall_hits::total      159027706                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3189198                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3189198                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1439126                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1439126                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       657536                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       657536                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       792800                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       792800                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       174919                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       174919                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       195568                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       195568                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4628324                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4628324                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5285860                       # number of overall misses
system.cpu0.dcache.overall_misses::total      5285860                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  52614413500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  52614413500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36171191500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  36171191500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  66218479500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  66218479500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2808474500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2808474500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5670137000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   5670137000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      6661000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      6661000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  88785605000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  88785605000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  88785605000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  88785605000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     86076698                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     86076698                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     77382928                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     77382928                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       853940                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       853940                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       932854                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       932854                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2022445                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2022445                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2021051                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2021051                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    163459626                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    163459626                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    164313566                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    164313566                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037051                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.037051                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018597                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018597                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.770003                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.770003                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.849865                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.849865                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086489                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086489                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.096765                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.096765                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028315                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.028315                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032169                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.032169                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16497.694248                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16497.694248                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25134.138012                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 25134.138012                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83524.822780                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83524.822780                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16055.857283                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16055.857283                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28993.173730                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28993.173730                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19183.100621                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19183.100621                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16796.813574                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16796.813574                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      5824476                       # number of writebacks
system.cpu0.dcache.writebacks::total          5824476                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        27468                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        27468                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21247                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21247                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        43989                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        43989                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        48715                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        48715                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        48715                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        48715                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3161730                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3161730                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1417879                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1417879                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       656252                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       656252                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       792800                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       792800                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       130930                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       130930                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       195568                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       195568                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4579609                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4579609                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5235861                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5235861                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14992                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        14992                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15725                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        15725                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30717                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        30717                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  47545298500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  47545298500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  34168378500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  34168378500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16138287000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16138287000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  65425679500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  65425679500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1807284000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1807284000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5474645000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5474645000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      6585000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      6585000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  81713677000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  81713677000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  97851964000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  97851964000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2585195500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2585195500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2654242000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2654242000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5239437500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5239437500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036732                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036732                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018323                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018323                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.768499                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.768499                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.849865                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.849865                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064738                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064738                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.096765                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.096765                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028017                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028017                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031865                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.031865                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15037.747847                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15037.747847                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24098.232994                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24098.232994                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24591.600483                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24591.600483                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82524.822780                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82524.822780                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13803.436951                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13803.436951                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27993.562341                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27993.562341                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17842.937465                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17842.937465                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18688.800944                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18688.800944                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172438.333778                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172438.333778                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168791.224165                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168791.224165                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170571.263470                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170571.263470                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          5187208                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.827248                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          467053304                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5187720                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            90.030554                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      59167640000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.827248                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999663                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999663                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          349                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          113                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        949669768                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       949669768                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    467053304                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      467053304                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    467053304                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       467053304                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    467053304                       # number of overall hits
system.cpu0.icache.overall_hits::total      467053304                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5187720                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5187720                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5187720                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5187720                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5187720                       # number of overall misses
system.cpu0.icache.overall_misses::total      5187720                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  57877602000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  57877602000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  57877602000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  57877602000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  57877602000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  57877602000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    472241024                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    472241024                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    472241024                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    472241024                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    472241024                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    472241024                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010985                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.010985                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010985                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.010985                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010985                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.010985                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11156.654947                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11156.654947                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11156.654947                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11156.654947                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11156.654947                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11156.654947                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      5187208                       # number of writebacks
system.cpu0.icache.writebacks::total          5187208                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5187720                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      5187720                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      5187720                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      5187720                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      5187720                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      5187720                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  55283742000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  55283742000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  55283742000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  55283742000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  55283742000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  55283742000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5954209000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5954209000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   5954209000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   5954209000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010985                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010985                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010985                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010985                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010985                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010985                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10656.654947                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10656.654947                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10656.654947                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10656.654947                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10656.654947                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10656.654947                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7982984                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7983049                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           57                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1030695                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2438237                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16163.287998                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          15536795                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2453930                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.331393                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      8764179000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15209.476134                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    57.686152                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    84.208097                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   811.917616                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.928313                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003521                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005140                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.049556                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.986529                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1345                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           71                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14277                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          134                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          148                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          690                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          373                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           28                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           39                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          836                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4477                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6612                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2188                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.082092                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004333                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.871399                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       373900742                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      373900742                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       267168                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       160390                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        427558                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3842470                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3842470                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      7168468                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      7168468                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          471                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total          471                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       929656                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       929656                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4695648                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      4695648                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2994194                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2994194                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       216752                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       216752                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       267168                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       160390                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4695648                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3923850                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        9047056                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       267168                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       160390                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4695648                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3923850                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       9047056                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10276                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8531                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        18807                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       247276                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       247276                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       195553                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       195553                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           15                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total           15                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       259410                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       259410                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       492072                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       492072                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       954718                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       954718                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       574037                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       574037                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10276                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8531                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       492072                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1214128                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1725007                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10276                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8531                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       492072                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1214128                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1725007                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    446033500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    421456000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    867489500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3471551500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   3471551500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   2028869500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2028869500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      6470500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      6470500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16372128999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  16372128999                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  19305851000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  19305851000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  40062303500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  40062303500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  62780545000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total  62780545000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    446033500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    421456000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  19305851000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  56434432499                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  76607772999                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    446033500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    421456000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  19305851000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  56434432499                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  76607772999                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       277444                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       168921                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       446365                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3842470                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3842470                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      7168468                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      7168468                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       247747                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       247747                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       195553                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       195553                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           15                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           15                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1189066                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1189066                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5187720                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      5187720                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3948912                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3948912                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       790789                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       790789                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       277444                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       168921                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5187720                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5137978                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     10772063                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       277444                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       168921                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5187720                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5137978                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     10772063                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.037038                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.050503                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.042134                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998099                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998099                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.218163                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.218163                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.094853                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.094853                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.241767                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.241767                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.725904                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.725904                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.037038                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.050503                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.094853                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.236305                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.160137                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.037038                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.050503                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.094853                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.236305                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.160137                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 43405.362009                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 49402.883601                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46125.883979                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14039.176871                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14039.176871                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10375.036435                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10375.036435                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 431366.666667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 431366.666667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63112.944755                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63112.944755                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39233.793022                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39233.793022                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41962.447026                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41962.447026                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 109366.722006                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 109366.722006                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 43405.362009                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 49402.883601                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39233.793022                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46481.452120                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 44410.122973                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 43405.362009                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 49402.883601                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39233.793022                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46481.452120                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 44410.122973                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1553882                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1553882                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5243                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5243                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          604                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          604                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5847                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         5847                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5847                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         5847                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10276                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8531                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        18807                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       729213                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       729213                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       247276                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       247276                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       195553                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       195553                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           15                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           15                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       254167                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       254167                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       492072                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       492072                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       954114                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       954114                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       574037                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       574037                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10276                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8531                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       492072                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1208281                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1719160                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10276                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8531                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       492072                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1208281                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       729213                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2448373                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        14992                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        58117                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        15725                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        15725                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        30717                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        73842                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    384377500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    370270000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    754647500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  39166505132                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  39166505132                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7760971000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7760971000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   4006997499                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   4006997499                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      6014500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      6014500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  14251828999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  14251828999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  16353419000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  16353419000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  34284773000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  34284773000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  59336323000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  59336323000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    384377500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    370270000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  16353419000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  48536601999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  65644668499                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    384377500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    370270000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  16353419000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  48536601999                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  39166505132                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 104811173631                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2464927000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8095698500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2535920000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2535920000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5000847000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10631618500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.037038                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.050503                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.042134                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998099                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998099                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.213753                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.213753                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.094853                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.094853                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.241614                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.241614                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.725904                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.725904                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.037038                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.050503                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.094853                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.235167                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.159594                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.037038                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.050503                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.094853                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.235167                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.227289                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40125.883979                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53710.651253                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53710.651253                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31385.864378                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31385.864378                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20490.595895                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20490.595895                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400966.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400966.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56072.696294                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56072.696294                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33233.793022                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33233.793022                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35933.623236                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35933.623236                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 103366.722006                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 103366.722006                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33233.793022                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40169.962119                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38184.153016                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33233.793022                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40169.962119                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53710.651253                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42808.499208                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164416.155283                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139300.006883                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161266.772655                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161266.772655                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 162803.887098                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143977.932613                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests     22819923                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11703604                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          745                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops      1879398                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1879148                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          250                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        571604                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      9815849                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        15726                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        15725                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5399709                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      7169213                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2378526                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       893354                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       436778                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       349583                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       518285                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           80                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          141                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1259427                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1201684                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5187720                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4806547                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       796318                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       790789                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     15648898                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18825417                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       354875                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       604975                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         35434165                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    664167892                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    709387519                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1351368                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2219552                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1377126331                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    6368237                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     18252902                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.116630                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.321021                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          16124321     88.34%     88.34% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           2128331     11.66%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               250      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      18252902                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   22598952997                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    218107077                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   7824705000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8347252415                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    185954998                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    327531000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    91986                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong                91986                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         7535                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        69987                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            5                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        91981                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.271795                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    82.431072                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047        91980    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        91981                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        77527                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23020.089775                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21173.462910                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 18225.313395                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        76677     98.90%     98.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          165      0.21%     99.12% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          586      0.76%     99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           21      0.03%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           33      0.04%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215            9      0.01%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           21      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        77527                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -5562525576                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.783829                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.411632                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1202455220     21.62%     21.62% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    -4360070356     78.38%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -5562525576                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        69988     90.28%     90.28% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         7535      9.72%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        77523                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        91986                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        91986                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        77523                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        77523                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       169509                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    75524944                       # DTB read hits
system.cpu1.dtb.read_misses                     67300                       # DTB read misses
system.cpu1.dtb.write_hits                   69031204                       # DTB write hits
system.cpu1.dtb.write_misses                    24686                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              39919                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   34037                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4586                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     9261                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                75592244                       # DTB read accesses
system.cpu1.dtb.write_accesses               69055890                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        144556148                       # DTB hits
system.cpu1.dtb.misses                          91986                       # DTB misses
system.cpu1.dtb.accesses                    144648134                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    54155                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                54155                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          390                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        48650                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        54155                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          54155    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        54155                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        49040                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 26306.504894                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23642.829205                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 24027.787857                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        48185     98.26%     98.26% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071           51      0.10%     98.36% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          689      1.40%     99.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           22      0.04%     99.81% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           39      0.08%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           16      0.03%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           29      0.06%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::917504-983039            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        49040                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -2103778220                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -2103778220    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -2103778220                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        48650     99.20%     99.20% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          390      0.80%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        49040                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        54155                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        54155                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        49040                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        49040                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       103195                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   400011912                       # ITB inst hits
system.cpu1.itb.inst_misses                     54155                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              39919                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   23432                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               400066067                       # ITB inst accesses
system.cpu1.itb.hits                        400011912                       # DTB hits
system.cpu1.itb.misses                          54155                       # DTB misses
system.cpu1.itb.accesses                    400066067                       # DTB accesses
system.cpu1.numCycles                     95204836507                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   14080                       # number of quiesce instructions executed
system.cpu1.committedInsts                  399717589                       # Number of instructions committed
system.cpu1.committedOps                    471481802                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            433690793                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                447669                       # Number of float alu accesses
system.cpu1.num_func_calls                   24290810                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     60559296                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   433690793                       # number of integer instructions
system.cpu1.num_fp_insts                       447669                       # number of float instructions
system.cpu1.num_int_register_reads          628918503                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         343906147                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              709471                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             405960                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           102969972                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          102767338                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    144547138                       # number of memory refs
system.cpu1.num_load_insts                   75521772                       # Number of load instructions
system.cpu1.num_store_insts                  69025366                       # Number of store instructions
system.cpu1.num_idle_cycles              94207572529.552017                       # Number of idle cycles
system.cpu1.num_busy_cycles              997263977.447979                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.010475                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.989525                       # Percentage of idle cycles
system.cpu1.Branches                         89155171                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                326125112     69.13%     69.13% # Class of executed instruction
system.cpu1.op_class::IntMult                  978063      0.21%     69.33% # Class of executed instruction
system.cpu1.op_class::IntDiv                    57214      0.01%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.35% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             68664      0.01%     69.36% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.36% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.36% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.36% # Class of executed instruction
system.cpu1.op_class::MemRead                75521772     16.01%     85.37% # Class of executed instruction
system.cpu1.op_class::MemWrite               69025366     14.63%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 471776234                       # Class of executed instruction
system.cpu1.dcache.tags.replacements          4623789                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          430.899907                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          139725575                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          4624300                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            30.215508                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8408408114000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.899907                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.841601                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.841601                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          420                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           29                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        293714645                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       293714645                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     70428619                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       70428619                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     65452147                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      65452147                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       175356                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       175356                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       181976                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       181976                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1569435                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1569435                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1531483                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1531483                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    135880766                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       135880766                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    136056122                       # number of overall hits
system.cpu1.dcache.overall_hits::total      136056122                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      2625513                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      2625513                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1190956                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1190956                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       551150                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       551150                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       454381                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       454381                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       150766                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       150766                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       187526                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       187526                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      3816469                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       3816469                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      4367619                       # number of overall misses
system.cpu1.dcache.overall_misses::total      4367619                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  39306904500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  39306904500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  28030249500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  28030249500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20535959500                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  20535959500                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2343079000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2343079000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5222807000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   5222807000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5948500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5948500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  67337154000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  67337154000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  67337154000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  67337154000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     73054132                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     73054132                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     66643103                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     66643103                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       726506                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       726506                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       636357                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       636357                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1720201                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1720201                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1719009                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1719009                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    139697235                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    139697235                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    140423741                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    140423741                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035939                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035939                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.017871                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.017871                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.758631                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.758631                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.714035                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.714035                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.087644                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.087644                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.109090                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.109090                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027320                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.027320                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031103                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.031103                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14971.133070                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14971.133070                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23535.923661                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 23535.923661                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45195.462618                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45195.462618                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15541.163127                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15541.163127                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27851.108646                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27851.108646                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17643.836227                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17643.836227                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15417.359893                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15417.359893                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      4623789                       # number of writebacks
system.cpu1.dcache.writebacks::total          4623789                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        13826                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        13826                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          458                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          458                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        43478                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        43478                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        14284                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        14284                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        14284                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        14284                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2611687                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2611687                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1190498                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1190498                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       551150                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       551150                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       454381                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       454381                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       107288                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       107288                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       187526                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       187526                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      3802185                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      3802185                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4353335                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4353335                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        24123                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        24123                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        23288                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        23288                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        47411                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        47411                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  35578565500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  35578565500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26805763500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26805763500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12511151000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12511151000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  20081578500                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  20081578500                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1492978000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1492978000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5035346000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5035346000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      5883500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      5883500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  62384329000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  62384329000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  74895480000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  74895480000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   4378993500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   4378993500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   4297960500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   4297960500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   8676954000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   8676954000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035750                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035750                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017864                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017864                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.758631                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.758631                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.714035                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.714035                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062369                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.062369                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.109090                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.109090                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027217                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027217                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031001                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031001                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13622.829037                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13622.829037                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22516.428839                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22516.428839                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22700.083462                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22700.083462                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44195.462618                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44195.462618                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13915.610320                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13915.610320                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26851.455265                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26851.455265                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16407.494375                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16407.494375                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17204.161867                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17204.161867                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181527.732869                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181527.732869                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 184556.874785                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184556.874785                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 183015.629284                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 183015.629284                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          4822868                       # number of replacements
system.cpu1.icache.tags.tagsinuse          495.969838                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          395188527                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4823380                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            81.931867                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8408376446000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   495.969838                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.968691                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.968691                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          291                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          160                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        804847209                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       804847209                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    395188527                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      395188527                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    395188527                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       395188527                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    395188527                       # number of overall hits
system.cpu1.icache.overall_hits::total      395188527                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4823385                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4823385                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4823385                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4823385                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4823385                       # number of overall misses
system.cpu1.icache.overall_misses::total      4823385                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  52228876500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  52228876500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  52228876500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  52228876500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  52228876500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  52228876500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    400011912                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    400011912                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    400011912                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    400011912                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    400011912                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    400011912                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.012058                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.012058                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.012058                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.012058                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.012058                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.012058                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10828.261999                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10828.261999                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10828.261999                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10828.261999                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10828.261999                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10828.261999                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks      4822868                       # number of writebacks
system.cpu1.icache.writebacks::total          4822868                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4823385                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      4823385                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      4823385                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      4823385                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      4823385                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      4823385                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  49817184000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  49817184000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  49817184000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  49817184000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  49817184000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  49817184000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14655500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14655500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14655500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     14655500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.012058                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.012058                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.012058                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.012058                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.012058                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.012058                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10328.261999                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10328.261999                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10328.261999                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10328.261999                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10328.261999                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10328.261999                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133231.818182                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133231.818182                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133231.818182                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133231.818182                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      6259356                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      6259387                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           27                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       793397                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         1777622                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13086.026545                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          13889107                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         1793675                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            7.743380                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    10216605092500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 11949.147964                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    18.692431                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    11.350132                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1106.836018                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.729318                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001141                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000693                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.067556                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.798708                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1073                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           90                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14890                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          279                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          606                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          184                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           80                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          993                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4499                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8129                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1192                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.065491                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005493                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.908813                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       320280578                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      320280578                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       210783                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       138334                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        349117                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      2929003                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      2929003                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      6516555                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      6516555                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          209                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total          209                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       752189                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       752189                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4404363                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4404363                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2449744                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2449744                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       191107                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       191107                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       210783                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       138334                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4404363                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3201933                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        7955413                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       210783                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       138334                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4404363                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3201933                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       7955413                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9658                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8230                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        17888                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       199042                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       199042                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       187508                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       187508                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           18                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total           18                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       241510                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       241510                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       419022                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       419022                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       820381                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       820381                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       261023                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       261023                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker         9658                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8230                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       419022                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1061891                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1498801                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker         9658                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8230                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       419022                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1061891                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1498801                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    365970000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    332045500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    698015500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3049287500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   3049287500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1869580500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1869580500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      5786000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      5786000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  12702911999                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  12702911999                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  16109032000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  16109032000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  28713782500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  28713782500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  18098463500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total  18098463500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    365970000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    332045500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  16109032000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  41416694499                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  58223741999                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    365970000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    332045500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  16109032000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  41416694499                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  58223741999                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       220441                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       146564                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       367005                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      2929003                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      2929003                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      6516555                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      6516555                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       199251                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       199251                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       187508                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       187508                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           18                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           18                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data       993699                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total       993699                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4823385                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      4823385                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3270125                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3270125                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       452130                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       452130                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       220441                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       146564                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4823385                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4263824                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      9454214                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       220441                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       146564                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4823385                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4263824                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      9454214                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.043812                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.056153                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.048740                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.998951                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.998951                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.243041                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.243041                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.086873                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.086873                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.250871                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.250871                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.577318                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.577318                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.043812                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.056153                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.086873                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.249047                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.158533                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.043812                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.056153                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.086873                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.249047                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.158533                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37892.938497                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40345.747266                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39021.438953                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15319.819435                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15319.819435                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9970.670585                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  9970.670585                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 321444.444444                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 321444.444444                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52597.871720                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52597.871720                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38444.358530                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38444.358530                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35000.545478                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35000.545478                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69336.661903                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69336.661903                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37892.938497                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40345.747266                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38444.358530                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39002.773824                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 38846.879605                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37892.938497                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40345.747266                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38444.358530                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39002.773824                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 38846.879605                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks       999911                       # number of writebacks
system.cpu1.l2cache.writebacks::total          999911                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         3856                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         3856                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          484                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          484                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            2                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4340                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         4340                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4340                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         4340                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker         9658                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8230                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        17888                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       596510                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       596510                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       199042                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       199042                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       187508                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       187508                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           18                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           18                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       237654                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       237654                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       419022                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       419022                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       819897                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       819897                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       261021                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       261021                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker         9658                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8230                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       419022                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1057551                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1494461                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker         9658                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8230                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       419022                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1057551                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       596510                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2090971                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        24123                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        24233                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        23288                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        23288                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        47411                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        47521                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    308022000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    282665500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    590687500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  26979236218                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  26979236218                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   6259584005                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   6259584005                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3627729000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3627729000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      5396000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5396000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  10808104999                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  10808104999                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  13594900000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  13594900000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  23755841000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  23755841000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  16532269500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  16532269500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    308022000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    282665500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13594900000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34563945999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  48749533499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    308022000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    282665500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13594900000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34563945999                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  26979236218                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  75728769717                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13830500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   4185464000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   4199294500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   4122722000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   4122722000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13830500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   8308186000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   8322016500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.043812                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.056153                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.048740                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.998951                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.998951                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.239161                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.239161                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.086873                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.086873                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.250723                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.250723                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.577314                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.577314                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.043812                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.056153                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.086873                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.248029                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.158074                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.043812                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.056153                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.086873                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.248029                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.221168                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33021.438953                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45228.472646                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45228.472646                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31448.558621                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31448.558621                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19347.062525                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19347.062525                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 299777.777778                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 299777.777778                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45478.321421                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45478.321421                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32444.358530                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32444.358530                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28974.177244                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28974.177244                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63336.932661                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63336.932661                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32444.358530                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32683.006303                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32620.144319                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32444.358530                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32683.006303                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45228.472646                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36217.034917                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125731.818182                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173505.119595                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173288.263938                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177032.033665                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 177032.033665                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125731.818182                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 175237.518719                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 175122.924602                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests     19593534                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10054336                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1096                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops      1611494                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1611307                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          187                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq        454071                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      8632529                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        23288                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        23288                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      3935373                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      6517651                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      2069350                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       732453                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       387389                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       344195                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       449127                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           94                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          141                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1061448                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1001075                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4823385                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4143057                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       462376                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       452130                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14469858                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15078885                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       308515                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       488328                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         30345586                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    617360632                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    574871104                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1172512                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1763528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1195167776                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5321649                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     15507476                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.118236                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.322925                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          13674115     88.18%     88.18% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           1833174     11.82%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               187      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      15507476                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   19383363503                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    170060906                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7235187500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   6851260042                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    161951000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    267887000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40445                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40445                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136989                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136989                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47854                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122996                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231792                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231792                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354868                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47874                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156011                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355520                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7355520                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7513617                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             37057000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               320500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               13000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            26714502                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            37418500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           568759261                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92994000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148232000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115885                       # number of replacements
system.iocache.tags.tagsinuse               11.295009                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115901                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9206049239000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.821414                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.473594                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.238838                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.467100                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.705938                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1043421                       # Number of tag accesses
system.iocache.tags.data_accesses             1043421                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8912                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8949                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8912                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8952                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8912                       # number of overall misses
system.iocache.overall_misses::total             8952                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5263500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1680350485                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1685613985                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13574924276                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13574924276                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5632500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1680350485                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1685982985                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5632500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1680350485                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1685982985                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8912                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8949                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8912                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8952                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8912                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8952                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142256.756757                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 188549.201638                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 188357.803665                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126887.424998                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126887.424998                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 140812.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 188549.201638                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 188335.900916                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 140812.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 188549.201638                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 188335.900916                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         33982                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3504                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.698059                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106958                       # number of writebacks
system.iocache.writebacks::total               106958                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8912                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8949                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8912                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8952                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8912                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8952                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3413500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1234750485                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1238163985                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8219197460                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8219197460                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3632500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1234750485                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1238382985                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3632500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1234750485                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1238382985                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92256.756757                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138549.201638                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 138357.803665                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76826.417595                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76826.417595                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90812.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 138549.201638                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 138335.900916                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90812.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 138549.201638                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 138335.900916                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1212335                       # number of replacements
system.l2c.tags.tagsinuse                62688.740428                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5318857                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1271612                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.182767                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   22897.710256                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   262.803618                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   467.362186                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4684.066084                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    11639.690690                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16421.765271                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     8.113156                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     2.385766                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2988.095077                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1979.468778                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1337.279546                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.349391                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.004010                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.007131                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.071473                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.177608                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.250576                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000124                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000036                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.045595                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.030204                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.020405                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.956554                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10727                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          233                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        48317                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1           79                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          232                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         1534                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         8882                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          227                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          300                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1867                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3        10232                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        35894                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.163681                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003555                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.737259                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 68046834                       # Number of tag accesses
system.l2c.tags.data_accesses                68046834                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks      2553793                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2553793                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          170923                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          116715                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              287638                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         41425                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         35212                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             76637                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           168896                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           169545                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               338441                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5417                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4358                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       442976                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       579881                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       303485                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5587                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4895                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       380461                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       481285                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       259287                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2467632                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5417                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4358                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              442976                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              748777                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       303485                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5587                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4895                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              380461                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              650830                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       259287                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2806073                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5417                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4358                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             442976                       # number of overall hits
system.l2c.overall_hits::cpu0.data             748777                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       303485                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5587                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4895                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             380461                       # number of overall hits
system.l2c.overall_hits::cpu1.data             650830                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       259287                       # number of overall hits
system.l2c.overall_hits::total                2806073                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         65926                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         56137                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total            122063                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        14762                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        11662                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           26424                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         479802                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         149602                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             629404                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1666                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1796                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        49096                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       137247                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       210371                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1115                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1118                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        38561                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        72759                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       136420                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         650149                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1666                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1796                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             49096                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            617049                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       210371                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1115                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1118                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             38561                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            222361                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       136420                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1279553                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1666                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1796                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            49096                       # number of overall misses
system.l2c.overall_misses::cpu0.data           617049                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       210371                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1115                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1118                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            38561                       # number of overall misses
system.l2c.overall_misses::cpu1.data           222361                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       136420                       # number of overall misses
system.l2c.overall_misses::total              1279553                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    951839000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    920304000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1872143000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data    185965000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data    175745500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    361710500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  63393976500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  19575358000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  82969334500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    226854500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    248582500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6606900000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  18800983000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  33843632698                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    154867000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    158576000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5179317500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  10092238000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  22255519844                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  97567471042                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    226854500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    248582500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6606900000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  82194959500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  33843632698                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    154867000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    158576000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   5179317500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  29667596000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  22255519844                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    180536805542                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    226854500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    248582500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6606900000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  82194959500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  33843632698                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    154867000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    158576000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   5179317500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  29667596000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  22255519844                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   180536805542                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2553793                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2553793                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       236849                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       172852                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          409701                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        56187                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        46874                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        103061                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       648698                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       319147                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           967845                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         7083                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6154                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       492072                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       717128                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       513856                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         6702                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6013                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       419022                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       554044                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       395707                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3117781                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         7083                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6154                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          492072                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1365826                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       513856                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         6702                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6013                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          419022                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          873191                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       395707                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4085626                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         7083                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6154                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         492072                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1365826                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       513856                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         6702                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6013                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         419022                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         873191                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       395707                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4085626                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.278346                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.324769                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.297932                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.262730                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.248795                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.256392                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.739638                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.468756                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.650315                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.235211                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.291843                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.099774                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.191384                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.409397                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.166368                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.185930                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.092026                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.131324                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.344750                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.208529                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.235211                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.291843                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.099774                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.451777                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.409397                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.166368                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.185930                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.092026                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.254653                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.344750                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.313184                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.235211                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.291843                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.099774                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.451777                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.409397                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.166368                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.185930                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.092026                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.254653                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.344750                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.313184                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14437.991081                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16393.893511                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15337.514234                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12597.547758                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15069.927971                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 13688.711020                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 132125.286055                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130849.574204                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 131822.064207                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136167.166867                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138408.964365                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134571.044484                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136986.476936                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 160875.941541                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 138894.170404                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141838.998211                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134314.916626                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138707.761239                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 163139.714441                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 150069.401079                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136167.166867                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138408.964365                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 134571.044484                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 133206.535462                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 160875.941541                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 138894.170404                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141838.998211                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 134314.916626                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 133420.860673                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 163139.714441                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 141093.651878                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136167.166867                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138408.964365                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 134571.044484                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 133206.535462                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 160875.941541                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 138894.170404                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141838.998211                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 134314.916626                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 133420.860673                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 163139.714441                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 141093.651878                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              974440                       # number of writebacks
system.l2c.writebacks::total                   974440                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          109                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           16                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          101                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           21                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          247                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            109                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            101                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             21                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                247                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           109                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            16                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           101                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            21                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               247                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        38798                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        38798                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        65926                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        56137                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total       122063                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        14762                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11662                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        26424                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       479802                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       149602                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        629404                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1666                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1796                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        48987                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       137231                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       210371                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1115                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1118                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        38460                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        72738                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       136420                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       649902                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1666                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1796                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        48987                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       617033                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       210371                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1115                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1118                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        38460                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       222340                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       136420                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1279306                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1666                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1796                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        48987                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       617033                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       210371                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1115                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1118                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        38460                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       222340                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       136420                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1279306                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        14992                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        24121                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        82348                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15725                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        23288                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        39013                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        30717                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        47409                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       121361                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   4679642000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   3966885500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   8646527500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data   1090611500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    859764000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total   1950375500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  58595767959                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  18079108058                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  76674876017                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    210193003                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    230621502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   6104112113                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17426442010                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  31739278014                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    143716501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    147393505                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   4783143154                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   9361991430                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  20890811537                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  91037702769                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    210193003                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    230621502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   6104112113                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  76022209969                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  31739278014                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    143716501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    147393505                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   4783143154                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  27441099488                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  20890811537                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 167712578786                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    210193003                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    230621502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   6104112113                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  76022209969                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  31739278014                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    143716501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    147393505                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   4783143154                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  27441099488                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  20890811537                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 167712578786                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   4854521000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2194977011                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11849500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3751197013                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  10812544524                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2268278521                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3726528606                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5994807127                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   4854521000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4463255532                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11849500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   7477725619                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  16807351651                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.278346                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.324769                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.297932                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.262730                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.248795                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.256392                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.739638                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.468756                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.650315                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.235211                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.291843                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.099553                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.191362                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.409397                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.166368                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.185930                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.091785                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.131286                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.344750                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.208450                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.235211                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.291843                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.099553                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.451765                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.409397                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.166368                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.185930                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.091785                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.254629                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.344750                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.313124                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.235211                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.291843                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.099553                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.451765                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.409397                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.166368                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.185930                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.091785                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.254629                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.344750                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.313124                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70983.253951                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70664.365748                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70836.596675                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73879.657228                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73723.546561                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73810.759158                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122124.893100                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120848.037179                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 121821.399319                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124606.775532                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126986.191240                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124366.696672                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128708.397674                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140079.123882                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124606.775532                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123206.068345                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124366.696672                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123419.535342                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 131096.531077                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124606.775532                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123206.068345                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124366.696672                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123419.535342                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 131096.531077                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146409.886006                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107722.727273                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155515.816633                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131303.061689                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144246.646804                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160019.263397                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153661.782662                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145302.455709                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107722.727273                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157727.976102                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 138490.550103                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               82348                       # Transaction distribution
system.membus.trans_dist::ReadResp             741199                       # Transaction distribution
system.membus.trans_dist::WriteReq              39013                       # Transaction distribution
system.membus.trans_dist::WriteResp             39013                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1081398                       # Transaction distribution
system.membus.trans_dist::CleanEvict           196468                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           401198                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         306316                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
system.membus.trans_dist::ReadExReq            643986                       # Transaction distribution
system.membus.trans_dist::ReadExResp           621414                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        658851                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106984                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122996                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        28036                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4525576                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4676700                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238552                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       238552                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4915252                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156011                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        56072                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    143876076                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    144088363                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7276096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7276096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               151364459                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           576558                       # Total snoops (count)
system.membus.snoop_fanout::samples           3516604                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3516604    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3516604                       # Request fanout histogram
system.membus.reqLayer0.occupancy           101595998                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            23093498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          7460114319                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6921315949                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45614101                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             162                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              162                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     10579543                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      5766836                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1724769                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         116961                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       105875                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        11086                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              82350                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           3947474                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             39013                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            39013                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      3635231                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2252852                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          680846                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        382953                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1063799                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          141                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          141                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1092357                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1092357                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      3872368                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       106984                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8825237                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6597118                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              15422355                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    252378371                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    173059496                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              425437867                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2867232                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          7585274                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.353752                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.481180                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                4913057     64.77%     64.77% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                2661131     35.08%     99.85% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  11086      0.15%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            7585274                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8312830316                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2630923                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4557123754                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3526163360                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------