path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.526955                       # Number of seconds simulated
sim_ticks                                47526954967000                       # Number of ticks simulated
final_tick                               47526954967000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 679404                       # Simulator instruction rate (inst/s)
host_op_rate                                   799114                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            36258651928                       # Simulator tick rate (ticks/s)
host_mem_usage                                 756696                       # Number of bytes of host memory used
host_seconds                                  1310.78                       # Real time elapsed on the host
sim_insts                                   890546366                       # Number of instructions simulated
sim_ops                                    1047459319                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       120896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       123520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3402100                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         13323656                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     13846976                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       139776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       143808                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3041464                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         11124432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     15361728                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        416704                       # Number of bytes read from this memory
system.physmem.bytes_read::total             61045060                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3402100                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3041464                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6443564                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     78583104                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          78603688                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1889                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1930                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             93565                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            208195                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       216359                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2184                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2247                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             47611                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            173832                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       240027                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6511                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                994350                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1227861                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1230435                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2544                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2599                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               71583                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              280339                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       291350                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2941                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          3026                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               63995                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              234066                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       323221                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8768                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1284430                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          71583                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          63995                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             135577                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1653443                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1653876                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1653443                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2544                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2599                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              71583                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             280772                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       291350                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2941                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         3026                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              63995                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             234066                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       323221                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8768                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2938306                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        994350                       # Number of read requests accepted
system.physmem.writeReqs                      1902822                       # Number of write requests accepted
system.physmem.readBursts                      994350                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1902822                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 63617152                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     21248                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 118663680                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  61045060                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              121636456                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      332                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   48679                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         115330                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               57482                       # Per bank write bursts
system.physmem.perBankRdBursts::1               61474                       # Per bank write bursts
system.physmem.perBankRdBursts::2               58055                       # Per bank write bursts
system.physmem.perBankRdBursts::3               62815                       # Per bank write bursts
system.physmem.perBankRdBursts::4               61744                       # Per bank write bursts
system.physmem.perBankRdBursts::5               72443                       # Per bank write bursts
system.physmem.perBankRdBursts::6               62137                       # Per bank write bursts
system.physmem.perBankRdBursts::7               62898                       # Per bank write bursts
system.physmem.perBankRdBursts::8               53757                       # Per bank write bursts
system.physmem.perBankRdBursts::9               98485                       # Per bank write bursts
system.physmem.perBankRdBursts::10              53699                       # Per bank write bursts
system.physmem.perBankRdBursts::11              61424                       # Per bank write bursts
system.physmem.perBankRdBursts::12              50178                       # Per bank write bursts
system.physmem.perBankRdBursts::13              60766                       # Per bank write bursts
system.physmem.perBankRdBursts::14              57507                       # Per bank write bursts
system.physmem.perBankRdBursts::15              59154                       # Per bank write bursts
system.physmem.perBankWrBursts::0              114707                       # Per bank write bursts
system.physmem.perBankWrBursts::1              119877                       # Per bank write bursts
system.physmem.perBankWrBursts::2              118693                       # Per bank write bursts
system.physmem.perBankWrBursts::3              118700                       # Per bank write bursts
system.physmem.perBankWrBursts::4              118108                       # Per bank write bursts
system.physmem.perBankWrBursts::5              125436                       # Per bank write bursts
system.physmem.perBankWrBursts::6              113884                       # Per bank write bursts
system.physmem.perBankWrBursts::7              116296                       # Per bank write bursts
system.physmem.perBankWrBursts::8              112515                       # Per bank write bursts
system.physmem.perBankWrBursts::9              116242                       # Per bank write bursts
system.physmem.perBankWrBursts::10             112992                       # Per bank write bursts
system.physmem.perBankWrBursts::11             118745                       # Per bank write bursts
system.physmem.perBankWrBursts::12             107808                       # Per bank write bursts
system.physmem.perBankWrBursts::13             111387                       # Per bank write bursts
system.physmem.perBankWrBursts::14             114155                       # Per bank write bursts
system.physmem.perBankWrBursts::15             114575                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         406                       # Number of times write queue was full causing retry
system.physmem.totGap                    47526951912500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  951125                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1900248                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    698116                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     83658                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     42191                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     36638                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     31495                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     28119                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     24839                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     21358                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     17624                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4596                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1385                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1018                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      839                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      651                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      464                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      363                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      281                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      218                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       93                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    55966                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    69244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    86453                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    95710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    99723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    98450                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    98652                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    98653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   101180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   101256                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   102685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   108850                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   104999                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   104785                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   118151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   108223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   102687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    99179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     6890                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     5415                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     5566                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     6838                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     6775                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     6308                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     6158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     7224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     5430                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     4899                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     4456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     5091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     4051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     3523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     3763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     2982                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     2416                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1572                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      928                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      971                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      818                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      630                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      450                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                     1611                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1054851                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      172.802142                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     106.115345                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     242.100455                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         681651     64.62%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       201380     19.09%     83.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        48895      4.64%     88.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        24340      2.31%     90.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        17755      1.68%     92.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11649      1.10%     93.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8558      0.81%     94.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         7940      0.75%     95.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        52683      4.99%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1054851                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         92018                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        10.802300                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      106.341779                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          92015    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           92018                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         92018                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.149536                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.827281                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       17.009129                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31           90131     97.95%     97.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47             760      0.83%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              32      0.03%     98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              41      0.04%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95             142      0.15%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111            182      0.20%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127           347      0.38%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143           116      0.13%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            35      0.04%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175            12      0.01%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            63      0.07%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            31      0.03%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            15      0.02%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             6      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             4      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             5      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             6      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319            11      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335            16      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             8      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            24      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             5      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             4      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::432-447             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::448-463             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::464-479             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::736-751             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::848-863             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           92018                       # Writes before turning the bus around for reads
system.physmem.totQLat                    36585898476                       # Total ticks spent queuing
system.physmem.totMemAccLat               55223735976                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4970090000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       36806.07                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  55556.07                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.34                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.50                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.28                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.56                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.94                       # Average write queue length when enqueuing
system.physmem.readRowHits                     744165                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1049121                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.86                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  56.58                       # Row buffer hit rate for writes
system.physmem.avgGap                     16404601.42                       # Average gap between requests
system.physmem.pageHitRate                      62.96                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 4105851120                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2240295750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3892535400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               6128142480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3104229389040                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1214897373855                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           27450471155250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             31785964742895                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.798736                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   45665609957576                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1587029340000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    274315218424                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 3868822440                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 2110964625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3860766000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               5886555120                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3104229389040                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1202076105075                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           27461717882250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             31783750484550                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.752146                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   45684364167822                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1587029340000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    255557515928                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   101631                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               101631                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9048                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        76119                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           11                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       101620                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean     0.113167                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev    36.075158                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-1023       101619    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::11264-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       101620                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        85178                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 19101.889572                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 17045.635811                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 15664.933997                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        84047     98.67%     98.67% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          953      1.12%     99.79% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607           46      0.05%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           63      0.07%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           53      0.06%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        85178                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   6479942056                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.123756                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     -801929896    -12.38%    -12.38% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     7281871952    112.38%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   6479942056                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        76120     89.38%     89.38% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M         9048     10.62%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        85168                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       101631                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       101631                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85168                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85168                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       186799                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    83767358                       # DTB read hits
system.cpu0.dtb.read_misses                     74871                       # DTB read misses
system.cpu0.dtb.write_hits                   75914688                       # DTB write hits
system.cpu0.dtb.write_misses                    26760                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              42080                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   32159                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  3900                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     8424                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                83842229                       # DTB read accesses
system.cpu0.dtb.write_accesses               75941448                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        159682046                       # DTB hits
system.cpu0.dtb.misses                         101631                       # DTB misses
system.cpu0.dtb.accesses                    159783677                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    55722                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                55722                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          543                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        49598                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        55722                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          55722    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        55722                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        50141                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 22337.612912                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 19289.783493                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 21041.520478                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        48785     97.30%     97.30% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071         1144      2.28%     99.58% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607           57      0.11%     99.69% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           79      0.16%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           56      0.11%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           13      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        50141                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -241360296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -241360296    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -241360296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        49598     98.92%     98.92% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          543      1.08%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        50141                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        55722                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        55722                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        50141                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        50141                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       105863                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   444122432                       # ITB inst hits
system.cpu0.itb.inst_misses                     55722                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              42080                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   22526                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               444178154                       # ITB inst accesses
system.cpu0.itb.hits                        444122432                       # DTB hits
system.cpu0.itb.misses                          55722                       # DTB misses
system.cpu0.itb.accesses                    444178154                       # DTB accesses
system.cpu0.numCycles                     95053909934                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  443872382                       # Number of instructions committed
system.cpu0.committedOps                    521690846                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            479475231                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                421225                       # Number of float alu accesses
system.cpu0.num_func_calls                   26535732                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     67239811                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   479475231                       # number of integer instructions
system.cpu0.num_fp_insts                       421225                       # number of float instructions
system.cpu0.num_int_register_reads          693782505                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         380162379                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              701849                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             304628                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           115037577                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          114748059                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    159672530                       # number of memory refs
system.cpu0.num_load_insts                   83761106                       # Number of load instructions
system.cpu0.num_store_insts                  75911424                       # Number of store instructions
system.cpu0.num_idle_cycles              93959856753.206024                       # Number of idle cycles
system.cpu0.num_busy_cycles              1094053180.793977                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.011510                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.988490                       # Percentage of idle cycles
system.cpu0.Branches                         99058393                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                361081858     69.17%     69.17% # Class of executed instruction
system.cpu0.op_class::IntMult                 1125018      0.22%     69.39% # Class of executed instruction
system.cpu0.op_class::IntDiv                    61306      0.01%     69.40% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.40% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             43308      0.01%     69.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
system.cpu0.op_class::MemRead                83761106     16.05%     85.46% # Class of executed instruction
system.cpu0.op_class::MemWrite               75911424     14.54%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 521984020                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    5106                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          5414405                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          480.206026                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          154030593                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5414914                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.445621                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       4071814500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.206026                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.937902                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.937902                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          344                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        324790756                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       324790756                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     77996551                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       77996551                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     71694037                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      71694037                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       187802                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       187802                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       131287                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       131287                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1831493                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1831493                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1787873                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1787873                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    149690588                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       149690588                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    149878390                       # number of overall hits
system.cpu0.dcache.overall_hits::total      149878390                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2964325                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      2964325                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1343066                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1343066                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       617580                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       617580                       # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       739156                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total       739156                       # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       153043                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       153043                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       195288                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       195288                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4307391                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4307391                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4924971                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4924971                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  44154787210                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  44154787210                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  26046845450                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  26046845450                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  30884044772                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  30884044772                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2257944026                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2257944026                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4202199390                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4202199390                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2186500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2186500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  70201632660                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  70201632660                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  70201632660                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  70201632660                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     80960876                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     80960876                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     73037103                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     73037103                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       805382                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       805382                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       870443                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total       870443                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1984536                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1984536                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1983161                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1983161                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    153997979                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    153997979                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    154803361                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    154803361                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036614                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036614                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018389                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018389                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766816                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766816                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.849172                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.849172                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.077118                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077118                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098473                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098473                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027970                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.027970                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031814                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.031814                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14895.393457                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14895.393457                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19393.570718                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19393.570718                       # average WriteReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41782.850673                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41782.850673                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14753.657639                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14753.657639                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21517.960090                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21517.960090                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16297.947565                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16297.947565                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14254.222545                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14254.222545                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      3655915                       # number of writebacks
system.cpu0.dcache.writebacks::total          3655915                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        33290                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        33290                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21376                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21376                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        42886                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        42886                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        54666                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        54666                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        54666                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        54666                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2931035                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2931035                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1321690                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1321690                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       611921                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       611921                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       739156                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       739156                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       110157                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       110157                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       195288                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       195288                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4252725                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4252725                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4864646                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4864646                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16584                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16584                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18033                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18033                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34617                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34617                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38329059920                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  38329059920                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  23455096050                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  23455096050                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13388812156                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13388812156                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  29772038228                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  29772038228                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1440580476                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1440580476                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3899742610                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3899742610                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2117500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2117500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61784155970                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  61784155970                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  75172968126                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  75172968126                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2701006250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2701006250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2792188500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2792188500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5493194750                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5493194750                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036203                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036203                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018096                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018096                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.759790                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.759790                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.849172                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.849172                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.055508                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.055508                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098473                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098473                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027615                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027615                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031425                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.031425                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13076.971077                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13076.971077                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17746.291528                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17746.291528                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21879.968421                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21879.968421                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 40278.423267                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 40278.423267                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13077.520956                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13077.520956                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19969.187098                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19969.187098                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14528.133366                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14528.133366                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15452.916435                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15452.916435                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162868.201278                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162868.201278                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154837.714191                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154837.714191                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 158684.887483                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 158684.887483                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          5032307                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.899757                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          439089613                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5032819                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            87.245262                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      33435686250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.899757                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999804                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        893277683                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       893277683                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    439089613                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      439089613                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    439089613                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       439089613                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    439089613                       # number of overall hits
system.cpu0.icache.overall_hits::total      439089613                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5032819                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5032819                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5032819                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5032819                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5032819                       # number of overall misses
system.cpu0.icache.overall_misses::total      5032819                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  52854361147                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  52854361147                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  52854361147                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  52854361147                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  52854361147                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  52854361147                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    444122432                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    444122432                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    444122432                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    444122432                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    444122432                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    444122432                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011332                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011332                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011332                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011332                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011332                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011332                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10501.939598                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10501.939598                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10501.939598                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10501.939598                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10501.939598                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10501.939598                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5032819                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      5032819                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      5032819                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      5032819                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      5032819                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      5032819                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  47804251855                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  47804251855                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  47804251855                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  47804251855                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  47804251855                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  47804251855                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3811870500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3811870500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3811870500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3811870500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011332                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011332                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011332                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.011332                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011332                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.011332                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9498.504090                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9498.504090                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9498.504090                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9498.504090                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9498.504090                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9498.504090                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88391.200000                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88391.200000                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7211191                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7211221                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           21                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       945331                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements         2374120                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16169.428044                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          10531211                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2389368                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            4.407530                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      5341335500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  8264.618229                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    69.150581                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    77.449352                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  3311.410043                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3382.587139                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1064.212699                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.504432                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004221                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004727                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.202112                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.206457                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.064954                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.986904                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1373                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           85                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        13790                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          173                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          780                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          417                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           54                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           15                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           16                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3709                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6679                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3275                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.083801                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005188                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.841675                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       244043620                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      244043620                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       211402                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       128647                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      4517111                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data      2702351                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       7559511                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      3655914                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      3655914                       # number of Writeback hits
system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       175642                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.WriteInvalidateReq_hits::total       175642                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       102383                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total       102383                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        30801                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        30801                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       876779                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       876779                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       211402                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       128647                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4517111                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3579130                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8436290                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       211402                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       128647                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4517111                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3579130                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8436290                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10881                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8892                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst       515708                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data       950762                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total      1486243                       # number of ReadReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data       562136                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::total       562136                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       120119                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       120119                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       164484                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       164484                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       240029                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       240029                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10881                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8892                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       515708                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1190791                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1726272                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10881                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8892                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       515708                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1190791                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1726272                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    393469249                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    355451999                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  15907969852                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  31938942740                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total  48595833840                       # number of ReadReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data    181717619                       # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total    181717619                       # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2563026586                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2563026586                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3399427212                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3399427212                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2070498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2070498                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  12166293140                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  12166293140                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    393469249                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    355451999                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  15907969852                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  44105235880                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  60762126980                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    393469249                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    355451999                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  15907969852                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  44105235880                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  60762126980                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       222283                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       137539                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      5032819                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data      3653113                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      9045754                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      3655914                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      3655914                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       737778                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::total       737778                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       222502                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       222502                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       195285                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       195285                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1116808                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1116808                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       222283                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       137539                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5032819                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4769921                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     10162562                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       222283                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       137539                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5032819                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4769921                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     10162562                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.048951                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.064651                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.102469                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.260261                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.164303                       # miss rate for ReadReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.761931                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.761931                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.539856                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.539856                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.842277                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.842277                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.214924                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.214924                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.048951                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.064651                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.102469                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.249646                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.169866                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.048951                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.064651                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.102469                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.249646                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.169866                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36161.129400                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39974.358862                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30846.854910                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33592.994609                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32697.098550                       # average ReadReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data   323.262732                       # average WriteInvalidateReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total   323.262732                       # average WriteInvalidateReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21337.395300                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21337.395300                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20667.221201                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20667.221201                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       690166                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       690166                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50686.763433                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50686.763433                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36161.129400                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39974.358862                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30846.854910                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37038.603651                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 35198.466395                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36161.129400                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39974.358862                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30846.854910                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37038.603651                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 35198.466395                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1321734                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1321734                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data          498                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          498                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         6011                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         6011                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6509                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         6509                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6509                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         6509                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10881                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8892                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       515708                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       950264                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total      1485745                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       659076                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       659076                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data       562136                       # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total       562136                       # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       120119                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       120119                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       164484                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       164484                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       234018                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       234018                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10881                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8892                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       515708                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1184282                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1719763                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10881                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8892                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       515708                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1184282                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       659076                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2378839                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        16584                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        59709                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        18033                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        18033                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        34617                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        77742                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    322190251                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    297082001                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  12538366148                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  25676104173                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  38833742573                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  32139076466                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  32139076466                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  24223804784                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  24223804784                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2466827080                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2466827080                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2435399890                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2435399890                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1771498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1771498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   9980703954                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9980703954                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    322190251                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    297082001                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  12538366148                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  35656808127                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  48814446527                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    322190251                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    297082001                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  12538366148                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  35656808127                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  32139076466                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  80953522993                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3468251000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2568327500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6036578500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2656940000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2656940000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3468251000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5225267500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8693518500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.048951                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.064651                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.102469                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.260124                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.164248                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.761931                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.761931                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.539856                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.539856                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.842277                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.842277                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.209542                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.209542                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.048951                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.064651                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.102469                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248281                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.169225                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.048951                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.064651                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.102469                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248281                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.234079                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24312.917674                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27019.969370                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26137.555619                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48763.839779                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43092.427427                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43092.427427                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20536.526944                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20536.526944                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14806.302680                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14806.302680                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 590499.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590499.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42649.300285                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42649.300285                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24312.917674                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30108.376322                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28384.403274                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24312.917674                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30108.376322                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34030.685975                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154867.794260                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101099.976553                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147337.658737                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 147337.658737                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 150945.128116                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111825.248900                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq      11389901                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      9301467                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        38146                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        18033                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      3655914                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       950949                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1103178                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       737778                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       440847                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       362789                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       484218                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           43                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           86                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1248974                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1125262                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     10151888                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     15745151                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       304033                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       517558                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         26718630                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    322272916                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    593126965                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1100312                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1778264                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         918278457                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    4307980                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     19190741                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.234424                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.423639                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1          14691964     76.56%     76.56% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2           4498777     23.44%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      19190741                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   11979643994                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    187059488                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   7611089646                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   7824710310                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    166780001                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    295551751                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   115983                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               115983                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11170                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        89969                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore           19                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       115964                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.064675                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    22.024176                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-511       115963    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7168-7679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       115964                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       101158                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 19050.238172                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17171.563979                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 14858.973019                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        99918     98.77%     98.77% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1061      1.05%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607           33      0.03%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           72      0.07%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           53      0.05%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       101158                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   3223072220                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.344065                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.475063                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     2114124352     65.59%     65.59% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1     1108947868     34.41%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   3223072220                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        89969     88.96%     88.96% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        11170     11.04%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       101139                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       115983                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       115983                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       101139                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       101139                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       217122                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    83993689                       # DTB read hits
system.cpu1.dtb.read_misses                     86321                       # DTB read misses
system.cpu1.dtb.write_hits                   76478778                       # DTB write hits
system.cpu1.dtb.write_misses                    29662                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              42080                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   42752                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4958                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    11385                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                84080010                       # DTB read accesses
system.cpu1.dtb.write_accesses               76508440                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        160472467                       # DTB hits
system.cpu1.dtb.misses                         115983                       # DTB misses
system.cpu1.dtb.accesses                    160588450                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    60651                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                60651                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          616                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        54731                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        60651                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          60651    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        60651                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        55347                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 21982.528123                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 19135.216139                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 20466.687075                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        53969     97.51%     97.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071         1178      2.13%     99.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607           42      0.08%     99.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           68      0.12%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           60      0.11%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           20      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        55347                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   2053569352                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     2053569352    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   2053569352                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        54731     98.89%     98.89% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          616      1.11%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        55347                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60651                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60651                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55347                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55347                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       115998                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   446979774                       # ITB inst hits
system.cpu1.itb.inst_misses                     60651                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              42080                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   29800                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               447040425                       # ITB inst accesses
system.cpu1.itb.hits                        446979774                       # DTB hits
system.cpu1.itb.misses                          60651                       # DTB misses
system.cpu1.itb.accesses                    447040425                       # DTB accesses
system.cpu1.numCycles                     95053909934                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  446673984                       # Number of instructions committed
system.cpu1.committedOps                    525768473                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            482657433                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                472663                       # Number of float alu accesses
system.cpu1.num_func_calls                   26533376                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     68272280                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   482657433                       # number of integer instructions
system.cpu1.num_fp_insts                       472663                       # number of float instructions
system.cpu1.num_int_register_reads          706740468                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         383340050                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              750974                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             430296                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           118015071                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          117677935                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    160465117                       # number of memory refs
system.cpu1.num_load_insts                   83993061                       # Number of load instructions
system.cpu1.num_store_insts                  76472056                       # Number of store instructions
system.cpu1.num_idle_cycles              93999959015.450027                       # Number of idle cycles
system.cpu1.num_busy_cycles              1053950918.549978                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.011088                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.988912                       # Percentage of idle cycles
system.cpu1.Branches                         99666047                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                364374913     69.26%     69.26% # Class of executed instruction
system.cpu1.op_class::IntMult                 1108574      0.21%     69.47% # Class of executed instruction
system.cpu1.op_class::IntDiv                    57501      0.01%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             68224      0.01%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::MemRead                83993061     15.97%     85.46% # Class of executed instruction
system.cpu1.op_class::MemWrite               76472056     14.54%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 526074372                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   14059                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements          5413042                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          455.092206                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          154856630                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5413554                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            28.605354                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8382280704500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   455.092206                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.888852                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.888852                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          419                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        326337345                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       326337345                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     78172197                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       78172197                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     72471418                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      72471418                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       183858                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       183858                       # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       197039                       # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total       197039                       # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1730902                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1730902                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1704111                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1704111                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    150643615                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       150643615                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    150827473                       # number of overall hits
system.cpu1.dcache.overall_hits::total      150827473                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3026410                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3026410                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1374450                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1374450                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       681215                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       681215                       # number of SoftPFReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       497314                       # number of WriteInvalidateReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::total       497314                       # number of WriteInvalidateReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       177400                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       177400                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       202765                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       202765                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4400860                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4400860                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      5082075                       # number of overall misses
system.cpu1.dcache.overall_misses::total      5082075                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  44105582717                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  44105582717                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  23281173553                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  23281173553                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  13579881027                       # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  13579881027                       # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2688373759                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2688373759                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4348203540                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4348203540                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1867000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1867000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  67386756270                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  67386756270                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  67386756270                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  67386756270                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     81198607                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     81198607                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     73845868                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     73845868                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       865073                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       865073                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       694353                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total       694353                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1908302                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1908302                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1906876                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1906876                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    155044475                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    155044475                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    155909548                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    155909548                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037272                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.037272                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018612                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018612                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.787465                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.787465                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.716226                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.716226                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.092962                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.092962                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106334                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106334                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028385                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.028385                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.032596                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.032596                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14573.564956                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14573.564956                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16938.537999                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 16938.537999                       # average WriteReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27306.452316                       # average WriteInvalidateReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27306.452316                       # average WriteInvalidateReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15154.305293                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15154.305293                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21444.546840                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21444.546840                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15312.179045                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15312.179045                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13259.693387                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13259.693387                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3550271                       # number of writebacks
system.cpu1.dcache.writebacks::total          3550271                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18006                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        18006                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          425                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          425                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44886                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44886                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        18431                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        18431                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        18431                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        18431                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3008404                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      3008404                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1374025                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1374025                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       681215                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       681215                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       497314                       # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       497314                       # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       132514                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       132514                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       202765                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       202765                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4382429                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4382429                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5063644                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5063644                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        21725                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        21725                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        20113                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        20113                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        41838                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        41838                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38446720676                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38446720676                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  21137642197                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  21137642197                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13605784836                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13605784836                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  12830642973                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  12830642973                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1690394742                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1690394742                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4033173960                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4033173960                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1807000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1807000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  59584362873                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  59584362873                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  73190147709                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  73190147709                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3727466501                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3727466501                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3465674500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3465674500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   7193141001                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7193141001                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037050                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037050                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018607                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018607                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.787465                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.787465                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.716226                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.716226                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.069441                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.069441                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106334                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106334                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028266                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.028266                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032478                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.032478                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12779.773154                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12779.773154                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15383.739158                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15383.739158                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19972.820381                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19972.820381                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25799.882917                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25799.882917                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12756.348325                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12756.348325                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19890.878406                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19890.878406                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13596.195825                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13596.195825                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14454.046870                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14454.046870                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171574.982785                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171574.982785                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172310.172525                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172310.172525                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171928.414384                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171928.414384                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          4892397                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.394395                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          442086860                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4892909                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            90.352561                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8382252985250                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.394395                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969520                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969520                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          283                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          151                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        898852462                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       898852462                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    442086860                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      442086860                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    442086860                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       442086860                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    442086860                       # number of overall hits
system.cpu1.icache.overall_hits::total      442086860                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4892914                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4892914                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4892914                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4892914                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4892914                       # number of overall misses
system.cpu1.icache.overall_misses::total      4892914                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  51771462698                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  51771462698                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  51771462698                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  51771462698                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  51771462698                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  51771462698                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    446979774                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    446979774                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    446979774                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    446979774                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    446979774                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    446979774                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.010947                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.010947                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.010947                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.010947                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.010947                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.010947                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10580.905918                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10580.905918                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10580.905918                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10580.905918                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10580.905918                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10580.905918                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4892914                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      4892914                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      4892914                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      4892914                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      4892914                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      4892914                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  46862593334                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  46862593334                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  46862593334                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  46862593334                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  46862593334                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  46862593334                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10105750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10105750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10105750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10105750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.010947                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.010947                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.010947                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.010947                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.010947                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.010947                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9577.645005                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9577.645005                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9577.645005                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  9577.645005                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9577.645005                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  9577.645005                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91870.454545                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91870.454545                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7631682                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7631760                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           35                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       935080                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements         2142260                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13497.078408                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          10799538                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2158371                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            5.003560                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9893608612000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5297.531895                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    78.016993                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    87.104378                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3470.735386                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3768.987855                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   794.701900                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.323336                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004762                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005316                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.211837                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.230041                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.048505                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.823796                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1633                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           75                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14403                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           31                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          128                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          713                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          761                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           32                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           43                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          926                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1571                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5509                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         6302                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.099670                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004578                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.879089                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       240281832                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      240281832                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       248777                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       141659                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      4360207                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data      2869888                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       7620531                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3550270                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3550270                       # number of Writeback hits
system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       228063                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.WriteInvalidateReq_hits::total       228063                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        73786                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        73786                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35221                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        35221                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       953536                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       953536                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       248777                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       141659                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4360207                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3823424                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8574067                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       248777                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       141659                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4360207                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3823424                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8574067                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9961                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7958                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst       532707                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data       952245                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total      1502871                       # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       267701                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::total       267701                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       120750                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       120750                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       167539                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       167539                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       227703                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       227703                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker         9961                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7958                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       532707                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1179948                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1730574                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker         9961                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7958                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       532707                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1179948                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1730574                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    394640977                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    358915726                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  16056528318                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  31264991014                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total  48075076035                       # number of ReadReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data    240883663                       # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total    240883663                       # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2642176746                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   2642176746                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3519293594                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3519293594                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1767000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1767000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   9869071556                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   9869071556                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    394640977                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    358915726                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  16056528318                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  41134062570                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  57944147591                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    394640977                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    358915726                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  16056528318                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  41134062570                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  57944147591                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       258738                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       149617                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      4892914                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3822133                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      9123402                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3550271                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3550271                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       495764                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::total       495764                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       194536                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       194536                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       202760                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       202760                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1181239                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1181239                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       258738                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       149617                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4892914                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      5003372                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10304641                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       258738                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       149617                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4892914                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      5003372                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10304641                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.038498                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.053189                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.108873                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.249140                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.164727                       # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.539977                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.539977                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.620708                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.620708                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.826292                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.826292                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.192766                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.192766                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.038498                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.053189                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.108873                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.235831                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.167941                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.038498                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.053189                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.108873                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.235831                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.167941                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39618.610280                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45101.247298                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30141.387889                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32832.927465                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31988.824081                       # average ReadReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data   899.823546                       # average WriteInvalidateReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total   899.823546                       # average WriteInvalidateReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21881.380919                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21881.380919                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21005.817117                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21005.817117                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       353400                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       353400                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43341.860037                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43341.860037                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39618.610280                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45101.247298                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30141.387889                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34860.911303                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 33482.617670                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39618.610280                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45101.247298                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30141.387889                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34860.911303                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 33482.617670                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1053113                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1053113                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          432                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          432                       # number of ReadReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data            1                       # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total            1                       # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         7197                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         7197                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7629                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         7629                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7629                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         7629                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker         9961                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7958                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       532707                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data       951813                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total      1502439                       # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       707306                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       707306                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data       267700                       # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total       267700                       # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       120750                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       120750                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       167539                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       167539                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       220506                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       220506                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker         9961                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7958                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       532707                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1172319                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1722945                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker         9961                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7958                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       532707                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1172319                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       707306                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2430251                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        21725                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        21835                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        20113                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        20113                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        41838                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        41948                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    329233523                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    306561274                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  12577785182                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  24989286886                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  38202866865                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  35407537019                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  35407537019                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   9092223824                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   9092223824                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2448079564                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2448079564                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2512705540                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2512705540                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1507000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1507000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7591763498                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7591763498                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    329233523                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    306561274                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  12577785182                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  32581050384                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  45794630363                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    329233523                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    306561274                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  12577785182                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  32581050384                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  35407537019                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  81202167382                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9241250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3553660750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3562902000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3314826000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3314826000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9241250                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   6868486750                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   6877728000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.038498                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.053189                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.108873                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.249027                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.164680                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.539975                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.539975                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.620708                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.620708                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.826292                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.826292                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.186673                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.186673                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.038498                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.053189                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.108873                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234306                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.167201                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.038498                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.053189                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.108873                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234306                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.235840                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23611.075473                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26254.408047                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25427.233229                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50059.715341                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33964.227957                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33964.227957                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20273.950841                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20273.950841                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14997.735095                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14997.735095                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       301400                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       301400                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34428.829592                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34428.829592                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23611.075473                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27791.966507                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26579.275811                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23611.075473                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27791.966507                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33413.078477                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163574.718067                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163173.895123                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164810.122806                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164810.122806                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164168.620632                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163958.424716                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq      11407818                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9339972                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        38146                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        20113                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      3550271                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq      1013669                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1157980                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       495764                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       395206                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       367201                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       457834                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           51                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           86                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1341582                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1187599                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      9786048                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15579584                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       330806                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       594855                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         26291293                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    313146936                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    585201818                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1196936                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      2069904                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         901615594                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    4634762                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     19271924                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.253755                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.435159                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1          14381570     74.62%     74.62% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2           4890354     25.38%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      19271924                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   11505600998                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    168563993                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7347478432                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   8042476622                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    181503274                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    336447522                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40366                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40366                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136641                       # Transaction distribution
system.iobus.trans_dist::WriteResp              29913                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47782                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122716                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231218                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231218                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354014                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47802                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155823                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496797                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36274000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           607607215                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92806000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148515621                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170500                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115613                       # number of replacements
system.iocache.tags.tagsinuse               11.298152                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115629                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9179138787000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.392909                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.905243                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.462057                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.244078                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706135                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040838                       # Number of tag accesses
system.iocache.tags.data_accesses             1040838                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8881                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8918                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8881                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8921                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8881                       # number of overall misses
system.iocache.overall_misses::total             8921                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5195500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1629816861                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1635012361                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19901379733                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  19901379733                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5564500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1629816861                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1635381361                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5564500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1629816861                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1635381361                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8881                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8918                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8881                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8921                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8881                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8921                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 183517.268438                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 183338.457165                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186468.215773                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 186468.215773                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 183517.268438                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 183318.166237                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 183517.268438                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 183318.166237                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        110961                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                16203                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.848176                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106702                       # number of writebacks
system.iocache.writebacks::total               106702                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8881                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8918                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106728                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106728                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8881                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8921                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8881                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8921                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3270500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1166890035                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1170160535                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       213000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       213000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14351455801                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14351455801                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3483500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1166890035                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1170373535                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3483500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1166890035                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1170373535                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131391.739106                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 131213.336510                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        71000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        71000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134467.579276                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134467.579276                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 131391.739106                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 131193.087658                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 131391.739106                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 131193.087658                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1448041                       # number of replacements
system.l2c.tags.tagsinuse                64131.287175                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4245095                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1507106                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.816720                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              11172879000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   19347.050639                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   116.894544                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   154.865125                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3200.431152                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     7856.746302                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  9704.320174                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   227.109782                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   297.906768                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3324.337079                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     8639.334854                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11262.290757                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.295213                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001784                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.002363                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.048835                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.119884                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.148076                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003465                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.004546                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.050725                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.131826                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.171849                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.978566                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10716                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          318                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        48031                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2           38                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          439                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        10237                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          318                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1326                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4887                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        41702                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.163513                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.004852                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.732895                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 58352089                       # Number of tag accesses
system.l2c.tags.data_accesses                58352089                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         5485                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4305                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             465111                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             536784                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       265347                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         5257                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         3875                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             485070                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             556488                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher       285641                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2613363                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         2374848                       # number of Writeback hits
system.l2c.Writeback_hits::total              2374848                       # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data       123464                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data       121626                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total       245090                       # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data           24332                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           31013                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               55345                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          5518                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          6203                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             11721                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            54595                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            49708                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               104303                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5485                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4305                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              465111                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              591379                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       265347                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5257                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3875                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              485070                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              606196                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       285641                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2717666                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5485                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4305                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             465111                       # number of overall hits
system.l2c.overall_hits::cpu0.data             591379                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       265347                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5257                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3875                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             485070                       # number of overall hits
system.l2c.overall_hits::cpu1.data             606196                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       285641                       # number of overall hits
system.l2c.overall_hits::total                2717666                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1889                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1930                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            50597                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           131294                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       216525                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2185                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2247                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst            47637                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data           122248                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       240093                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               816645                       # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data       431801                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data       136823                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total       568624                       # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data         44180                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         43907                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             88087                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         9646                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        11002                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           20648                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          78703                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          53921                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             132624                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1889                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1930                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             50597                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            209997                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       216525                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2185                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2247                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             47637                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            176169                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       240093                       # number of demand (read+write) misses
system.l2c.demand_misses::total                949269                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1889                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1930                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            50597                       # number of overall misses
system.l2c.overall_misses::cpu0.data           209997                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       216525                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2185                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2247                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            47637                       # number of overall misses
system.l2c.overall_misses::cpu1.data           176169                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       240093                       # number of overall misses
system.l2c.overall_misses::total               949269                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    170785750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    176668500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   4301026862                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  11907133634                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  27854403488                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    192678771                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    202084771                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst   4020493910                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data  11059922872                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  30832642419                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    90717840977                       # number of ReadReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu0.data     51822854                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu1.data     41218687                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::total     93041541                       # number of WriteInvalidateReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    233428095                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    271641854                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    505069949                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     51474876                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     56093222                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    107568098                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6900295884                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4492674608                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  11392970492                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    170785750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    176668500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   4301026862                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  18807429518                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  27854403488                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    192678771                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    202084771                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   4020493910                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  15552597480                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  30832642419                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    102110811469                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    170785750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    176668500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   4301026862                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  18807429518                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  27854403488                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    192678771                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    202084771                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   4020493910                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  15552597480                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  30832642419                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   102110811469                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         7374                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6235                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         515708                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         668078                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       481872                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         7442                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6122                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         532707                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         678736                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher       525734                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            3430008                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      2374848                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2374848                       # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data       555265                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data       258449                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total       813714                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        68512                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        74920                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          143432                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        15164                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        17205                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         32369                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       133298                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       103629                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           236927                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         7374                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6235                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          515708                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          801376                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       481872                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         7442                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6122                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          532707                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          782365                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       525734                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             3666935                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         7374                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6235                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         515708                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         801376                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       481872                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         7442                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6122                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         532707                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         782365                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       525734                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            3666935                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.256170                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.309543                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.098112                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.196525                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.293604                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.367037                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.089424                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.180111                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.238088                       # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.777649                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.529400                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total     0.698801                       # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.644851                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.586052                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.614138                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.636112                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.639465                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.637894                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.590429                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.520327                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.559767                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.256170                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.309543                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.098112                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.262046                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.293604                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.367037                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.089424                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.225175                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.258873                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.256170                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.309543                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.098112                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.262046                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.293604                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.367037                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.089424                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.225175                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.258873                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90410.667020                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91538.082902                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85005.570726                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 90690.615215                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88182.503890                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89935.367601                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84398.553855                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 90471.196846                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 111086.017764                       # average ReadReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   120.015595                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   301.255542                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::total   163.625772                       # average WriteInvalidateReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5283.569375                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6186.755050                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5733.762632                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5336.396019                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5098.456826                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5209.613425                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87675.131621                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83319.571373                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 85904.289510                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90410.667020                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91538.082902                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 85005.570726                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 89560.467616                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88182.503890                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89935.367601                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 84398.553855                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 88282.260103                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 107567.835323                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90410.667020                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91538.082902                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 85005.570726                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 89560.467616                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88182.503890                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89935.367601                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 84398.553855                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 88282.260103                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 107567.835323                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               328                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       14                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     23.428571                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1121159                       # number of writebacks
system.l2c.writebacks::total                  1121159                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst           120                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            25                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst           120                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            30                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               296                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            120                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             25                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            120                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             30                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                296                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           120                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            25                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker            1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           120                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            30                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               296                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1889                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1930                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        50477                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       131269                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       216525                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2184                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2247                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst        47517                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data       122218                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       240093                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          816349                       # number of ReadReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data       431801                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data       136823                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::total       568624                       # number of WriteInvalidateReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        44180                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        43907                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        88087                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9646                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11002                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        20648                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        78703                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        53921                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        132624                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1889                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1930                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        50477                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       209972                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       216525                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2184                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2247                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        47517                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       176139                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       240093                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           948973                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1889                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1930                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        50477                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       209972                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       216525                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2184                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2247                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        47517                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       176139                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       240093                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          948973                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16584                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        21723                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        81542                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        18033                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        20113                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38146                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        34617                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        41836                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       119688                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    146937750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    152273500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   3658828888                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10259837116                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  25193281260                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    165099729                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    173733729                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   3415229090                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data   9525126628                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  27878676483                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  80569024173                       # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data  13996588148                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   4310102313                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total  18306690461                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    786063539                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    780665261                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1566728800                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    172133111                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    196209961                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    368343072                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5916837616                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3817995892                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   9734833508                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    146937750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    152273500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   3658828888                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  16176674732                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  25193281260                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    165099729                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    173733729                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   3415229090                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  13343122520                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  27878676483                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  90303857681                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    146937750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    152273500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   3658828888                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  16176674732                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  25193281260                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    165099729                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    173733729                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   3415229090                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  13343122520                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  27878676483                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  90303857681                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2605759500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2243809000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7049250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3129187250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7985805000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2322501000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2942063000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5264564000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2605759500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4566310000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7049250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6071250250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13250369000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.256170                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.309543                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.097879                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.196488                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.293469                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.367037                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.089199                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.180067                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.238002                       # mshr miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.777649                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.529400                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.698801                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.644851                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.586052                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.614138                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.636112                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.639465                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.637894                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.590429                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.520327                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.559767                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.256170                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.309543                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.097879                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.262014                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.293469                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.367037                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.089199                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.225137                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.258792                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.256170                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.309543                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.097879                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.262014                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.449341                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.293469                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.367037                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.089199                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.225137                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456682                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.258792                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72485.070190                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78158.873123                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71873.836522                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77935.546548                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 98694.338050                       # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32414.441254                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31501.299584                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32194.719992                       # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17792.293775                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17779.972692                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.152327                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.024984                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17834.026632                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.164665                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75179.314842                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70807.215964                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 73401.748613                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72485.070190                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77042.056712                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71873.836522                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75753.368192                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 95159.564794                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72485.070190                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77042.056712                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71873.836522                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75753.368192                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 95159.564794                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 135299.626146                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144049.498228                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97934.867921                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 128791.715189                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146276.686720                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138010.905468                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 131909.466447                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145120.237355                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 110707.581378                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              906809                       # Transaction distribution
system.membus.trans_dist::ReadResp             906809                       # Transaction distribution
system.membus.trans_dist::WriteReq              38146                       # Transaction distribution
system.membus.trans_dist::WriteResp             38146                       # Transaction distribution
system.membus.trans_dist::Writeback           1227861                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       672387                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       672387                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           370275                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         320224                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          115346                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq           24                       # Transaction distribution
system.membus.trans_dist::ReadExReq            145002                       # Transaction distribution
system.membus.trans_dist::ReadExResp           128981                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122716                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24970                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5055890                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5203668                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335590                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       335590                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5539258                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155823                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49940                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    168605292                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    168811259                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14076224                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14076224                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               182887483                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           594337                       # Total snoops (count)
system.membus.snoop_fanout::samples           3681134                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3681134    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3681134                       # Request fanout histogram
system.membus.reqLayer0.occupancy           100790999                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               55000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21573500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         11112792344                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5991933811                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          151912879                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            4327568                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4320333                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38146                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38146                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          2374848                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq       920665                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp       813714                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          419012                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        331945                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         750957                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           86                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           86                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           292509                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          292509                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7096014                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6270717                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              13366731                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    236480377                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    202778754                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              439259131                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1555479                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          8704899                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.013311                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.114603                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                8589027     98.67%     98.67% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 115872      1.33%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            8704899                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         7795939791                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2526000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3978610795                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3846379763                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------