path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.832459                       # Number of seconds simulated
sim_ticks                                51832458543500                       # Number of ticks simulated
final_tick                               51832458543500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 536175                       # Simulator instruction rate (inst/s)
host_op_rate                                   630049                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            31477440084                       # Simulator tick rate (ticks/s)
host_mem_usage                                 712068                       # Number of bytes of host memory used
host_seconds                                  1646.65                       # Real time elapsed on the host
sim_insts                                   882895003                       # Number of instructions simulated
sim_ops                                    1037473525                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       255168                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       250176                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           5270964                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          81048392                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        390144                       # Number of bytes read from this memory
system.physmem.bytes_read::total             87214844                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      5270964                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5270964                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     75813760                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          75834340                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         3987                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         3909                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             122766                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1266394                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6096                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1403152                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1184590                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1187163                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           4923                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           4827                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               101692                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1563661                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7527                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1682630                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          101692                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             101692                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1462670                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 397                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1463067                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1462670                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          4923                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          4827                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              101692                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1564058                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7527                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3145697                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1403152                       # Number of read requests accepted
system.physmem.writeReqs                      1187163                       # Number of write requests accepted
system.physmem.readBursts                     1403152                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1187163                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 89743360                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     58368                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  75832768                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  87214844                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               75834340                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      912                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2250                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         142509                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               84707                       # Per bank write bursts
system.physmem.perBankRdBursts::1               87220                       # Per bank write bursts
system.physmem.perBankRdBursts::2               81347                       # Per bank write bursts
system.physmem.perBankRdBursts::3               82774                       # Per bank write bursts
system.physmem.perBankRdBursts::4               86841                       # Per bank write bursts
system.physmem.perBankRdBursts::5               98270                       # Per bank write bursts
system.physmem.perBankRdBursts::6               81495                       # Per bank write bursts
system.physmem.perBankRdBursts::7               83122                       # Per bank write bursts
system.physmem.perBankRdBursts::8               79285                       # Per bank write bursts
system.physmem.perBankRdBursts::9              129613                       # Per bank write bursts
system.physmem.perBankRdBursts::10              85444                       # Per bank write bursts
system.physmem.perBankRdBursts::11              88159                       # Per bank write bursts
system.physmem.perBankRdBursts::12              83519                       # Per bank write bursts
system.physmem.perBankRdBursts::13              84779                       # Per bank write bursts
system.physmem.perBankRdBursts::14              82284                       # Per bank write bursts
system.physmem.perBankRdBursts::15              83381                       # Per bank write bursts
system.physmem.perBankWrBursts::0               72521                       # Per bank write bursts
system.physmem.perBankWrBursts::1               74576                       # Per bank write bursts
system.physmem.perBankWrBursts::2               72526                       # Per bank write bursts
system.physmem.perBankWrBursts::3               74694                       # Per bank write bursts
system.physmem.perBankWrBursts::4               74615                       # Per bank write bursts
system.physmem.perBankWrBursts::5               83452                       # Per bank write bursts
system.physmem.perBankWrBursts::6               71356                       # Per bank write bursts
system.physmem.perBankWrBursts::7               73404                       # Per bank write bursts
system.physmem.perBankWrBursts::8               69434                       # Per bank write bursts
system.physmem.perBankWrBursts::9               76014                       # Per bank write bursts
system.physmem.perBankWrBursts::10              73389                       # Per bank write bursts
system.physmem.perBankWrBursts::11              75855                       # Per bank write bursts
system.physmem.perBankWrBursts::12              72723                       # Per bank write bursts
system.physmem.perBankWrBursts::13              74909                       # Per bank write bursts
system.physmem.perBankWrBursts::14              71861                       # Per bank write bursts
system.physmem.perBankWrBursts::15              73558                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
system.physmem.totGap                    51832455911500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1360036                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1184590                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1369724                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     26989                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       402                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       311                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       443                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       479                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       493                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       784                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       854                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      363                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      161                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      142                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      120                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      110                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       91                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       88                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       47                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    15525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    18184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    68862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    70049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    70008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    69966                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    69777                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    72690                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    73075                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    75585                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    74412                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    74484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    71661                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    71703                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    72226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    69733                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    69498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    68867                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      515                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      431                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      399                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      395                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      361                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       47                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       564142                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      293.500232                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     169.709934                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     326.462784                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         227896     40.40%     40.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       137874     24.44%     64.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        50148      8.89%     73.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        27962      4.96%     78.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        20021      3.55%     82.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        14110      2.50%     84.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        11549      2.05%     86.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        10920      1.94%     88.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        63662     11.28%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         564142                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         68197                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.561359                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      299.455370                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          68195    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           68197                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         68197                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.374474                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.924162                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.358180                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           65696     96.33%     96.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             133      0.20%     96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             441      0.65%     97.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             195      0.29%     97.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             359      0.53%     97.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             498      0.73%     98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             123      0.18%     98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              30      0.04%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              34      0.05%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              28      0.04%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              38      0.06%     99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              22      0.03%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             434      0.64%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              35      0.05%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              41      0.06%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              27      0.04%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               4      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            26      0.04%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             5      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           68197                       # Writes before turning the bus around for reads
system.physmem.totQLat                    16916842552                       # Total ticks spent queuing
system.physmem.totMemAccLat               43208842552                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   7011200000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12064.16                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30814.16                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.73                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.46                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.68                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.46                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.64                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1132918                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    890066                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.79                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.12                       # Row buffer hit rate for writes
system.physmem.avgGap                     20010097.58                       # Average gap between requests
system.physmem.pageHitRate                      78.19                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2149066080                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1172605500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                5349013800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3869493120                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3385443743760                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1308122393760                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29951995045500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34658101361520                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.656420                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49827055945457                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1730799460000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    274602731543                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2115847440                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1154480250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                5588419200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3808574640                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3385443743760                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1306419956235                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29953488411750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34658019433275                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.654839                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49829529145116                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1730799460000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    272122791134                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    207675                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                207675                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15981                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       160171                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore           22                       # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples       207653                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean     0.182998                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev    62.840123                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-2047       207651    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       207653                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       176174                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 24712.505818                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 21157.403643                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 15094.851220                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767       111064     63.04%     63.04% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-65535        63199     35.87%     98.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-98303          999      0.57%     99.48% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-131071          662      0.38%     99.86% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839           15      0.01%     99.87% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::163840-196607           88      0.05%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-229375           11      0.01%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::229376-262143           50      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-294911           52      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::294912-327679           13      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-360447            8      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::360448-393215            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       176174                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples   -781821628                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean     0.029012                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev     0.167839                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0      -759139796     97.10%     97.10% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::1       -22681832      2.90%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total   -781821628                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        160172     90.93%     90.93% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         15981      9.07%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       176153                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       207675                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       207675                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       176153                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       176153                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       383828                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    165829611                       # DTB read hits
system.cpu.dtb.read_misses                     153241                       # DTB read misses
system.cpu.dtb.write_hits                   150793131                       # DTB write hits
system.cpu.dtb.write_misses                     54434                       # DTB write misses
system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               42000                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1055                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    75015                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   8164                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     19719                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                165982852                       # DTB read accesses
system.cpu.dtb.write_accesses               150847565                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         316622742                       # DTB hits
system.cpu.dtb.misses                          207675                       # DTB misses
system.cpu.dtb.accesses                     316830417                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    122431                       # Table walker walks requested
system.cpu.itb.walker.walksLong                122431                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1128                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       110257                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       122431                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          122431    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       122431                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       111385                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28118.386677                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24591.122191                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 17995.361080                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       109197     98.04%     98.04% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071         1895      1.70%     99.74% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607          129      0.12%     99.85% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           78      0.07%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679           51      0.05%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           19      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       111385                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples   -887504296                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0      -887504296    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total   -887504296                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        110257     98.99%     98.99% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1128      1.01%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       111385                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       122431                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       122431                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       111385                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       111385                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       233816                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    883439249                       # ITB inst hits
system.cpu.itb.inst_misses                     122431                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               42000                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1055                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    53485                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                883561680                       # ITB inst accesses
system.cpu.itb.hits                         883439249                       # DTB hits
system.cpu.itb.misses                          122431                       # DTB misses
system.cpu.itb.accesses                     883561680                       # DTB accesses
system.cpu.numCycles                     103664917087                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   882895003                       # Number of instructions committed
system.cpu.committedOps                    1037473525                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             952709754                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 896425                       # Number of float alu accesses
system.cpu.num_func_calls                    52419949                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    134729686                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    952709754                       # number of integer instructions
system.cpu.num_fp_insts                        896425                       # number of float instructions
system.cpu.num_int_register_reads          1388360502                       # number of times the integer registers were read
system.cpu.num_int_register_writes          755717952                       # number of times the integer registers were written
system.cpu.num_fp_register_reads              1444442                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              761348                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            231664947                       # number of times the CC registers were read
system.cpu.num_cc_register_writes           231068644                       # number of times the CC registers were written
system.cpu.num_mem_refs                     316605789                       # number of memory refs
system.cpu.num_load_insts                   165822487                       # Number of load instructions
system.cpu.num_store_insts                  150783302                       # Number of store instructions
system.cpu.num_idle_cycles               100487560505.254059                       # Number of idle cycles
system.cpu.num_busy_cycles               3177356581.745939                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.030650                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.969350                       # Percentage of idle cycles
system.cpu.Branches                         197184546                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                 719043510     69.27%     69.27% # Class of executed instruction
system.cpu.op_class::IntMult                  2202813      0.21%     69.48% # Class of executed instruction
system.cpu.op_class::IntDiv                     97927      0.01%     69.49% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc             110813      0.01%     69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.50% # Class of executed instruction
system.cpu.op_class::MemRead                165822487     15.97%     85.47% # Class of executed instruction
system.cpu.op_class::MemWrite               150783302     14.53%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                 1038060895                       # Class of executed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    19158                       # number of quiesce instructions executed
system.cpu.dcache.tags.replacements          10067650                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.966034                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           306351638                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          10068162                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             30.427762                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        3466781500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.966034                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999934                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999934                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          401                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1276220350                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1276220350                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    154968992                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       154968992                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    143085243                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      143085243                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       390390                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        390390                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       335374                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       335374                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3613361                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3613361                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      3913213                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      3913213                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     298054235                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        298054235                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    298444625                       # number of overall hits
system.cpu.dcache.overall_hits::total       298444625                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      5249224                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       5249224                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2178798                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2178798                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1272425                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1272425                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1229487                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1229487                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       301533                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       301533                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      7428022                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        7428022                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      8700447                       # number of overall misses
system.cpu.dcache.overall_misses::total       8700447                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  82824595500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  82824595500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  63552242000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  63552242000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  50841662000                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  50841662000                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4423231500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   4423231500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 146376837500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 146376837500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 146376837500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 146376837500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    160218216                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    160218216                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    145264041                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    145264041                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1662815                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1662815                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1564861                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1564861                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3914894                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      3914894                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      3913214                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      3913214                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    305482257                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    305482257                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    307145072                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    307145072                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032763                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.032763                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014999                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.014999                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.765223                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.765223                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.785684                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.785684                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.077022                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.077022                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.024316                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.024316                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.028327                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.028327                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15778.445633                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15778.445633                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29168.487395                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29168.487395                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 41351.931334                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 41351.931334                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14669.145666                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14669.145666                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19706.031767                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19706.031767                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16824.059442                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16824.059442                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      7760504                       # number of writebacks
system.cpu.dcache.writebacks::total           7760504                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        23609                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        23609                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21261                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        21261                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        71576                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        71576                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        44870                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        44870                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        44870                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        44870                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5225615                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5225615                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2157537                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2157537                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1270654                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1270654                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1229487                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1229487                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       229957                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       229957                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      7383152                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      7383152                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      8653806                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      8653806                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33706                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33706                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33710                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67416                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67416                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  77028808000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  77028808000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  60744856000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  60744856000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20507265000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20507265000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  49612175000                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  49612175000                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3074046500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3074046500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        81000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137773664000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 137773664000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 158280929000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 158280929000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5831352000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5831352000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5695270000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5695270000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11526622000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11526622000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032616                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032616                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014853                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014853                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.764158                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.764158                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.785684                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.785684                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.058739                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.058739                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024169                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024169                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028175                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.028175                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14740.620578                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14740.620578                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28154.722723                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28154.722723                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16139.141733                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16139.141733                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 40351.931334                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 40351.931334                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13367.918785                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13367.918785                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18660.548232                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18660.548232                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18290.325552                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18290.325552                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173006.349018                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173006.349018                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168948.976565                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168948.976565                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170977.542423                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170977.542423                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          13898073                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.854844                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           869540659                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          13898585                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             62.563251                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       43284980500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.854844                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999716                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999716                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          248                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          195                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         897337839                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        897337839                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    869540659                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       869540659                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     869540659                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        869540659                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    869540659                       # number of overall hits
system.cpu.icache.overall_hits::total       869540659                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     13898590                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      13898590                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     13898590                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       13898590                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     13898590                       # number of overall misses
system.cpu.icache.overall_misses::total      13898590                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 186400133500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 186400133500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 186400133500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 186400133500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 186400133500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 186400133500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    883439249                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    883439249                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    883439249                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    883439249                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    883439249                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    883439249                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015732                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.015732                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.015732                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.015732                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.015732                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.015732                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13411.441988                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13411.441988                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13411.441988                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13411.441988                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13411.441988                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13411.441988                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13898590                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     13898590                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     13898590                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     13898590                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     13898590                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     13898590                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 172501543500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 172501543500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 172501543500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 172501543500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 172501543500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 172501543500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3229158000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3229158000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   3229158000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   3229158000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.015732                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.015732                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.015732                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.015732                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.015732                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.015732                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12411.441988                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12411.441988                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12411.441988                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12411.441988                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12411.441988                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12411.441988                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74879.026087                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74879.026087                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74879.026087                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74879.026087                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1262077                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65231.896667                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           43818011                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1325564                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            33.056126                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      38337641500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 38267.922304                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   322.380584                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   465.537699                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  6521.520612                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19654.535467                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.583922                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004919                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007104                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.099511                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.299904                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995360                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          334                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63153                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          334                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          404                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2433                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5488                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54788                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.005096                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.963638                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        393503422                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       393503422                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       363149                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       250594                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         613743                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      7760504                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      7760504                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         9779                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         9779                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1625617                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1625617                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     13818912                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     13818912                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6453062                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6453062                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       721925                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       721925                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       363149                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       250594                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     13818912                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8078679                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        22511334                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       363149                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       250594                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     13818912                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8078679                       # number of overall hits
system.cpu.l2cache.overall_hits::total       22511334                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3987                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3909                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         7896                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        35285                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        35285                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       486856                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       486856                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        79678                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        79678                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       273164                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       273164                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       507562                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       507562                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         3987                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         3909                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        79678                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       760020                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        847594                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         3987                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         3909                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        79678                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       760020                       # number of overall misses
system.cpu.l2cache.overall_misses::total       847594                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    341850000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    340742500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    682592500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    544841000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    544841000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        79500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        79500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  39254870000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  39254870000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   6511661500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   6511661500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  22761554500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  22761554500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  40187730500                       # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total  40187730500                       # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    341850000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    340742500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   6511661500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  62016424500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  69210678500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    341850000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    340742500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   6511661500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  62016424500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  69210678500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       367136                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       254503                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       621639                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      7760504                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      7760504                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        45064                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        45064                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2112473                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2112473                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     13898590                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     13898590                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6726226                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      6726226                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1229487                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1229487                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       367136                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       254503                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     13898590                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      8838699                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     23358928                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       367136                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       254503                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     13898590                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      8838699                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     23358928                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.010860                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.015359                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.012702                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782998                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782998                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.230467                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.230467                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005733                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005733                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.040612                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.040612                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.412824                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.412824                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.010860                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.015359                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005733                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.085988                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.036286                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.010860                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.015359                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005733                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.085988                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.036286                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85741.158766                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87168.713226                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 86447.885005                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15441.150631                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15441.150631                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80629.323660                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80629.323660                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81724.710711                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81724.710711                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83325.601104                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83325.601104                       # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 79177.973331                       # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 79177.973331                       # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85741.158766                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87168.713226                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81724.710711                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81598.411226                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81655.460633                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85741.158766                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87168.713226                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81724.710711                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81598.411226                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81655.460633                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1077959                       # number of writebacks
system.cpu.l2cache.writebacks::total          1077959                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3987                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3909                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         7896                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1116                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         1116                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        35285                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        35285                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       486856                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       486856                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        79678                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        79678                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       273164                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       273164                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       507562                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       507562                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3987                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3909                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        79678                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       760020                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       847594                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3987                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3909                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        79678                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       760020                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       847594                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33706                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        76831                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33710                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67416                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       110541                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    301980000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    301652500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    603632500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    728816500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    728816500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        69500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        69500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  34386310000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  34386310000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   5714881500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   5714881500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  20029914500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  20029914500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  35112110500                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  35112110500                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    301980000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    301652500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5714881500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  54416224500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  60734738500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    301980000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    301652500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5714881500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  54416224500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  60734738500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2690095500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5410027000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8100122500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5307605000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5307605000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2690095500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10717632000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13407727500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.010860                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.015359                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.012702                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782998                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782998                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.230467                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.230467                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005733                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005733                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.040612                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.040612                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.412824                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.412824                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.010860                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.015359                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005733                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.085988                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.036286                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.010860                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.015359                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005733                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.085988                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.036286                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77168.713226                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76447.885005                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20655.136744                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20655.136744                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70629.323660                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70629.323660                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71724.710711                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71724.710711                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73325.601104                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73325.601104                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69177.973331                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69177.973331                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77168.713226                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71724.710711                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71598.411226                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71655.460633                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77168.713226                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71724.710711                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71598.411226                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71655.460633                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62379.026087                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160506.349018                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105427.789564                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157448.976565                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157448.976565                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62379.026087                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158977.572090                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 121291.896220                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        1048560                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      21674258                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33710                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33710                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      8945109                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict     16396444                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        45067                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        45068                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2112473                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2112473                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     13898590                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      6735107                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1336151                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1229487                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41779933                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     30429687                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       620392                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       972976                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          73802988                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    889682260                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1062595910                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2036024                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2937088                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         1957251282                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1844105                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     50552964                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.048758                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.215362                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1           48088105     95.12%     95.12% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2            2464859      4.88%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       50552964                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    32307276000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1324500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   20891010000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13945928913                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     365889000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     605840000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40329                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40329                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231016                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231016                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353800                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334496                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334496                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492416                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           568778648                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147776000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115490                       # number of replacements
system.iocache.tags.tagsinuse               10.455215                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115506                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13165278431000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.510021                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.945193                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219376                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.434075                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653451                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039929                       # Number of tag accesses
system.iocache.tags.data_accesses             1039929                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8844                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8881                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8844                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8884                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8844                       # number of overall misses
system.iocache.overall_misses::total             8884                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1566099238                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1571168238                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12612607410                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12612607410                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1566099238                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1571519238                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1566099238                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1571519238                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8844                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8881                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8844                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8884                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8844                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8884                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 177080.420398                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 176913.437451                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118246.150623                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118246.150623                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 177080.420398                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 176893.205538                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 177080.420398                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 176893.205538                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         29516                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3281                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.996038                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8844                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8881                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8844                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8884                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8844                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8884                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1123899238                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1127118238                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7279407410                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7279407410                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1123899238                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1127319238                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1123899238                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1127319238                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127080.420398                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 126913.437451                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68246.150623                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68246.150623                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 127080.420398                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 126893.205538                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 127080.420398                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 126893.205538                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               76831                       # Transaction distribution
system.membus.trans_dist::ReadResp             446450                       # Transaction distribution
system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
system.membus.trans_dist::Writeback           1184590                       # Transaction distribution
system.membus.trans_dist::CleanEvict           190005                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            35851                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           35852                       # Transaction distribution
system.membus.trans_dist::ReadExReq            993855                       # Transaction distribution
system.membus.trans_dist::ReadExResp           993855                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        369619                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4133679                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4263383                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       340829                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       340829                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4604212                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    155834656                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    156004506                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7214528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7214528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               163219034                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3445                       # Total snoops (count)
system.membus.snoop_fanout::samples           2994110                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2994110    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2994110                       # Request fanout histogram
system.membus.reqLayer0.occupancy           107330000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5385500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          7724756059                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7445249237                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          228975298                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks

---------- End Simulation Statistics   ----------