path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.824462                       # Number of seconds simulated
sim_ticks                                51824462100500                       # Number of ticks simulated
final_tick                               51824462100500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 723017                       # Simulator instruction rate (inst/s)
host_op_rate                                   849578                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            41937024652                       # Simulator tick rate (ticks/s)
host_mem_usage                                 712044                       # Number of bytes of host memory used
host_seconds                                  1235.77                       # Real time elapsed on the host
sim_insts                                   893481288                       # Number of instructions simulated
sim_ops                                    1049881338                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       266048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       259456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           5261620                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          50351624                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        398272                       # Number of bytes read from this memory
system.physmem.bytes_read::total             56537020                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      5261620                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5261620                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     77705792                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          77726372                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         4157                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         4054                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             122620                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             786757                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6223                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                923811                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1214153                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1216726                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           5134                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           5006                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               101528                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               971580                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7685                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1090933                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          101528                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             101528                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1499404                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 397                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1499801                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1499404                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          5134                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          5006                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              101528                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              971977                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7685                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2590734                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        923811                       # Number of read requests accepted
system.physmem.writeReqs                      1833124                       # Number of write requests accepted
system.physmem.readBursts                      923811                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1833124                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 59092736                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     31168                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 114062016                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  56537020                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              117175844                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      487                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   50880                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          36215                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               57129                       # Per bank write bursts
system.physmem.perBankRdBursts::1               60965                       # Per bank write bursts
system.physmem.perBankRdBursts::2               52485                       # Per bank write bursts
system.physmem.perBankRdBursts::3               50413                       # Per bank write bursts
system.physmem.perBankRdBursts::4               54002                       # Per bank write bursts
system.physmem.perBankRdBursts::5               59718                       # Per bank write bursts
system.physmem.perBankRdBursts::6               51713                       # Per bank write bursts
system.physmem.perBankRdBursts::7               51669                       # Per bank write bursts
system.physmem.perBankRdBursts::8               50247                       # Per bank write bursts
system.physmem.perBankRdBursts::9              101235                       # Per bank write bursts
system.physmem.perBankRdBursts::10              59848                       # Per bank write bursts
system.physmem.perBankRdBursts::11              58323                       # Per bank write bursts
system.physmem.perBankRdBursts::12              55369                       # Per bank write bursts
system.physmem.perBankRdBursts::13              55988                       # Per bank write bursts
system.physmem.perBankRdBursts::14              51743                       # Per bank write bursts
system.physmem.perBankRdBursts::15              52477                       # Per bank write bursts
system.physmem.perBankWrBursts::0              110630                       # Per bank write bursts
system.physmem.perBankWrBursts::1              112240                       # Per bank write bursts
system.physmem.perBankWrBursts::2              108805                       # Per bank write bursts
system.physmem.perBankWrBursts::3              108103                       # Per bank write bursts
system.physmem.perBankWrBursts::4              111102                       # Per bank write bursts
system.physmem.perBankWrBursts::5              113339                       # Per bank write bursts
system.physmem.perBankWrBursts::6              105567                       # Per bank write bursts
system.physmem.perBankWrBursts::7              107723                       # Per bank write bursts
system.physmem.perBankWrBursts::8              108849                       # Per bank write bursts
system.physmem.perBankWrBursts::9              115780                       # Per bank write bursts
system.physmem.perBankWrBursts::10             115663                       # Per bank write bursts
system.physmem.perBankWrBursts::11             113049                       # Per bank write bursts
system.physmem.perBankWrBursts::12             112494                       # Per bank write bursts
system.physmem.perBankWrBursts::13             116984                       # Per bank write bursts
system.physmem.perBankWrBursts::14             111502                       # Per bank write bursts
system.physmem.perBankWrBursts::15             110389                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         145                       # Number of times write queue was full causing retry
system.physmem.totGap                    51824459475500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  880695                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1830551                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    889155                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     28186                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       257                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       284                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       462                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       528                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       455                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       746                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       480                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1765                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      152                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      105                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       92                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    57524                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    60978                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    91825                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   117209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   106855                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    97040                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    98714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    93369                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    94185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    92986                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    93402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    98737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    96397                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    94916                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   105152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    97025                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    94048                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    92817                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     5441                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     5084                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     5738                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     7709                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     7730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     6924                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     6738                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     7452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     5737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     5138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     4676                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     5004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     4547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     3838                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     3903                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     3022                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     2209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      847                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      643                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      513                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      524                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      509                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      329                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       603787                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      286.780656                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     164.845955                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     326.273004                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         251324     41.62%     41.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       149673     24.79%     66.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        51779      8.58%     74.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        28017      4.64%     79.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        19714      3.27%     82.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        13055      2.16%     85.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         9885      1.64%     86.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         8959      1.48%     88.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        71381     11.82%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         603787                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         89136                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        10.358104                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      107.922360                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          89134    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           89136                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         89136                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.994379                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.728374                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       17.051434                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31           87330     97.97%     97.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47             694      0.78%     98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              23      0.03%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              47      0.05%     98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95             149      0.17%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111            187      0.21%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127           322      0.36%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143           118      0.13%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            42      0.05%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175            12      0.01%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            62      0.07%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            32      0.04%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            11      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             9      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             3      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             6      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319            11      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335            10      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             8      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            26      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             5      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::432-447             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::464-479             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             4      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-655             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-687             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::688-703             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-719             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           89136                       # Writes before turning the bus around for reads
system.physmem.totQLat                    12043609520                       # Total ticks spent queuing
system.physmem.totMemAccLat               29355934520                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4616620000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13043.75                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31793.75                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.14                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.20                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.09                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.26                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.36                       # Average write queue length when enqueuing
system.physmem.readRowHits                     694872                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1406883                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.26                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.94                       # Row buffer hit rate for writes
system.physmem.avgGap                     18797853.22                       # Average gap between requests
system.physmem.pageHitRate                      77.68                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2251693080                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1228602375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3417133200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               5686258320                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3384921452640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1307306510865                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29947912845000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34652724495480                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.655841                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49820369752426                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1730532440000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    273552725074                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2312936640                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1262019000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3784755000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               5862520800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3384921452640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1309001038785                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29946426417000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34653571139865                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.672178                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49817859630672                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1730532440000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    276069619328                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    211321                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                211321                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15784                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       163511                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore           14                       # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples       211307                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean     0.170368                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev    58.877055                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-2047       211305    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::22528-24575            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       211307                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       179309                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       177365     98.92%     98.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         1663      0.93%     99.84% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607          114      0.06%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143           88      0.05%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679           58      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           14      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       179309                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples   -200578036                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean    -2.729096                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0      -747974796    372.91%    372.91% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::1       547396760   -272.91%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total   -200578036                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        163512     91.20%     91.20% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         15784      8.80%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       179296                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       211321                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       211321                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       179296                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       179296                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       390617                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    167775531                       # DTB read hits
system.cpu.dtb.read_misses                     155743                       # DTB read misses
system.cpu.dtb.write_hits                   152648275                       # DTB write hits
system.cpu.dtb.write_misses                     55578                       # DTB write misses
system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               42687                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1063                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    75520                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   8371                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     19881                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                167931274                       # DTB read accesses
system.cpu.dtb.write_accesses               152703853                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         320423806                       # DTB hits
system.cpu.dtb.misses                          211321                       # DTB misses
system.cpu.dtb.accesses                     320635127                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    122916                       # Table walker walks requested
system.cpu.itb.walker.walksLong                122916                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1122                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       110644                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       122916                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          122916    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       122916                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       111766                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 26583.507059                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-32767        56090     50.19%     50.19% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-65535        53429     47.80%     97.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-98303          753      0.67%     98.66% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::98304-131071         1184      1.06%     99.72% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-163839           19      0.02%     99.74% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::163840-196607          105      0.09%     99.83% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-229375           43      0.04%     99.87% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::229376-262143           54      0.05%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-294911           30      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::294912-327679           11      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-360447           20      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::360448-393215           11      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-425983            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::425984-458751            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-491519            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::491520-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       111766                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples   -853761296                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0      -853761296    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total   -853761296                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        110644     99.00%     99.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1122      1.00%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       111766                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       122916                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       122916                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       111766                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       111766                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       234682                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    894030670                       # ITB inst hits
system.cpu.itb.inst_misses                     122916                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               42687                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1063                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    53866                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                894153586                       # ITB inst accesses
system.cpu.itb.hits                         894030670                       # DTB hits
system.cpu.itb.misses                          122916                       # DTB misses
system.cpu.itb.accesses                     894153586                       # DTB accesses
system.cpu.numCycles                     103648924201                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   893481288                       # Number of instructions committed
system.cpu.committedOps                    1049881338                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             963989017                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 895873                       # Number of float alu accesses
system.cpu.num_func_calls                    52999943                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    136446519                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    963989017                       # number of integer instructions
system.cpu.num_fp_insts                        895873                       # number of float instructions
system.cpu.num_int_register_reads          1405913792                       # number of times the integer registers were read
system.cpu.num_int_register_writes          764688301                       # number of times the integer registers were written
system.cpu.num_fp_register_reads              1443674                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              760516                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            234750393                       # number of times the CC registers were read
system.cpu.num_cc_register_writes           234155899                       # number of times the CC registers were written
system.cpu.num_mem_refs                     320407593                       # number of memory refs
system.cpu.num_load_insts                   167768846                       # Number of load instructions
system.cpu.num_store_insts                  152638747                       # Number of store instructions
system.cpu.num_idle_cycles               100474792122.552063                       # Number of idle cycles
system.cpu.num_busy_cycles               3174132078.447939                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.030624                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.969376                       # Percentage of idle cycles
system.cpu.Branches                         199584978                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                 727639004     69.27%     69.27% # Class of executed instruction
system.cpu.op_class::IntMult                  2217476      0.21%     69.48% # Class of executed instruction
system.cpu.op_class::IntDiv                     99175      0.01%     69.49% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc             110553      0.01%     69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.50% # Class of executed instruction
system.cpu.op_class::MemRead                167768846     15.97%     85.47% # Class of executed instruction
system.cpu.op_class::MemWrite               152638747     14.53%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                 1050473844                       # Class of executed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16327                       # number of quiesce instructions executed
system.cpu.dcache.tags.replacements          10213653                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.965664                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           310015199                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          10214165                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             30.351497                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        3500615250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.965664                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999933                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          401                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1291569953                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1291569953                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    156758765                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       156758765                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    144836105                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      144836105                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       393576                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        393576                       # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       334400                       # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total       334400                       # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3672090                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3672090                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      3974747                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      3974747                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     301594870                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        301594870                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    301988446                       # number of overall hits
system.cpu.dcache.overall_hits::total       301988446                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      5315823                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       5315823                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2219045                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2219045                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1297249                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1297249                       # number of SoftPFReq misses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1232796                       # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total      1232796                       # number of WriteInvalidateReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       304342                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       304342                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      7534868                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        7534868                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      8832117                       # number of overall misses
system.cpu.dcache.overall_misses::total       8832117                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  84066704475                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  84066704475                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  66382286210                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  66382286210                       # number of WriteReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  32849513005                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::total  32849513005                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4463810234                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   4463810234                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       164000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 150448990685                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 150448990685                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 150448990685                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 150448990685                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    162074588                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    162074588                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    147055150                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    147055150                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1690825                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1690825                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1567196                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total      1567196                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3976432                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      3976432                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      3974749                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      3974749                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    309129738                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    309129738                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    310820563                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    310820563                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032799                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.032799                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015090                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.015090                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.767228                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.767228                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.786625                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.786625                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.076536                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.076536                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.024374                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.024374                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.028415                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.028415                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479                       # average WriteReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441                       # average WriteInvalidateReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441                       # average WriteInvalidateReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19967.037337                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17034.306802                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      7878976                       # number of writebacks
system.cpu.dcache.writebacks::total           7878976                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        16016                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        16016                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21118                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        21118                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70685                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        70685                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        37134                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        37134                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        37134                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        37134                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5299807                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5299807                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2197927                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2197927                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1295520                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1295520                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1232796                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1232796                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       233657                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       233657                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      7497734                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      7497734                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      8793254                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      8793254                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75489557525                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  75489557525                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  62224351540                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  62224351540                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20153084274                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20153084274                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  31000318995                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  31000318995                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2998156750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2998156750                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       161000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       161000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 137713909065                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 157866993339                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5751194250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5751194250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5618584250                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5618584250                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11369778500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11369778500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032700                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032700                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014946                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014946                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.766206                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.766206                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.786625                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786625                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.058760                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.058760                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024254                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024254                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028290                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.028290                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        80500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        80500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          13753173                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.880059                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           880276980                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          13753685                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             64.002991                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       35133104250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.880059                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999766                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999766                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         907784360                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        907784360                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    880276980                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       880276980                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     880276980                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        880276980                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    880276980                       # number of overall hits
system.cpu.icache.overall_hits::total       880276980                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     13753690                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      13753690                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     13753690                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       13753690                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     13753690                       # number of overall misses
system.cpu.icache.overall_misses::total      13753690                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 184520052183                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 184520052183                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 184520052183                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 184520052183                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 184520052183                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 184520052183                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    894030670                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    894030670                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    894030670                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    894030670                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    894030670                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    894030670                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015384                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.015384                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.015384                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.015384                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.015384                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.015384                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13416.039782                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13416.039782                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13416.039782                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13416.039782                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13416.039782                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13416.039782                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13753690                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     13753690                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     13753690                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     13753690                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     13753690                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     13753690                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 163860958817                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 163860958817                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 163860958817                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3211087000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3211087000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   3211087000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   3211087000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.015384                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.015384                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.015384                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.015384                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.015384                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.015384                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11913.963367                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11913.963367                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1292250                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65291.754390                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           27666738                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1355280                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            20.414038                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       7588597000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   308.197317                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   420.773838                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  6468.758735                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19751.242576                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.585064                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004703                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006420                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.098705                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.301380                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996273                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          297                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        62733                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          292                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          391                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2458                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5452                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54401                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004532                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.957230                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        264471216                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       264471216                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       371629                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       250715                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst     13674158                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      6553954                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total       20850456                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      7878976                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      7878976                       # number of Writeback hits
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       723057                       # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total       723057                       # number of WriteInvalidateReq hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         9863                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         9863                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1639498                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1639498                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       371629                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       250715                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     13674158                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8193452                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        22489954                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       371629                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       250715                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     13674158                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8193452                       # number of overall hits
system.cpu.l2cache.overall_hits::total       22489954                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         4157                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         4054                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        79532                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       275030                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       362773                       # number of ReadReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       509738                       # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total       509738                       # number of WriteInvalidateReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        35651                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        35651                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       512916                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       512916                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         4157                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         4054                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        79532                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       787946                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        875689                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         4157                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         4054                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        79532                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       787946                       # number of overall misses
system.cpu.l2cache.overall_misses::total       875689                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    357827500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    356872250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   6528298780                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  22994549799                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  30237548329                       # number of ReadReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data       123996                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::total       123996                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    554901623                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    554901623                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       159000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41601774937                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  41601774937                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    357827500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    356872250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   6528298780                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  64596324736                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  71839323266                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    357827500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    356872250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   6528298780                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  64596324736                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  71839323266                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       375786                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       254769                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst     13753690                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      6828984                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total     21213229                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      7878976                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      7878976                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1232795                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total      1232795                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        45514                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        45514                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2152414                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2152414                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       375786                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       254769                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     13753690                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      8981398                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     23365643                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       375786                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       254769                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     13753690                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      8981398                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     23365643                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.011062                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.015912                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005783                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.040274                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.017101                       # miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.413482                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.413482                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.783297                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.783297                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.238298                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.238298                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.011062                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.015912                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005783                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087731                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.037478                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.011062                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.015912                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005783                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087731                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.037478                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86078.301660                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88029.662062                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82083.925715                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83607.423914                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 83351.154383                       # average ReadReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data     0.243254                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     0.243254                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15564.826316                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15564.826316                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81108.358751                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81108.358751                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86078.301660                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88029.662062                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82083.925715                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81980.649354                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82037.485073                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86078.301660                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88029.662062                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82083.925715                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81980.649354                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82037.485073                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1107523                       # number of writebacks
system.cpu.l2cache.writebacks::total          1107523                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         4157                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4054                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        79532                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       275030                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       362773                       # number of ReadReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data       509738                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       509738                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        35651                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        35651                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       512916                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       512916                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         4157                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4054                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        79532                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       787946                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       875689                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         4157                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4054                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        79532                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       787946                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       875689                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    305614500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    305848750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   5531016720                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  19548409701                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  25690889671                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  16058529504                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  16058529504                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    625079648                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    625079648                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       135000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       135000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  35188398563                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  35188398563                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    305614500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    305848750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5531016720                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  54736808264                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  60879288234                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    305614500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    305848750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5531016720                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  54736808264                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  60879288234                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2585776000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5279091500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   7864867500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5180093000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5180093000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2585776000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10459184500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13044960500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.011062                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.015912                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005783                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.040274                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.017101                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.413482                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.413482                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783297                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783297                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.238298                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.238298                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.011062                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.015912                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005783                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087731                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.037478                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.011062                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.015912                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005783                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087731                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.037478                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437                       # average ReadReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        67500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        67500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq       21652739                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      21644705                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33710                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33710                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      7878976                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1339565                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1232795                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        45517                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        45519                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2152414                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2152414                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     27593630                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     28534080                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       622119                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       992785                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          57742614                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    880408660                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1158207750                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2038152                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3006288                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2043660850                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      470306                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     32992382                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.003506                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.059104                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3           32876724     99.65%     99.65% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4             115658      0.35%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       32992382                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    25622352750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1278000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   20698021683                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   14320653166                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     367823750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     617486750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40333                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40333                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp              29907                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231024                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231024                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353808                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492448                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           606968921                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148463571                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              174500                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115493                       # number of replacements
system.iocache.tags.tagsinuse               10.456626                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115509                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13157260299000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.510556                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.946069                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219410                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.434129                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653539                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039965                       # Number of tag accesses
system.iocache.tags.data_accesses             1039965                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8848                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8885                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8848                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8888                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8848                       # number of overall misses
system.iocache.overall_misses::total             8888                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1591055254                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1596127254                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       352500                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       352500                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19834612096                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  19834612096                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5424500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1591055254                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1596479754                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5424500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1591055254                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1596479754                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8848                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8885                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8848                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8888                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8848                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8888                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 179642.909848                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117500                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117500                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 179820.892179                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 179621.934518                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 179820.892179                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 179621.934518                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        109316                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                16121                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.780969                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8848                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8885                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8848                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8888                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8848                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8888                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3142000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1129796362                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1132938362                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       193500                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       193500                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14288050130                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14288050130                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3335500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1129796362                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1133131862                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3335500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1129796362                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1133131862                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        64500                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        64500                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 127490.083483                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 127490.083483                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              448489                       # Transaction distribution
system.membus.trans_dist::ReadResp             448489                       # Transaction distribution
system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
system.membus.trans_dist::Writeback           1214153                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       616398                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       616398                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            36221                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           36223                       # Transaction distribution
system.membus.trans_dist::ReadExReq            512353                       # Transaction distribution
system.membus.trans_dist::ReadExResp           512353                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4040402                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4170106                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335069                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       335069                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4505175                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    159663776                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    159833626                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14049088                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14049088                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               173882714                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3324                       # Total snoops (count)
system.membus.snoop_fanout::samples           2750930                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2750930    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2750930                       # Request fanout histogram
system.membus.reqLayer0.occupancy           107107000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5171500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         10418059043                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5433894864                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          151694929                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped

---------- End Simulation Statistics   ----------